JPH06334482A - Low pass filter - Google Patents

Abstract

PURPOSE:To obtain the low pass filter obtaining a coefficient with high accuracy from a short coefficient word length. CONSTITUTION:Equations of A0=a0.delta1, A1=a1.delta1, A2=a2.delta1, B1=delta2 (b1-2) and B2=delta2 (b2+1) are established, where a0, a1, a2 are input coefficients, b1, b2 are output feedback coefficients and delta1, delta2 are multiple of coefficients. An input signal Xn, data Xn-1 of one preceding sample obtained by delay devices 1, 2, and data Xn-2 of two preceding sample are multiplied respectively by A0, A1, A2 at coefficient devices 10, 11, 12 respectively and they are added by an adder 43 and multiplied by 1/delta1 at a coefficient device 31 and the result is fed to a synthesizer 46. data Yn-1 of one preceding sample and data Yn-2 of two preceding sample obtained by delay devices 3, 4 from an output Yn are multiplied respectively by B1, B2 at coefficient devices 21, 22 and added by an adder 44 and multiplied by 1/delta1 at a coefficient device 32 and the result is fed to the synthesizer 46. Then the data Yn-1 of one preceding sample from the output Yn obtained by the delay devices 3, 5 is doubled by a coefficient device 35 and fed to the synthesizer 46 together with data Xn-2 of two preceding sample obtained by the delay device 4 to provide an output signal Yn.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-precision low-pass filter device used in, for example, a DSP (Digital Signal Processor) circuit in audio equipment and the like, and particularly to a second-order IIR (Infinite Impulse Response) low-pass filter.
e) The present invention relates to a configuration for improving the accuracy of the filter coefficient when the filter is used.

[0002]

2. Description of the Related Art In order to make up for the lack of low-frequency reproduction capability of a reproduction speaker in an audio reproduction apparatus, a signal obtained by cutting an input signal with an LPF (low-pass filter) 52 having a cut-off frequency in a low frequency range as shown in FIG. In addition to the normal reproduction system (amplifier 53 and speaker 55 in the figure), there is a device (subwoofer output) driven by a dedicated amplifier 54 and speaker 56.

A DSP is used for LPF signal processing of such a device.
There is one that realizes an LPF by using a digital filter. As a digital filter that realizes this LPF, FIG.
The second-order IIR filter as shown in FIG. In FIG. 3, ¹ to 4 indicated by Z ⁻¹ are unit delay devices, 10
˜12, 21, 22 are coefficient multipliers, which are multipliers or attenuators. Further, a ₀ , a ₁ , a ₂ , b ₁ and b ₂ are filter coefficients of the coefficient units 10 to 12, 21 and 22, respectively, a ₀ , a ₁ and a ₂ are input coefficients, and b ₁ and b ₂ are Output feedback coefficients, δ ₁ and δ ₂ are coefficient multiplication factors, and 41 is an adder.

In the second-order IIR filter, X _n is an input data signal and Y _n is a composite signal from the adder 41, which is an output data signal. The input data signal X _n and the output data signal Y _n are delayed by the delay units 1 and 4 to become delayed data signals X _n-1 and Y _n-1 , and the signals X _n-1 and Y _n-1 are further delayed by the delay unit 2. , 5 to be delayed data signals X _n-2 and Y _n-2 .

The above data signals X _n , X _n-1 , X _n-2 ,
Y _n , Y _n-1 , and Y _n-2 are coefficient units 10 to 12, 21, and
Each filter coefficient set in 22 is multiplied to obtain an adder 4
It is synthesized in 1. Note that FIG. 4 is an output frequency characteristic diagram of the second-order IIR filter of FIG. When the above arithmetic processing is displayed by a mathematical expression, the following mathematical expression (1) is obtained.

[Formula 1] Y _n = a ₀ · X _n + a ₁ · X _n-1 + a ₂ · X _n-2 + b ₁ · Y _n-1 + b ₂ · Y _n-2 (1)

[0006]

However, the configuration in which each coefficient unit is multiplied by each filter coefficient as shown in FIG. 3 has a drawback that desired characteristics cannot be obtained if the cutoff frequency is considerably lowered. In particular,

(A) First, each filter coefficient of a _{0 to} b ₂ is calculated from a desired characteristic (transfer characteristic), but since the number of register digits holding these filter coefficients is finite, the actual An error occurs between the filter coefficient required for processing and the theoretical value. For example, assuming that the theoretical value of the filter coefficient a ₀ is 0.417531294, and the number of digits of the register is 8, the number of digits of a ₀ is rounded down and an error of 0.000000094 occurs. When the theoretical value of the filter coefficient becomes smaller in this way, the error rate increases and the accuracy decreases.

(B) In addition, a part of the filter coefficient is +1 to +1.
When the hardware is configured to handle only fixed-point numbers because it takes a value in the range of +2, each filter coefficient is halved in advance and then shifted (1 bit left shift). . However, this shift processing further deteriorates the accuracy of the filter coefficient. For example, if 0.84375 is displayed in fixed point, it is expressed as follows (in binary notation). 0.84375 = 0.5 + 0.25 + 0.0625 + 0.3125 = (1/2 ¹ ) × 1 + (1/2 ² ) × 1 + (1/2 ⁴ ) × 1 + (1/2 ⁵ ) × 1 = 011011 ( However, the most significant bit is a sign bit indicating a sign, and "0" means positive. Therefore, when the filter coefficient takes a value exceeding 1, the number is halved (2
In decimal notation, shift to the right by 1 bit), and a numerical value of 1 or less is processed. <Right Bit Shift> 011011 → 0011011 = 0.25 + 0.125 + 0.03125 + 0.015625 = 0.416875 Also, 0.84375 × (1/2) = 0.416875 After processing, the value halved is 2 Double (in binary display, shift 1 bit to the left). To reduce the numerical value of the filter coefficient to ½ in this way is to shift to the right by 1 bit in the binary number display. Since the length (number of digits) of the register is fixed, the least significant bit is truncated, resulting in deterioration of filter coefficient accuracy.

(C) Further, the second-order IIR filter is set to L
When used as a PF, as described above, the filter coefficients (a ₀ , a ₁ , a ₂ ) of the feedforward unit among the respective filter coefficients become extremely smaller than those of other filters, so that the same hardware (register) is used. Since the error to be processed in step 1 becomes large and the accuracy deteriorates, conventionally, in such a case, it was necessary to increase the length of the register holding the filter coefficient. Also,
In this case, as a method of processing without changing the register length, there is also a method of dividing the numerical value of the filter coefficient into upper and lower parts, holding them in a register, processing them separately (multiplication with data), and adding them later. . For example, the filter coefficient a ₀ = 0.4
1753129407, memory (or register) when processing a ₀ × X _n with input data X _n = 0.5
The values 0.417531 and 0.29407 are held in the respective columns and multiplication and addition are performed. However, although this method improves accuracy, it requires a register or a memory for holding the filter coefficient obtained by dividing the arithmetic processing into two times or dividing into upper and lower parts, which increases processing time and hardware scale. There was a problem.

The present invention has been made in view of the above drawbacks and problems, and an object of the present invention is to provide a low-pass filter capable of obtaining highly accurate coefficient values with a short coefficient word length.

[0011]

In order to achieve the above object, a low-pass filter according to the present invention is provided with a plurality of first delay data obtained by inputting an input data signal and delaying the input data signal with a plurality of different delay times. And a first delay means for outputting the input signal and the first delayed data signal are attenuated by a result obtained by multiplying a predetermined different coefficient by a first magnification, and a plurality of first attenuated signals corresponding to the respective signals are output. The first attenuating means for producing the first attenuating signal,
And a second delay means for outputting a plurality of second delay data signals obtained by delaying the combined output signal by a plurality of different delay times, and a second delay data signal. A second attenuating means for attenuating the predetermined coefficient different from the first attenuating means by the second multiplication factor and outputting a plurality of second attenuating signals corresponding to the respective signals; Second combining means for outputting a result of multiplying the second combined signal obtained by combining by the reciprocal of the second scaling factor, and a plurality of third delayed data signals obtained by delaying the combined output signal with a plurality of different delay times A third delay means, a delay data output means for outputting a result obtained by multiplying the third delay data signal by a predetermined value, an output of the first and second combining means, and an output of the delay data output means. Output signal synthesizing means for obtaining a synthesized output signal by Characterized in that it has a.

[0012]

With the above construction, the low-pass filter of the present invention is the first
The delay means inputs the input data signal and outputs the plurality of first delay data obtained by delaying the input data signal by a plurality of different delay times, and the first attenuating means outputs the input signal and the first delay data signal by a predetermined difference. A first combined signal obtained by performing attenuation processing on the result of multiplying the coefficient by the first multiplication factor, outputting a plurality of first attenuated signals corresponding to the respective signals, and combining the first attenuated signals by the first combining means. Is multiplied by the reciprocal of the first scaling factor, and the result is output. The second delay means outputs a plurality of second delayed data signals obtained by delaying the combined output signal with a plurality of different delay times, and the second attenuating means outputs the second delayed data signals by a predetermined value different from the first attenuating means. The result obtained by multiplying the coefficient by the second magnification is subjected to attenuation processing, a plurality of second attenuated signals corresponding to the respective signals are output, and a second combined signal obtained by combining the respective second attenuated signals by the third delay means is obtained. The result of multiplying the reciprocal of the second scaling factor is output. Further, the delay data output means outputs a plurality of third delay data signals obtained by delaying the combined output signal with a plurality of different delay times, outputs the result of multiplying the third delayed data signal by a predetermined value, and outputs the output signal combining means. Thus, the outputs of the first and second combining means and the output of the delay data output means are combined to obtain a combined output signal.

[0013]

EXAMPLES Table 1 below shows filter coefficients a ₀ , a ₁ , and a when the LPF is designed by the second-order IIR filter and the cutoff frequency Fc is in the low frequency band of 50 Hz to 200 Hz.
The values (theoretical values) of ₂ , b ₁ and b ₂ are shown.

[0014]

[Table 1]

From Table 1, the characteristics of these coefficient values are as follows:
a _0, a _1, a is extremely small value of _2, b ₁ is a value as close as possible to -2, b ₂ is a value as close as possible to 1, it can be mentioned. Considering these, the formula (1) is modified as shown below to obtain the formula (2).

[0016]

[Formula 2] Y _n = a ₀ · X _n + a ₁ · X _n-1 + a ₂ · X _n-2 + b ₁ · Y _n-1 + b ₂ · Y _n-2 (1)

[Formula 3] Y _n = a ₀ · X _n + a ₁ · X _n-1 + a ₂ · X _n-2 + (b ₁ -2) · Y _n-1 + (b ₂ +1) · Y _n-2 +2・ Y _n-1 + Y _n-2 (2)

[Formula 4] Y _n = (a ₀ · X _n + a ₁ · X _n-1 + a ₂ · X _n-2 ) δ ₁ · (1 / δ ₁ ) + {(b ₁ -2) · Y _n-1 + (B ₂ +1) · Y _n-2 } δ ₂ + (1 / δ ₂ ) + 2Y _n-1 + Y _n-2 (3)

[Formula 5] Y _n = (a ₀ · δ ₁ · X _n + a ₁ · δ ₁ · X _n-1 + a ₂ · δ ₁ · X _n-2 ) (1 / δ ₁ ) + {δ ₂ (b ₁ -2) · Y _n-1 + δ ₂ (b ₂ +1) · Y _n-2 } (1 / δ ₂ ) + 2Y _n-1 + Y _n-2 (4)

[0017]

[Formula 6] Y _n = (a ₀ · X _n + A ₁ · X _n-1 + A ₂ · X _n-2 ) (1 / δ ₁ ) + (B ₁ · Y _n-1 + B ₂ · Y _n-2 ) (1 / δ ₂ ) + 2Y _n-1 + Y _n-2 (5) where A ₀ = a ₀ · δ ₁ , A ₁ = a ₁ · δ ₁ , A ₂ = a ₂ · δ ₁ , B ₁ = δ ₂ (b ₁ -2), B ₂ = δ ₂ (b ₂ +1)

Specifically, a ₀ , which has an extremely small value,
The coefficient values A ₀ , A ₁ , and A ₂ obtained by multiplying a ₁ and a ₂ by δ ₁ are held in a register, and the value is multiplied by (1 / δ ₁ ) after the feed-forward processing is performed using this value. . Thus, δ ₁
By multiplying and holding it in a register and using it for processing, the value of the lower digit of the coefficient value, which has been truncated in the operation process until now due to the restriction of the register length (number of digits), will be used, so the accuracy of operation will be improved. improves.

Further, the feedback unit sets the coefficient value to B ₁ ,
After converting to the form of B ₂ and calculating, multiply by 1 / δ, and 2 · Y _n-1
And (-1) · Y _n-2 are added later (or Y _n-2 is subtracted). (If this processing method is used, the value of the lower digit that has been truncated due to the limitation of the number of register digits will be used. The accuracy is improved because it comes to be known).

FIG. 1 is a second-order IIR embodying equation (2).
It is a block diagram of a filter (low-pass LPF), ¹ to 6 indicated by Z ⁻¹ are unit delay devices, delay devices 1 and 2 are first delay means, delay devices 3 and 4 are second delay means The delay devices 5 and 6 correspond to the third delay means. Reference numerals 10 to 12, 21 and 22 are coefficient multipliers, and multipliers or attenuators are used for the coefficient multiplier 10
.About.12 correspond to the first attenuator, and the coefficient units 21 and 22 correspond to the second attenuator. Further, 31, 32, and 35 are multipliers, and the multiplier 35 corresponds to delay data output means, and A ₀ ,
A ₁ , A ₂ , B ₁ , and B ₂ are coefficient units 10, 11, 12, 21,
The filter coefficients of 22 are 43 and 44, which are adders, and 46 is a combiner, which corresponds to output signal combining means. Also, A
₀ = a ₀ · δ ₁ , A ₁ = a ₁ · δ ₁ , A ₂ = a ₂ · δ ₁ , B ₁ = δ
₂ (b ₁ -2), B ₂ = δ ₂ (b ₂ +1), a ₀ , a ₁ , a ₂ are input coefficients, b ₁ and b ₂ are output feedback coefficients, and δ ₁ and δ ₂ are coefficients. It is a magnification. The coefficient multipliers δ ₁ and δ ₂ have different suitable values depending on the desired filter characteristics.

The adder 43 and the multiplier 31 are the first synthesizing means, the adder 44 and the multiplier 32 are the second synthesizing means, and one sample past data obtained by the input signal X _n and the delay unit 1 X _n-1 and the two-sample past data X _n-2 obtained by the delay unit 2 are coefficient units 10, 11, and 12, respectively.
Are multiplied by A ₀ , A ₁ and A ₂ and then added by the adder 43. This signal is further multiplied by 1 / δ ₁ in the coefficient unit 31, and then added to the combiner 46.

On the other hand, one sample past data Y _{n-1 of} the output Y _n obtained by the delay unit 3 and 2 obtained by the delay unit 4
The sample past data X _n-2 are coefficient units 21 and ₂ , respectively.
The value is multiplied by B ₁ and B ₂ by ₂ , and then added by the adder 44. This signal is further multiplied by 1 / δ ₁ in the coefficient unit 32 and then added to the combiner 46. Further, the output Y _n obtained by the delay unit 5 is the data Y _n-1 of one sample in the past, and is 2 by the coefficient unit 35.
Double sample past data X obtained by the delay 6
_It is added to the combiner 46 together with _n-2 . The adder 44 synthesizes the outputs of the coefficient units 31, 32, 35 and the delay unit 6 and outputs it as an output signal Y _n .

As a result, the value of each coefficient filter in Table 1 is represented by the quantization step (the minimum step in the case of being expressed in k-bit binary data in decimal as shown in Table 2 below, k Values (δ ₁ · a ₀ , δ ₁ · a ₁ , which are the minimum values that can represent binary data of bits)
δ ₁ · a ₂ , δ ₂ (b ₁ -2), δ ₂ (b ₂ +1)), and filter calculation is possible. The upper part of Table 2 shows coefficient values δ ₁ · a ₀ , δ ₁ · a ₁ , δ ₁ · a ₂ , δ ₂ (b ₁ −
2), δ ₂ (b ₂ +1) is a decimal expression and corresponds to the cutoff frequency Fc displayed in the left column of the LPF table. The lower row is a hexadecimal representation of the coefficient value, and the coefficient value is D
It is stored in the coefficient RAM of the SP. The coefficient RAM stores coefficient values as binary data, and the stored coefficient values are read out at the time of multiplication in each coefficient unit and multiplied by each signal.

[0024]

[Table 2]

Next, how to select the coefficient multiplying factor (δ ₁ , δ ₂ ) is usually the DSP (although the coefficient word length is short) rather than the coefficient word length (the word length of the register such as the multiplier and the adder). Since this is longer, several bits (about 2 to 6 bits) are secured as an overflow margin. Therefore, data slightly larger than the output data word length can be calculated during the calculation.

Since the coefficient accuracy is improved when the filter coefficient is closer to 1 as an absolute value, the coefficient magnification varies depending on the coefficient value. In the conventional method, as is clear from Table 1, the input coefficient (a ₀ , a ₁ , a ₂ ) is equal to the output feedback coefficient (b ₁ −
1, b ₂ +0.5), the multiplication factor necessary for maintaining the calculation accuracy by the DSP having a short coefficient word length cannot be obtained, and the calculation including many errors is performed, so that the desired characteristic is obtained. However, according to the present invention, since the input coefficient and the output feedback coefficient can be multiplied by independent coefficient multiplication factors, the calculation error can be reduced and a desired frequency characteristic can be obtained. As shown in FIG. Can be obtained.
In this way, since the coefficient scale factor differs between the input coefficient and the output feedback coefficient, the required quantization step is given to each filter coefficient.

FIG. 2 is a frequency characteristic diagram of the low-pass LPF of this embodiment (FIG. 1). It can be seen from FIG. 2 that the characteristics (see FIG. 4) that cannot be realized by the conventional method are realized.

[0028]

As described above, according to the low pass filter of the present invention, it is possible to realize a low pass filter with a short coefficient word length. Further, since the input coefficient and the output feedback coefficient can be multiplied by independent coefficient multiplication factors, a calculation error can be reduced and a desired frequency characteristic can be obtained. Therefore, a highly accurate coefficient value can be obtained in the low pass filter.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a second-order IIR filter (low-pass filter) according to the present invention.

FIG. 2 is a frequency characteristic diagram of the low pass filter of FIG.

FIG. 3 is a conventional example of a second-order IIR filter.

4 is an output frequency characteristic diagram of the second-order IIR filter of FIG.

FIG. 5 is an example of an audio device using a second-order IIR filter for low-pass LPF.

[Explanation of symbols]

1-6 Delay device 10-12, 21, 22 Coefficient device (attenuating means) 31, 32, 35 Multiplier 43, 44 Adder 46 Combiner (output signal combining means) A ₀ , A ₁ , A ₂ , B ₁ , B ₂ filter coefficient

Claims (1)

[Claims] 1. A first delay means for inputting an input data signal and outputting a plurality of first delay data obtained by delaying the input data signal with a plurality of different delay times, and the input signal and the first delay data signal. It is obtained by synthesizing the first attenuating means for attenuating the result obtained by multiplying a predetermined different coefficient by the first magnification and outputting a plurality of first attenuating signals corresponding to the respective signals, and the first attenuating signals. First combining means for outputting a result of multiplying the first combined signal by the reciprocal of the first scaling factor; and second delay for outputting a plurality of second delayed data signals obtained by delaying the combined output signal with a plurality of different delay times. Means for attenuating the second delayed data signal by a result of multiplying a second coefficient by a predetermined coefficient different from the first attenuating means, and outputting a plurality of second attenuated signals corresponding to the respective signals. 2 damping means, each of the second damping Second synthesizing means for outputting a result obtained by multiplying a second synthesized signal obtained by synthesizing signals by the reciprocal of the second scaling factor, and a plurality of third delay data obtained by delaying the synthesized output signal with a plurality of different delay times. A third delay means for outputting a signal, a delay data output means for outputting a result obtained by multiplying the third delay data signal by a predetermined value, an output of the first and second combining means, and a delay data output means A low pass filter comprising: an output signal synthesizing means for synthesizing an output and a synthesized output signal.