JPH06324894A - Error correction circuit for computer - Google Patents

Abstract

PURPOSE:To automatically correct the one-bit error of memory data by constituting of plural parity bit adding circuits and plural parity check circuits, adding a parity bit at every number data, and detecting which any one bit of data shows abnormality (inversion). CONSTITUTION:The parity bit adding circuit 7a adds parity to the bits of the data D0-D2. Similarly, the parity bit adding circuit 7b adds the parity to the bits of the data D3-D5, and the parity bit adding circuit 7c adds it to the bits of the data D0, D3, and D6, and the parity bit adding circuit 7b adds it to the bits of the data D1, D4, and D7. In such constitution, for example, the data in the parity bit adding circuits 7b, 7d become a parity error when the data 4 are inverted. In other works, the fact that which bit of the data is inverted can be detected from the data in four parity bit adding circuits 7a-7d. The detection and correction of an inverted bit are performed by a parity check/data correction circuit 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction circuit for automatically correcting data errors when reading memory data of a computer.

[0002]

2. Description of the Related Art The structure of a conventional error correction circuit is shown in FIG. In FIG. 3, 1 is an arithmetic unit, 2 is a data bus, 3 is an address bus, 4 is an address decoding circuit for inputting and decoding an address signal output from the arithmetic unit 1, and 5 is a data store from the arithmetic unit 1. The memory 5a is usually a master memory used when the arithmetic unit 1 reads data from the memory, 5b is a slave memory used when an error occurs in the data of the master memory, 6 is an error correction circuit, 7 Is a parity bit addition circuit for inputting data from the arithmetic unit 1 and adding parity, 8 is a parity bit memory for storing the parity data generated by the parity bit addition circuit 7, and 9 is a parity bit memory 8
Parity bit data output from the main memory 5a, 10 data read from the main memory 5a, 11 main data 5a
Data 10 and parity bit data 9 read from
A parity check circuit for inputting the data of 1 to perform a parity check, and 12 outputs the data of the main memory 5a to the data bus 2 or outputs the data of the slave memory 5b to the data bus based on the result of the parity check circuit 11. A selector switching signal for switching the input of the selector 12, 14 is a selector switching signal for switching the input of the selector 12, 14 is an output data from the slave memory 5b, and 15 is a chip select signal output from the address decoding circuit 4.

First, the case of writing data in the main memory 5a and the slave memory 5b will be described. When the address and data to be written to the main memory 5a and the slave memory 5b are output from the arithmetic unit 1, the address is input to the address decoding circuit 4 via the address bus 3. The address decode circuit 4 generates the chip select signal 15,
The data is input to the master memory 5a and the slave memory 5b. The data is input to the master memory 5a and the slave memory 5b via the data bus 2. At the same time, the parity bit addition circuit 12 inputs the parity bit data to the parity bit memory 8. In this way, when writing data to the master memory 5a and the slave memory 5b, the same data is written at the same address.

When reading data from the master memory 5a and the slave memory 5b, the data of the same address is read from the master memory 5a and the slave memory 5b. At the same time, the parity bit data 9 is also sent from the parity bit memory 8.
Is read. The data 10 and the parity bit data 9 read from the main system memory 5a are input to the parity check circuit 11. The parity check circuit 11 checks the parity of the data 10 read from the main memory 5a. If normal, the selector 12 outputs the data 10 read from the main system memory 5a to the data bus 2 without switching. Parity check circuit 1 if abnormal
The selector switching signal 13 from 1 is output to the selector 12 and switched to output the data 14 read from the slave memory 5b to the data bus 2. Therefore, if the data of the main memory 5a is abnormal, the data of the slave memory 5b is used so that the wrong data is not used.

[0005]

As described above, the conventional error correction circuit must wait for two sets of memories in the same address area, and when data becomes abnormal at the same address in two sets of memories, There was a problem that errors could not be corrected.

The present invention has been made in order to solve such a problem, and it is an object of the present invention to provide an error correction circuit capable of correcting memory data when the memory data becomes abnormal (inverted) by one bit. Has an aim.

[0007]

According to the present invention, an error correction circuit is composed of a plurality of parity bit addition circuits and a plurality of parity check circuits, and a parity bit is added every several bits of data, and which one bit of data is abnormal. It is to detect whether (reversed).

[0008]

According to the present invention, by adding a plurality of parity bits to data, it is detected which one bit of the data has become abnormal (inverted), and the data is corrected by correcting the bit.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an overall configuration diagram showing an embodiment of an error correction circuit according to the present invention. 1 to 15 are exactly the same as the above-mentioned conventional example. 16 is data read from the memory 5, 17 is data read from the memory 5
And parity bit data 9 are input to perform a parity check and correct the error data bit correctly.

The error correction circuit 6 detects and corrects a 1-bit error, and the number of parity bits added to the data bit length is shown in "Equation 1".

[0011]

[Equation 1]

In Equation 1, y is the number of data bits, a is the value of the integer part of the square root of the number y of data bits, and the number x of parity bits is a + b.

Assuming that the data bit length is 8 bits, the number of parity bits will be 4 bits from "Equation 2".

[0014]

[Equation 2]

The correspondence between the data bits D0 to D7 of the data and the four parity bit adding circuits 12 is shown in FIG. The parity bit adding circuit 7a is used for data D0, D
Parity is added to bits 1 and D2. Similarly,
The parity bit adding circuit 7b is used for data D3, D4, D
5, the parity bit adding circuit 7c outputs data D0, D
3 and D6, the parity bit adding circuit 7d outputs data D
Parity is added to 1, D4 and D7. By doing so, for example, if the data D4 is inverted, the data of 7b and 7d of the parity bit adding circuit 7 becomes a parity error. Further, if only 7a of the parity bit adding circuit 7 results in a parity error, it is understood that the data of D2 is inverted. In this way, which bit of the data is inverted can be detected from the data of the four parity bit adding circuits 7. The parity check / data correction circuit 17 detects the inverted bit and corrects the inverted bit.

[0016]

As described above, the error correction circuit 6 is composed of the plurality of parity bit addition circuits 7 and the parity check / data correction circuit 17, the parity bit is added for every several bits of data, and the data is read from the memory 5. Sometimes by checking the parity bit, the error bit of the data can be identified and the bit data corrected.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing bit allocation of a parity bit adding circuit of the present invention.

FIG. 3 is a diagram showing a configuration of a conventional error correction circuit.

[Explanation of symbols]

 1 arithmetic unit 2 data bus 3 address bus 4 address decode circuit 5 memory 6 error correction circuit 7 parity bit addition circuit 8 parity bit memory 9 parity bit data 10 data read from main memory 11 parity check circuit 12 selector 13 Selector switching signal 14 Data read from slave memory 15 Chip select signal 16 Data read from memory 17 Parity check / data correction circuit

Claims (1)

[Claims] 1. An arithmetic unit, a memory for storing the data, an error correction circuit for correcting the data when the arithmetic unit reads the data from the memory and corrects the data, and an address from the arithmetic unit. In an error correction circuit of a computer that is composed of an address decoding circuit that decodes a signal and sends a chip select signal to the memory, a plurality of parities that add a parity bit to every few bits of data when writing data from the arithmetic unit to the memory A bit addition circuit, a parity bit memory that stores the parity bit data from the plurality of parity bit addition circuits, and parity bit data and memory data from the parity bit memory are read and a parity check is performed to detect a 1-bit error. Parity check / data correction times for automatic correction An error correction circuit for a computer characterized by being configured with a path.