JPH06311480A - Processing system and processor for digital video signal - Google Patents

Abstract

PURPOSE:To improve reproducing picture quality by reducing the number of erroneous picture elements on a screen as much as possible when errors are generated in data words composed of plural low-order samples in a device for recording and reproducing component video signals. CONSTITUTION:The low-order samples 7, 8 and 9 of a luminance signal component Yc and two color difference signal components Cb and Cr sampled at a same position are stored in the address indicated by the same channel number 20, segment number 23 and sample number 26 of memories for the respective components of the memory 6 for low-order and the low-order sample 10 of a Yi component is stored in the address indicated by the channel number 21, segment number 24 and sample number 30 of the memory for the Yi component of the memory 6 for the low-order. At the time, the sample number 30 is a value shifted from the sample number 26 for a fixed value. At the time of reading the stored data, the stored data are read from the same address of the memories for the respective components of the memory 6 for the low-order.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal processing apparatus in an apparatus for recording / reproducing or transmitting a digitized video signal, for example, an apparatus such as a digital VTR.

[0002]

2. Description of the Related Art A VTR for recording / reproducing a component digital video signal is standardized as D-1. For details of D-1, for example, as the first document, SMPTE 227M 19-mm type D-1 cassette-helical d
ata and control records (SMPTE Journal, March 199
2) And as the second document, "D-1 Digital VTR
Format ”(Broadcasting Technology, Vol.43, No.12, Novembe
r 1990). D-1 is CCIR601
It is a digital VTR that quantizes a signal sampled by the so-called 4: 2: 2 system shown in the recommendation of No. 8 into 8 bits and records and reproduces it.

Here, the 4: 2: 2 method means a luminance signal and 2
Two color difference signals are 13.5MHz and 6.75MH respectively
z sampling method, aspect ratio is 4: 3, and scanning method is 525 lines / 60 Hz or 625 lines /
According to the current television signal of 50 Hz.

On the other hand, there is a movement to increase the aspect ratio to 16: 9 while keeping the scanning system as it is.
-Methods such as II are being studied. Here, the following method will be considered and this will be referred to as extended 4: 2: 2.

That is, in extended 4: 2: 2, the number of scanning lines in the vertical direction is set to the same number as 4: 2: 2,
In order to set the aspect ratio to 16: 9, the horizontal length of the screen is set to 4/3 times that of the 4: 2: 2 method. Therefore,
The sampling frequency for A / D conversion is 4: 2: 2.
If it is multiplied by / 3, the interval between the sample points on the screen is 4:
Same as the 2: 2 method. Therefore, in the extended 4: 2: 2, the sampling frequencies of the luminance signal and the two color difference signals are respectively set to 18 MHz and 9 MHz, which are 4/3 times the sampling frequency of the 4: 2: 2 method, and the number of quantization bits is 8. Bit.

When the digital video signal obtained by such an extended 4: 2: 2 system is used as the first component digital video signal, the data rate required for the digital VTR for recording this is expressed by the bit rate. hand,

[0007]

[Equation 1]

[0008] On the other hand, the data rate of D-1 is

[0009]

[Equation 2]

Therefore, the digital VTR for recording the first component digital video signal is D
It is necessary to use a recording / reproducing device having a data rate higher than -1.

Therefore, a new digital VTR for recording / reproducing the above-mentioned first component digital video signal will be newly considered and hereinafter referred to as DX.

At this time, the signal sampled by the 4: 2: 2 system is widely used at present, and it is desirable that the signal sampled by the 4: 2: 2 system can be recorded in the DX as well. . Therefore, consider a digital video signal in which each sample is quantized with 10 bits in the 4: 2: 2 system, and this will be referred to as a second component digital video signal. The data rate in this case is

[0013]

[Equation 3]

And becomes a value relatively lower than the data rate of the first component digital video signal.

Therefore, the data consisting of 10 bits per sample sampled at 13.5 MHz of the second component digital video signal is
A digital VTR capable of recording both of the extended 4: 2: 2 and 4: 2: 2 systems is constructed by encoding data consisting of 8 bits per word at a clock rate of Hz and recording the data on DX. be able to.

As described above, in order to encode a sample quantized with 10 bits into a word consisting of 8 bits, each of the conventional 10-bit samples is divided into upper 8 bits and lower 2 bits, and consecutively. The lower 2 bits of the four samples to be processed are collectively converted into one 8-bit word (Japanese Patent Laid-Open No. 60-262279).

[0017]

However, in a digital VTR, error correction is usually performed in units of one word. Therefore, in the conventional method as described above, when an error occurs in the process of recording / reproducing or transmitting, one word of With respect to the error, all the lower 2 bits of 4 consecutive samples become erroneous, resulting in an error of 4 consecutive samples. Therefore, there is a drawback that the image quality is greatly deteriorated because an error occurs near the screen.

In view of the above points, the present invention provides a digital video signal processing apparatus capable of improving reproduced image quality by reducing the number of samples that cause an error on a television screen with respect to an error of one word. The purpose is to provide.

[0019]

A processing method of a digital video signal according to the present invention considers two positive integers n and m,
When n> m and m is divisible by (nm), f = m /
(Nm), the luminance signal component of the second component digital video signal for the first component digital video signal quantized with m bits and the second component digital video signal quantized with n bits For each of the two color-difference signal components, sample data consisting of n bits each is composed of data consisting of m bits from the most significant bit and (nm) from the least significant bit.
When divided into data consisting of bits and called the upper sample and the lower sample, each of the f samples including the three lower samples of the luminance signal component and the two chrominance signal component samples sampled at the same position on the television screen. It is characterized in that the lower sample forms a word of m bits.

Also, the digital video signal processing apparatus according to the present invention considers two positive integers n and m, and when n> m, m
Is divisible by (n−m), f = m / (n−m), and the first component digital video signal quantized by m bits and the second component digital video quantized by n bits The signal and the luminance signal component of the second component digital video signal and 2
For each of the two color difference signal components, the sample data consisting of n bits is divided into a sample consisting of m bits from the most significant bit and a sample consisting of (n−m) bits from the least significant bit, and each is divided into an upper sample and a lower sample. When referred to as a sample, an upper memory for storing an upper sample for one horizontal scanning period, a lower memory for storing a lower sample for one horizontal scanning period, an upper sample and a lower sample for an upper memory and a lower sample, respectively. A write address generation circuit for generating an upper write address and a lower write address for writing to a memory, and an upper read address and a lower read address for reading a m-bit word from the upper memory and the lower memory, respectively. A read address generation circuit for
A m-bit word output from the upper memory and a m-bit word output from the lower memory have a multiplexer for selecting either one, and are sampled at the same position on the television screen. It is characterized in that three lower samples of the luminance signal component and the two color difference signal components are included in the same m-bit word output from the lower memory.

[0021]

In the digital video signal processing system according to the present invention, the first component digital video signal quantized with m bits and the luminance signal component of the second component digital video signal quantized with n bits are used. Each of the two color difference signal components is divided into an upper sample consisting of m bits from the most significant bit and a lower sample consisting of (n−m) bits from the least significant bit, and f
The lower samples of the samples are combined to make one m-bit sample.

At this time, the three lower samples of the luminance signal component and the two chrominance signal components sampled at the same position on the television screen are put in the same one m-bit sample word. As a result, when one m-bit word composed of lower order samples fails during reproduction, the lower order samples of the luminance signal component and the two color difference signal components sampled at the same position on the TV screen simultaneously fail. .

Therefore, the error of the three lower samples becomes the error of one pixel on the television screen, so that the number of error pixels is reduced in the entire screen, and the reproduction image quality is improved.

Further, in the digital video signal processing apparatus according to the present invention, the writing of the upper sample to the upper memory is performed as a word consisting of m bits in accordance with the upper write address, and the reading from the upper memory is m bits. The lower sample is written to the lower memory as a word consisting of (n−m) bits according to the lower write address, and the lower memory is read from the lower memory as a lower sample of f samples. Is performed according to the lower read address as an m-bit word composed of

The lower write address is set to the same address for the three lower samples of the luminance signal component and the two color difference signal component samples sampled at the same position on the television, so that the lower memory is sampled at the same position. The three subsamples taken are placed in one m-bit word.

By reading the m-bit word arranged in the lower memory and switching the m-bit word output from the upper memory and the m-bit word output from the lower memory by the multiplexer, continuous m-bit words are read. The encoded data is obtained as a word string of.

As a result, as described above, it is possible to reduce the number of pixels in error on the television screen when an error occurs during reproduction and improve the reproduced image quality.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the embodiments of the present invention described below, a luminance signal component as a first component digital video signal is quantized with a sampling frequency of 18 MHz and a quantization bit number of 8 bits, and a chrominance signal component is sampled with a sampling frequency of 9 bits.
Consider a component digital video signal based on the above-mentioned extended 4: 2: 2 system which is quantized at 8 MHz and a quantization bit number of 8 bits. In the first component digital video signal, the number of effective samples per line is 960 samples for the luminance signal component and 480 samples for the two color difference signal components.

On the other hand, as the second component digital video signal, the luminance signal component is quantized with a sampling frequency of 13.5 MHz and the number of quantization bits is 10 bits, and the chrominance signal component is sampled at a frequency of 6.75 MH.
z, the number of quantization bits is 10 bits, and the above-mentioned 4 is performed:
Consider a component digital video signal according to the 2: 2 system. In the second component digital video signal, the luminance signal component is 720 samples and the two color difference signal components are 360 samples.

Hereinafter, a mode for recording the first component digital video signal sampled by the extended 4: 2: 2 system will be described as an 18 MHz mode and the second component digital video signal sampled by the 4: 2: 2 system will be described. The recording mode will be referred to as a 13.5 MHz mode.

FIG. 8 shows the structure of sampling points in the 4: 2: 2 system and the extended 4: 2: 2 system. As described above, the sampling frequency of the luminance signal component is twice the sampling frequency of the two chrominance signal components in both the 4: 2: 2 method and the extended 4: 2: 2 method. A point 201 where the color difference signal component is sampled and a point 202 where only the luminance signal component is sampled appear alternately, and each of them constitutes one pixel.

Here, when the effective pixels are sequentially numbered for each horizontal scanning period and expressed as pix, as shown in FIG. 8, the luminance signal components Y and 2 are assigned to the pixels having the even pixel number pix. Samples of two color difference signal components Cb and Cr belong to
Only the sample of the luminance signal component Y belongs to the pixel having the odd pixel number pix. Therefore, the luminance signal component Y is set to the component Yc and the pixel number pix which belong to the pixel of which the pixel number pix is an even number.
Will be divided into components Yi belonging to odd-numbered pixels. In this way, the first digital video signal is considered to have 480 samples of Yc, Cb, Cr, and Yi components per line.

In order to record such a high bit rate data, usually, a plurality of heads are used at the same time for recording, so that the data rate for each head is reduced. The signal processing is divided into the same number of signal flows corresponding to the plurality of heads operating at the same time, and this will be referred to as a recording channel hereinafter.

In a normal VTR, data is arranged on the tape in units of one field to enable editing, but in order to reduce the recording density on the tape, one field of data is recorded for all recording channels. Is divided into a plurality of tracks and arranged. Hereinafter, a set of data corresponding to one track of each recording channel will be referred to as a segment.

In the embodiment of the present invention, as a digital VTR for recording / reproducing the first component digital video signal, when the number of recording channels is NCh, NCh = 4 channels, and the number of segments per field is NSeg. When the 525/60 system is NSeg = 3 segments, when the 625/50 system is N
Consider a digital VTR where Seg = 4 segments.

As described above, Yc, Cb, Cr,
The Yi component sample is divided into four recording channels. At this time, samples of each component are divided into four channels in order to avoid concentration of errors on one component when some channels are not reproduced. At this time, Yc, Cb, Cr belonging to the same pixel
The division shall be performed so that the component samples are in the same channel.

In this way, each data divided into 4 channels is further divided into 3 or 4 segments. At this time, it is assumed that the Yc, Cb, and Cr component samples belonging to the same pixel are divided into the same segment.

An example of division into such recording channels and segments is shown in FIG. 525 for (a) and (c)
/ 60 system, and (b) shows the 625/50 system. In the figure, pix is an effective pixel number in the horizontal direction. As described above, Yc,
The Cb and Cr component samples belong, and the Yi component samples belong to the pixels whose pix is an odd number. ch represents the channel number of the recording channel to which the sample data belonging to each pixel is distributed, and is an integer from 0 to NCh-1. seg represents the segment number of the segment to which the sample data belonging to each pixel is distributed, and is an integer from 0 to NSeg-1. splSeg is a sample number sequentially added to the sample data of each component of each segment of each recording channel.

In (a) and (c), all the combinations of ch and seg occur only once in the pixels where pix is in the range of 0 to 23 and pix is an even number. The same applies to pixels whose pix is an odd number. In the range where pix is 24 and beyond, the same c as 24 pixels in the range where pix is 0 to 23
The array of h and seg is repeated every 24 pixels. Also,
In (b), pix is in the range of 0 to 31, and even if pix is an even-numbered pixel
All combinations of seg and seg appear only once, and the same array of ch and seg is repeated at a cycle of 32 pixels. Therefore, all components are evenly distributed in 4 channels x 3 or 4 segments. Also, samples of Yc, Cb, and Cr components belonging to the same pixel with an even pix are distributed to the same ch and seg. As shown in (a) and (c), there are many distribution methods in which samples of Yc, Cb, and Cr components belonging to the same pixel are recorded in the same segment of the same channel. , Cb,
This is effective when performing a distribution method in which samples of Cr components are recorded in the same segment of the same channel.

As described above, by dividing each line into 4 channels × 3 or 4 segments, one field as a whole can be divided into 4 channels × 3 or 4 segments. Therefore, in 18MHz mode, 1
One of the Yc, Cb, Cr, and Yi components belonging to the line
One component sample is one segment of one recording channel in case of 525/60 system,

[0041]

[Equation 4]

When the sample is the 625/50 system,

[0043]

[Equation 5]

Samples are assigned. In contrast to the above-described first component digital video signal recording system, the second component digital video signal processing system of the present invention records the second component digital video signal by converting 10-bit samples into 8-bit samples. An example is shown below.

In the second digital video signal, the effective pixels per line are 720 pixels as described above, and Y
The number of samples of each component of c, Cb, Cr, and Yi is 360 samples, but if data of 24 samples of each component is added to this 360 samples, it becomes 1
The number of samples per line is 384 samples for each component, and after converting this to 8 bits,

[0046]

[Equation 6]

Therefore, the data amount is the same as that in the 18 MHz mode. Therefore, in the embodiment of the present invention, it is assumed that there are originally 768 pixel sample points, and the recording points and segments are divided. At this time, the added 96 samples × 10 bits of data is
It may be the video data after the effective pixel, or user data other than the video data may be inserted at the input of the video data.

In this way, the number of effective pixels for each component in the 13.5 MHz mode is 384, which is divisible by the 24 pixel period or the 32 pixel period described in FIG. 7, and therefore in FIG. 7 described above. Each component can be evenly divided into 4 channels x 3 or 4 segments in the same manner as the 18 MHz mode described.

Y belonging to one line divided in this way
A sample of one of the c, Cb, Cr, and Yi components is 525 / per segment of one recording channel.
In case of 60 method,

[0050]

[Equation 7]

In the case of the 525/60 system,

[0052]

[Equation 8]

It becomes From the above, Yc, Cb, Cr,
The video sample of each component of Yi is divided into four recording channels and four segments, and each sample has an address (ch, seg, splSeg) described in FIG.
Is given. That is, if the channel number is ch, ch is an integer from 0 to NCh-1, and if the segment number is seg, seg is an integer from 0 to NSeg-1,
If the sample number of each component of each segment of each recording channel is splSeg, splSeg is 0 to NS.
It is an integer up to plSeg-1.

However, NSplSeg is one recording channel for each of the Yc, Cb, Cr, and Yi components belonging to one line.
The number of samples distributed to one segment. As mentioned above, when the 525/60 system is used in the 18 MHz mode,

[0055]

[Equation 9]

In the 625/50 system in the 18 MHz mode,

[0057]

[Equation 10]

When the 525/60 system is used in the 13.5 MHz mode,

[0059]

[Equation 11]

In the 625/50 system in the 13.5 MHz mode,

[0061]

[Equation 12]

It is Here, each Yc, Cb, Cr, Y
A component number comp is defined to distinguish the i component, and is 0 for Cb, 1 for Cr, 2 for Yc, and 3 for Yi.

Next, in the 13.5 MHz mode, 10
Each bit sample is divided into an upper 8-bit upper sample and a lower 2-bit lower sample, and ch, seg, sp
3 lower 2 bits of Yc, Cb, and Cr component samples having the same value of 1Seg and 1 lower 2 bits of Yi component samples represented by the following expressions are collected to form one 8-bit data. .

That is, for the 8-bit word in which the data of the lower 2 bits are collected, the number lowP representing the position of 2 bits in 8 bits is set to 0 for (bit0, bit1),
1 for (bit2, bit3), (bit4, bit3)
5 is defined as 2 and (bit6, bit7) is defined as 3,

[0065]

[Equation 13]

When the lower samples are arranged to form an 8-bit word and the address in one segment of the converted 8-bit word is represented by splSeg8,
When mp = 0, 1, 2 (that is, Yc, Cb, Cr components),

[0067]

[Equation 14]

When comp = 3 (that is, the Yi component),

[0069]

[Equation 15]

By doing so, the position of the lower sample forming each 8-bit word on the television screen is determined. However, x mod y represents the remainder obtained by dividing x by y (the same applies hereinafter).

From (Equation 14), the lower 2-bit data of the Yc, Cb, and Cr components having the same splSeg always enter the same one 8-bit word. As described above, since the samples of Yc, Cb, and Cr components belonging to the same pixel have the same splSeg in the same segment of the same recording channel, the Yc belonging to the same pixel on the television screen according to the embodiment of the present invention. , Cb, Cr component lower 2-bit data are converted into the same 8-bit word.

On the other hand, the sample of the Yi component having the same splSeg belongs to the pixel relatively close to the pixel of the sample of the Yc, Cb, Cr component on the television screen,
By the constant compOfstLow of (Equation 15),
By shifting the order of the Yc, Cb, and Cr components represented by (Equation 14), the same spl as the Yc, Cb, and Cr components can be obtained.
Not the lower 2 bits of the Yi component having Seg, but the lower 2 bits of the Yi component of pixels horizontally separated on the screen are 1
Into an 8-bit word. For example, 525
In the / 60 method,

[0073]

[Equation 16]

In the 625/50 system,

[0075]

[Equation 17]

Then, the lower samples of the Yc, Cb, and Cr components and the lower samples of the Yi components of pixels that are horizontally separated from each other by about one-half line on the screen form one 8-bit word. You can

That is, the 8-bit word obtained by converting the lower 2 bits of each sample of the second digital video signal is Yc, Cb, Cr at the same position on the television screen.
It consists of the lower 2 bits of the component sample and the lower 2 bits of the Yi component sample at horizontally spaced positions on the television screen, and thus if one of these 8-bit words is in error, the television screen Above, Yc, Cb,
Only a total of two pixels, one pixel to which the Cr component belongs and another pixel to which the Yi component belongs, result in an error, and these two error pixels are separated in the horizontal direction.

An 8-bit word obtained by converting the lower 2 bits by the above method is combined with the upper sample of the upper 8 bits as follows.

That is, the 8-bit word obtained by converting the lower 2 bits as described above is 32 per channel of 1 line × 1 segment in the case of the 525/60 system.
Byte, 24 bytes in the case of the 625/50 system. If this is divided into 4 bytes and divided into 8 bytes or 6 bytes respectively and combined with 32 bytes or 24 bytes of 1 channel of 1 line of 1 line × 1 segment of 1 component, 40 bytes in the case of 525/60 system, 625/50
In the case of the system, it becomes 30 bytes, which corresponds to the number of data in the above 18 MHz mode. When the component number after combining is convComp and the sample number in the segment after combining is convSplSeg, the upper 8 bits of data are:

[0080]

[Equation 18]

Then,

[0082]

[Formula 19]

[0083]

[Equation 20]

Then, regarding the 8-bit word in which the lower 2 bits of data are collected,

[0085]

[Equation 21]

Then,

[0087]

[Equation 22]

[0088]

[Equation 23]

It is assumed that However, floor (x) represents an integer not exceeding x. Also, NSplOCSeg is 52
In case of 5/60 method,

[0090]

[Equation 24]

In the case of the 625/50 system,

[0092]

[Equation 25]

Is a constant. (Equation 19), (Equation 2)
0), (Equation 22), and (Equation 23), the upper sample of each segment and the quarter sample of the lower sample of each segment of each channel are combined into one signal for each component of each channel. It will be.

On the other hand, in the 18 MHz mode, since each sample is originally quantized with 8 bits, the above conversion is not necessary, but in order to make the notation the same,

[0095]

[Equation 26]

[0096]

[Equation 27]

It is assumed that By the above processing, even in the 18 MHz mode for recording the first digital video signal,
13.5 MHz for recording the second digital video signal
When in mode, all 8-bit words are (convC
Omp, ch, seg, convSplSeg) have a unified set of values. At this time, each component Yc, Cb, Cr, Yi belonging to the same recording channel and segment with the same line data
The number of bytes for each becomes NSplOCSeg mentioned above, and 1
The same value is obtained in both 8 MHz mode and 13.5 MHz mode. Therefore, the second digital video signal can be recorded by applying the system of the present invention to the device for recording the first digital video signal.

Further, according to the method described above, the same shuffling method can be applied to the 18 MHz mode and the 13.5 MHz mode as described below.

Here, the shuffling is a process of changing the order of data so as to record the data belonging to the adjacent pixels on the tape as far as possible from each other and record the reproduced image quality when an error occurs. Improve. In the embodiment of the present invention, (convComp, ch,
N having the same (convComp, ch, seg) among the addresses represented by seg, convSplSeg)
Conv for SplOCSeg 8-bit words
Shuffling can be performed by changing the order of SplSeg.

At this time, the amount of data arranged in one segment of one recording channel as described above is the same in the 18 MHz mode and the 13.5 MHz mode in 8-bit units, so the order can be changed within this range. If 1
The shuffling can be performed in the same manner in the 8 MHz mode and the 13.5 MHz mode. Therefore, for example, a tape recorded in 18 MHz mode
Even if you play it back in 3.5MHz mode, 13.5MHz
Even if the tape recorded in the mode is played in the 18MHz mode, the shuffling method is the same, so 13.5MH
Since the portion corresponding to 768 pixels of the effective pixel portion in the z mode is correctly reproduced, the vertical blanking period is set to 1
Effective pixel portion 7 in line 13.5 MHz mode
The correct mode can be determined by recording the identification signals of the 18 MHz mode and the 13.5 MHz mode using 68 pixels and detecting the identification signals during reproduction.

Next, an embodiment of a digital video signal processing apparatus for realizing the above processing method in the present invention will be described.

Also in this embodiment, the first component digital video signal is extended 4: 2: 2.
The second component digital video signal is a 4: 2: 2 system. The number of effective samples per line is also the same as that of the above-described embodiment. The pixel structure is as shown in FIG. 8, and the luminance signal component Y is divided into Yc and Yi as described above.

By performing the encoding of the present invention on the second component digital video signal, it is converted into the same 8-bit digital signal as the first component digital video signal. This makes the first
The second component digital video signal can be recorded by applying the processing device of the present invention to the digital VTR that records and reproduces the component digital video signal.

FIG. 1 is a block diagram showing the arrangement of a digital video signal processing apparatus according to the first embodiment of the present invention.

In FIG. 1, reference numerals 1, 2, 3, and 4 denote color difference signal components Cb and Cr and luminance signal components Yc and Yi, respectively.
Input terminals for inputting 0-bit samples, 5 are Cb, C
Upper memory for storing upper 8 bits 11, 12, 13, 14 of sample data 7, 8, 9, 10 obtained by sampling r, Yc, Yi components with 10 bits, 6 is Cb, Cr, Yc, Yi component Memory for storing the lower 2 bits 15, 16, 17, 18 of the sample data 7, 8, 9, 10 respectively sampled with 10 bits, 19 is the channel number of the write address of the data to the memories 5, 6. 20 and 21 are channel sequence generation circuits (abbreviated as ch generation in the figure), 22 is a segment sequence generation circuit that generates segment numbers 23 and 24 of write addresses of data to the memories 5 and 6 (seg generation in the figure) Is abbreviated), and 25 is a sample number 26 in one channel and one segment of the write addresses of data to the memories 5 and 6. A generated sample sequence generation circuit (abbreviated as splSeg generation in the figure), 27 is a shift circuit that obtains a sample number 30 by shifting the sample number 26 by a constant value, and 28 is a read address of data from the conversion memories 5 and 6. Of these, the component series generation circuit that generates the component number 29 (convCom in the figure
p is abbreviated as p), 31 is a segment sequence generation circuit (abbreviated as seg in the figure) that generates a segment number 32 among read addresses of data from the conversion memories 5 and 6, and 33 is from the conversion memories 5 and 6. A sample sequence generation circuit (abbreviated as convSplSeg generation in the figure) that generates a sample number 34 of the read address of the data of 35, an offset circuit 35 that subtracts the number of pixels per segment from the read sample number 34 and outputs the lower 4 bits, 38 is a comparison circuit for comparing the read sample number 34 with the number of pixels per segment to obtain an upper and lower selection signal 39 of the output; 40 is read data 44 of the channel 0 from the upper memory 5 and the lower data 6 from the lower memory 6; A multiplexer for switching the read data 45 of channel 0, 41 is A multiplexer for switching the channel 1 read data 46 from the rank memory 5 and the channel 1 read data 47 from the lower memory 6, 42 is the channel 2 read data 48 from the upper memory 5 and the lower memory 6 A multiplexer for switching the read data 49 of the channel 2 from the upper memory 5, 43 a multiplexer for switching the read data 50 of the channel 3 from the upper memory 5 and the read data 51 of the channel 3 from the lower memory 6, 52, 53 , 54 and 55 are output terminals for outputting data converted into 8-bit data of channels 0, 1, 2, and 3, respectively, and 60 is an upper memory 5 and a lower memory for each line in synchronization with an input video signal. 6, which switches the write / read memory chips. A memory switching circuit for outputting a down switch signal 61 (in the drawing switching circuit for short).

The channel series generation circuit 19, the segment series generation circuit 22, the sample series generation circuit 25, and the shift circuit 27 constitute a write address generation circuit, and the component series generation circuit 28 and the segment series generation circuit 3 are provided.
1, a sample sequence generation circuit 33, an offset circuit 35,
The comparison circuit 38 constitutes a read address generation circuit. Further, the video synchronization control circuit (not shown) synchronizes with the input video signal, and the whole operates based on clocks of 6.75 MHz and 9 MHz synchronized with the input signal as described later.

The operation of the embodiment of the present invention will be described below. 10-bit sample 7 of each component Cb, Cr, Yc, Yi of the second component digital video signal,
8, 9, and 10 are input at a clock rate of 6.75 MHz, respectively. These 10 bit samples 7,
The upper 8 bits 11, 1 for each of 8, 9 and 10
2, 13 and 14 in the upper memory 5, lower 2 bits 1
Write 5, 16, 17, 18 in the lower memory 6.

At this time, the channel sequence generation circuit 19, the segment sequence generation circuit 22, and the sample sequence generation circuit 25 which form the write address generation circuit are synchronized with the input video signal by the control circuit (not shown), and the input signal 7,
The values of ch, seg, and splSeg as shown in FIG. 7 are generated in synchronization with the clock rate of 6.75 MHz of 8, 9, and 10, and Yc, Cb, and Cr are assigned to the channel number 20.
The value of ch for the component is set to Yi for channel number 21.
The value of ch for the component is Y for the segment number 23.
The seg value for the c, Cb, and Cr components, the seg value for the Yi component for the segment number 24, and the splSeg value for the sample number 26 are output. That is,
Channel number 20 and segment number 23 are pi in FIG.
The value x is an even number, and the channel number 21 and the segment number 24 are values when pix in FIG. 7 is an odd number.

In the high-order memory 5, the high-order 8-bit data 11 of the Cb component is written at the address indicated by the channel number 20, the segment number 23 and the sample number 26 with the component number 0. In addition, the upper 8-bit data 12 of the Cr component has a component number of 1.
At the address indicated by the channel number 20, the segment number 23, and the sample number 26, the upper 8-bit data 13 of the Yc component has the component number 2 and the channel number 20, the segment number 23, and the sample number 2
Is written to the address indicated by 6. On the other hand, Y
The high-order 8-bit data 14 of the i component is written at the address indicated by the channel number 21, the segment number 24, and the sample number 26 with the component number 3.

In the lower-order memory 6, the lower 2-bit data 15 of the Cb component is at the address indicated by the channel number 20, the segment number 23, and the sample number 26 of the component number 0, and the lower 2-bit data 16 of the Cr component is Component number is 1 and channel number is 2
At the address indicated by 0, segment number 23, and sample number 26, the data 1 of the lower 2 bits of the Yc component
7 has a component number of 2 and is written at an address indicated by a channel number 20, a segment number 23 and a sample number 26. On the other hand, the lower 2-bit data 18 of the Yi component is written at the address indicated by the channel number 21, the segment number 24 and the sample number 30 with the component number 3. Here, the sample number 30 is the sample number 26 by the shift circuit 27.
As a constant value compOfstL as shown in (Equation 15)
It is a value shifted by ow.

From the above, the lower samples of the Yc, Cb, and Cr components are at the same sample number addresses as the upper samples as shown in (Equation 14), and the lower samples of the Yi component are as shown in (Equation 15). It is written to the address of the sample number which is horizontally shifted by a fixed value.

FIG. 5 shows an example of the values of these addresses.
This figure corresponds to (a) of FIG. 7, and is an example in the case of compOfstLow = 16 in the 525/60 system.

In this way, after writing one line of data in the upper memory 5 and the lower memory 6, the memory chips inside the upper memory 5 and the lower memory 6 are switched by the line switching signal 61, The written data is read in 8-bit units in the next 1-line period, and at the same time, the next 1-line data is written in another set of memory chips as described above.

At this time, the component series generation circuit 28, the segment series generation circuit 31, and the sample series generation circuit 33 which constitute the read address generation circuit are synchronized with the input video signal by the video synchronization control circuit (not shown), and the first digital video 18MHz recording signal
The component number 29, the segment number 32, and the sample number 34 are output at the clock rate of 9 MHz, which is the same as the clock rate of the input video signal in the mode.

From the upper memory 5, the segment number 3
In segment order according to 2, then sample number 3
4 in order of the samples in the segment, and 4 in order of each component according to the component number 29.
Channel data is read at the same time, channel 0 data is used as upper data 44, channel 1 data is used as upper data 46, and channel 2 data is used as upper data 4
8, the data of channel 3 is output to the upper data 50. As a result, as shown in (Equation 19) and (Equation 20), the upper 8-bit data is sequentially read.

In this way, the sample number 34 is 0 to N
All top 8 of that segment up to SplSeg-1
After reading the bit word, the lower 2-bit data is read from the lower memory 6 as described below.

From the lower memory 6, the segment number 3
In segment order according to 2, then sample number 3
7, the samples in the segment are sequentially read in parallel to the data of 4 channels, the data of channel 0 is the lower data 45, the data of channel 1 is the lower data 47, and the data of the channel 2 is the lower data 49.
Then, the data of channel 3 is output to the lower data 51. At this time, the data of all the components of Yc, Cb, Cr, and Yi are read out simultaneously, as shown in (Equation 13).
8-bit data 45, 4 by arranging bit-by-bit data
6,47,48 are obtained. Sample number 37 is
The offset circuit 35 changes the sample number 34 to NS.
The value 36 obtained by subtracting plSeg is obtained, and is obtained by adding the component number 29 to the lower order thereof as shown in FIG. This implements the inverse functions of (Equation 22) and (Equation 23) (see FIG. 6).

In this way, the sample number 34 is NSp
When all the lower 2 bit data of the segment from 1Seg to NSplOCSeg-1 are read, the next segment is moved to and the upper 8 bit word is read from the upper memory 5 as described above.

As described above, the sample number 34 is 0 to NS.
Up to plSeg-1, output 44 from upper memory 5
An 8-bit word consisting of upper samples is read out at 46, 48, and 50, and the sample number 34 is NSplSeg ~.
Up to NSplOCSeg-1, an 8-bit word consisting of lower samples is read to the outputs 45, 47, 49, 51 from the lower memory 6, so the sample number 34 is compared with NSplSeg by the comparison circuit 38, and the sample number 34 is NSplSeg. When it is smaller, multiplexers 40, 41, 42, through upper and lower selection signals 39,
43 is the output signal 44, 46, 48, 5 of the upper memory 5
When the sample number 34 is larger than NSplSeg, the multiplexers 40, 41, 42 and 43 are switched to the output signals 45, 47, 49 and 51 of the lower memory 6 through the upper and lower selection signals 39. As a result, one continuous 8-bit word signal is obtained for each channel.

From the above, (Equation 19), (Equation 20),
The processing described in (Equation 22) and (Equation 23) is realized.
Here, the component number 29, the segment number 32, the sample number 34, and the sample number 3 described above.
7. An example of the value of the switching signal 39 is shown in FIG. In the figure, the switching signal 39 is low for the upper memory side,
High indicates that the lower memory side is selected.

Next, a more detailed structure of the upper memory 5 is shown in FIG. In the figure, 62, 63, 64 and 65 are upper component memories for storing Cb, Cr, Yc and Yi components respectively, and 66 is one for each channel from the outputs of the upper component memories 62, 63, 64 and 65. Select output and upper read data 44, 46,
This is a multiplexer for obtaining 48 and 50.

The upper component memory 62 has a memory for two lines for storing the upper 8-bit word 11 of the Cb component, and the writing and reading of these two lines are alternately performed one line at a time according to the line switching signal 61. The upper component memory 63 is the upper 8 of the Cr component.
It has a memory for two lines for storing the bit word 12, and writing and reading of these two lines are performed alternately line by line according to the line switching signal 29. The upper component memory 64 has a memory for two lines for storing the upper 8-bit word 13 of the Yc component, and writes and reads these two lines alternately one line at a time according to the line switching signal 29. The upper component memory 65 stores the upper 8-bit word 1 of the Yi component.
It has a memory for 2 lines which stores 4 and writes and reads these 2 lines alternately one line at a time according to the line switching signal 29.

These four upper component memories 6
The channel numbers 20 and the segment numbers 23 of the write addresses of 62, 63, 64 corresponding to the Cb, Cr, Yc components of 2, 63, 64, 65 are common, and the samples of these components are the same as those of the respective memories. As described above, the pixel number pix is written at the same address corresponding to the even-numbered pixels. On the other hand, the channel number 21 and the segment number 24 of the write address of 65 corresponding to the Yi component are different from the above three as shown in FIG. 5, and as described above, the Yi is assigned to the address corresponding to the pixel having the odd pixel number pix.
The component sample 14 is written. The other addresses are common to the four upper component memories.

The multiplexer 66 selects one of the read data 100, 104, 108 and 112 of the channel 0 and outputs the higher read data 44 of the channel 0 and the read data 101, 105, 109 and 11 of the channel 1.
Select one from 3 and read upper data 4 of channel 1
6 is the read data 102, 106,
One of 110 and 114 is selected and the upper read data 48 of the channel 2 is set to the read data 10 of the channel 3
One of 3, 107, 111 and 115 is selected and the upper read data 50 of channel 3 is output. At this time, the output data from one memory corresponding to one component indicated by the read component number 29 is selected from the four upper component memories 62, 63, 64, 65. In this way, the output 44, 46 of each channel from the upper memory 5 is arranged in the order of the component number 29.
48,50 are obtained.

On the other hand, the detailed structure of the lower memory 6 is shown in FIG.
Shown in. In the figure, reference numerals 67, 68, 69 and 70 denote lower component memories for storing Cb, Cr, Yc and Yi components, respectively, which have a capacity of two lines like the upper component memory and have a line switching signal 2
In accordance with 9, writing and reading of these two lines are alternately performed one line at a time.

Read data 116, 1 of channel 0
20 bits, 124, 128 are arranged in order from the LSB in units of 2 bits to form 8-bit upper read data 45, and channel 1 read data 117, 121, 125, 129 are arranged in units of 2 bits in order from the LSB to form 8-bit upper read data 47. , Read data of channel 2 11
8, 122, 126, and 130 are arranged in order from the LSB in units of 2 bits, and 8-bit high-order read data 49 is read out from channel 3 read data 119, 123, 127, and 1.
2 are arranged in order from LSB to obtain upper read data 51 of 8 bits. As a result, the processing shown in (Equation 13) is realized.

Four lower component memories 67, 6
The channel numbers 20, segment numbers 23, and sample numbers 26 of the write addresses 67, 68, 69 corresponding to the Cb, Cr, Yc components of 8, 69, 70 are common as shown in FIG. Samples are written to the same address in each memory. As a result, the processing shown in (Equation 14) is realized.

On the other hand, the channel number 21, segment number 24, and sample number 30 of the write address of 70 corresponding to the Yi component are different from the above three as shown in FIG. 5, and the processing shown in (Equation 15) is realized. To be done.

The other addresses are common to the four upper component memories. Further, a detailed configuration of the upper component memory 62 is shown in FIG. In the figure, the upper component memory 62 includes eight RAs.
It is composed of M77, 78, 79, 80, 81, 82, 83, 84, and 4 of RAM77, 78, 79, 80.
One set of 1-line memory, RAM 81, 82, 8
Another set of 1-line memories is constituted by 4 of 3, 84. As described above, these two sets of 1-line memories alternately perform writing / reading for each line according to the switching signal 61. RAMs 77 and 81 are memories for storing channel 0 data, RAMs 78 and 82 for storing channel 1 data, RAMs 79 and 83 for storing channel 2 data, and RAMs 80 and 84 for storing channel 3 data.

The write segment number 23, write sample number 26, read segment number 32, and read sample number 34 are selected by the address multiplexer 72 controlled by the switching signal 61, and the RAM 7
It is alternately supplied to 7, 78, 79 and 80 line by line. On the other hand, in the RAMs 81, 82, 83 and 84, the write segment number 23 and the write sample number 26, which are also selected by the address multiplexer 75 controlled by the switching signal 200 which is the switching signal 61 inverted.
One of the read segment number 32 and the read sample number 34 is alternately supplied for each line.

When the write data control circuit 73 indicates that the memory switching signal 61 is writing to the RAMs 77, 78, 79, 80, the upper 8-bit word 11 of the Cb sample is assigned to the assigned channel indicated by the write channel number 20. Is supplied to the RAM corresponding to. At this time, the write enable control circuit 71 puts the RAM corresponding to the channel number 20 into the write mode.

When the write data control circuit 74 indicates that the memory switching signal 200 is writing to the RAMs 81, 82, 83, 84, the upper 8-bit word 11 of the Cb sample is assigned to the assigned channel indicated by the write channel number 20. Is supplied to the RAM corresponding to. At this time, the write enable control circuit 76 puts the RAM corresponding to the channel number 20 into the write mode.

In reading, when either one of the switching signals 61 and 200 indicates reading, the write enable control circuits 71 and 76 correspond to the corresponding group of RAM 77, 78, 79, 80 or RAM 81 ,.
The four RAMs 82, 83 and 84 are read from the same address on all channels simultaneously.

The multiplexer 85 uses the switching signal 200
According to the above, the output data from the set of RAMs on the read side is selected for each line and set as the read data 100, 101, 102, 103 of each channel.

Other upper component memory 6
3, 64 and 65 have the same configuration and operate in the same manner.

The lower component memories 67 and 6
The configurations and operations of 8, 69 and 70 are similar except that the bit width of the data in each RAM is 2 bits instead of 8 bits.

As described above, 13.5 MHz 10
An apparatus for implementing the signal processing method described in the first embodiment of the present invention for encoding a bit second component digital video signal into an 18 MHz 8-bit signal is obtained.

As a result, the 8-bit word obtained by converting the lower 2 bits of each sample of the second digital video signal is Yc, Cb, C at the same position on the television screen.
It consists of the lower 2 bits of the r component sample and the lower 2 bits of the Yi component sample at horizontally separated positions on the television screen. Therefore, if one word of this 8-bit word is in error, the television screen Above, Yc, Cb,
Only one pixel to which the Cr component belongs and another pixel to which the Yi component belongs, a total of two pixels will be in error.

Also, an 8-bit word obtained by converting the lower 2 bits of each sample of the second digital video signal is combined with the upper 8 bits of data of each sample, so that each segment of each recording channel It is possible to construct the same set of data numbers as in the 18 MHz mode for recording the first digital video signal for the component.
Therefore, the second digital video signal can be recorded by applying the system of the present invention to the device for recording the first digital video signal.

In the 18 MHz mode, the clock rate 9 is output from each of the similar input terminals 1, 2, 3 and 4.
Enter the sample in MHz. At this time, the input signal 7,
The upper 8 bits of each of 8, 9, and 10 are used as an 8-bit sample that is the first digital video signal, and the lower 2 bits of each of the input signals 7, 8, 9, and 10 are set to 0, and only the upper memory 5 is used. Each address may be generated so as to be distributed to each channel and segment by using the embodiment of the present invention and the 18 MHz mode and 13.5 MHz.
Both signal processing in MHz mode is possible. At this time, the same shuffling can be applied as described in the embodiment of the signal processing method of the present invention, and the mode determination can be performed using the effective pixel portion 768 pixels of one line in the vertical blanking period. .

[0141]

As described above, according to the present invention, it is possible to construct an m-bit word that always includes three lower samples of a luminance signal component and two chrominance signal components sampled at the same position on a television screen. Even if an error occurs in one m-bit word converted from the lower (n−m) bits in the process of recording / reproducing or transmitting, the number of error pixels on the corresponding screen can be minimized. . As a result, the image quality deterioration due to an error can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a digital video signal processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a high-order memory in the embodiment.

FIG. 3 is a block diagram showing a configuration of a lower memory in the embodiment.

FIG. 4 is a block diagram showing a configuration of a component memory in the embodiment.

FIG. 5 is a timing diagram showing write addresses in the embodiment.

FIG. 6 is a timing diagram showing a read address in the embodiment.

FIG. 7 is a schematic diagram showing distribution of channels and segments in the same embodiment.

FIG. 8 is a schematic diagram showing a sampling structure of a digital video signal.

[Explanation of symbols]

 5 Upper memory 6 Lower memory 11, 12, 13, 14 Upper sample 15, 16, 17, 18 Lower sample 40, 41, 42, 43 Multiplexer

Claims (2)

[Claims] 1. Considering two positive integers n and m, n> m
Is divisible by (n−m), f = m / (n−m), and the first component digital video signal quantized by m bits and the second component digital video quantized by n bits Regarding the signal, the second
For each of the luminance signal component and the two chrominance signal components of the component digital video signal, sample data consisting of n bits each is composed of data consisting of m bits from the most significant bit and (nm) bits from the least significant bit. When divided into data and called the upper sample and the lower sample, respectively, the lower sample of the f sample including the three lower samples of the luminance signal component and the two samples of the two color difference signal components sampled at the same position on the television screen. A method of processing a digital video signal, characterized in that a sample is made up of words of m bits. 2. Considering two positive integers n and m, n> m
Is divisible by (n−m), f = m / (n−m), and the first component digital video signal quantized by m bits and the second component digital video quantized by n bits Regarding the signal, the second
For each of the luminance signal component and the two chrominance signal components of the component digital video signal, the sample data consisting of n bits each is composed of a sample consisting of m bits from the most significant bit and (n−m) bits consisting of the least significant bit. Divide into samples,
When called a lower sample, an upper memory for storing the upper sample for one horizontal scanning period, a lower memory for storing the lower sample for one horizontal scanning period, the upper sample and the lower sample, respectively. A write address generating circuit for generating an upper write address and a lower write address for writing in the upper memory and the lower memory; and for reading a word of m bits from the upper memory and the lower memory, respectively. One of a read address generation circuit for generating an upper read address and a lower read address, a word composed of m bits output from the upper memory and a word composed of m bits output from the lower memory. And a multiplexer to select
The three lower samples of the luminance signal component and the two color difference signal components sampled at the same position on the television screen are included in the same m-bit word output from the lower memory. For processing digital video signals.