JPH06314255A - Computer system - Google Patents

Abstract

PURPOSE:To bring out the performance of an extended board while keeping compatibility by adding an access speed judging means for the extended board connected to an extended bus slot and a means.to hold the information of a judged result. CONSTITUTION:The extended bus slot to connect a CPU 101 and the extended boards 106,107, and a bus interface circuit to connect the CPU 101 and the signal of the extended bus slot are provided, and bus clocks 111 to 113 are supplied from a bus interface logic circuit 104 to each extended board 106, 107 of the extended bus slot. Namely, the means to judge the access speed of the extended boards 106, 107 connected to the extended bus slot and the means to hold the result of judgement are added. Accordingly, the operation possible frequency of the bus clocks 111 to 113 corresponding to the extended bus slot is determined automatically, and only at the time of accessing the corresponding extended board, the bus clock of the corresponding frequency is supplied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is capable of automatically determining the performance according to the data access performance of the expansion board to be mounted, and dynamically switching the access speed so as to maximize the performance. Regarding computer systems that can.

[0002]

2. Description of the Related Art In recent years, due to advances in semiconductor technology, CP
The data processing capability of U, memory LSI, peripheral control IC, etc. has been dramatically improved. On the other hand, in the so-called industry standard computer system, the data transfer speed of the expansion bus slot, which is assumed to be mounted with an arbitrary board, has recently been increased due to the problem of compatibility with past assets. It is lower than the processing capacity of semiconductors.

Generally, the data transfer rate of an expansion bus of a computer system, which is an industry standard, is defined by a bus clock output to the bus, and the bus clock is fixed at a certain frequency. The expansion board mounted is designed according to the specified bus clock. Therefore, for example, in the conventional computer system as shown in FIG. 1, the CPU clock 10
8 and the bus clock 401, as shown in FIG. 2, when the CPU clock 108 has a higher frequency than the specified bus clock, it is corrected and expanded by a frequency divider circuit so as to meet the specified value. Output to the bus. In addition,
In this example, the CPU clock has a frequency twice the specified value of the bus clock.

[0004]

Here, for example, in FIG.
When the expansion board 1 indicated by 106 of FIG. 1 can operate at a frequency higher than the bus clock, the bus clock 401 is adjusted according to the performance of this expansion board in order to increase the processing capacity.
It is conceivable to set a high frequency. However, there is a problem that only the expansion board 2 indicated by 107 in FIG. 1 or any other expansion board is guaranteed to operate with the specified bus clock.

In order to solve this problem, for example, FIG.
As shown in, multiple bus clocks with different frequencies (3
01, 302, 303, 304) may be prepared and a certain kind of switch may be used to handle the problem. By providing this switch for each expansion bus slot, it becomes possible to supply bus clocks having different frequencies for each expansion board. However, this method has a problem that all accessible devices in the expansion board 1, for example, must support the supplied high-frequency bus clock. For example, the expansion board 1 is equipped with a certain readable / writable memory (RAM) and a read-only memory (ROM), and high-speed access is possible for RAM access, but for ROM When only the specified access speed is supported, as a result, this expansion board 1
It can only operate at the specified bus clock speed. Further, in this method, it is necessary to check the setting of the bus clock changeover switches (305, 306) every time the expansion board is inserted or removed, which is complicated and causes a problem of erroneous operation.

In a computer system equipped with a plurality of memory modules having different access speeds, as a prior art characterized by dynamically changing the memory access speed, for example, "Computer System (Japanese Patent Laid-Open No. 2-287845)" There is. According to the prior art, a computer system receives a certain status signal from a memory module, determines the access speed based on the contents of the status, and controls the memory access speed of the CPU. Although the prior art is similar to the present invention in that the access speed is dynamically changed individually according to the performance of the memory module, when the prior art is applied to the industry standard expansion bus, the compatibility is not improved. Comes up with a problem. That is, the prior art requires some kind of status signal from the expansion board, and in this respect, there is a problem that compatibility as an industry standard bus is lost.

As described above, when the expansion board designed and manufactured by the recent semiconductor technology is used in the industry standard computer system, regardless of the high data processing capability of the expansion board, the industry standard computer system is used. Since the data transfer speed of the expansion bus is low, there is a problem that the performance of the expansion board cannot be fully exhibited.

The present invention has been made to solve the above-mentioned conventional problems, and has a function of detecting the operable bus clock of the expansion board to be mounted and switching the bus clock frequency while ensuring compatibility. The purpose is to provide a computer system.

[0009]

According to the present invention, a CPU and an expansion bus slot for connecting an arbitrary expansion board are provided.
In a computer system including a bus interface circuit for connecting a signal of the CPU and the expansion bus slot, an access speed judging means of an expansion board connected to the expansion bus slot, and information of a result of the judgment are held. Means is provided in the bus interface circuit to improve the data transfer speed between the expansion board and the computer system, thereby achieving the above object.

[0010]

According to the present invention, the industry standard computer system is provided with the access speed judging means for the expansion board connected to the expansion bus slot and the means for holding the information of the result of the judgment. Corresponding to, the frequency of the operable bus clock is automatically determined, the information of the determined bus clock is retained, and the bus clock of the frequency suitable for the expansion board is maintained only while the expansion board is accessed. Supplied. This enables the bus clock speed to be automatically and dynamically switched according to the performance of the expansion board to be mounted, and the expansion board to be mounted while maintaining compatibility as an industry standard computer system. It is possible to maximize the performance of.

Further, it is easy to make a series of these processes, that is, the determination of the access speed of the expansion board and the retention of the determination result, automatically after the power of the computer system is turned on. It is possible to realize it without being conscious of it and without causing complexity and malfunction.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 4 is a block diagram showing an embodiment of the present invention. FIG. 1 is a block diagram showing a conventional technique.
The difference is that the bus clocks 111, 112, and 113 are individually supplied from the bus interface logic to each expansion external bus slot.

The internal bus 109 has a CPU 101 and an RO.
The M102, the memory 103, the bus interface logic 104, and the other logic 105 are connected. The CPU clock 108 is supplied to the CPU 101 and the internal bus 109, and is supplied to the bus interface logic 104 and other necessary blocks via the internal bus. Bus interface logic is expansion bus 1
10 and controls interface between the internal bus and the expansion bus. The general operation of the bus interface logic is to convert various signals that operate in synchronization with the CPU clock so as to match the external bus interface protocol, as shown in the timing chart of FIG. The external bus interface protocol mentioned here is an external expansion bus specification defined by an industry standard computer system.

The timing chart of FIG. 2 shows the operation of a general bus interface logic.
Here, the case where the CPU clock has a frequency twice as high as the bus clock of the external bus is shown. Where ADS #,
CADDDR, M / IO #, and W / R # are address strobe, address, memory / IO area, and read / write signals from the CPU, respectively. DRY # is C
The bus cycle of the CPU ends when this signal becomes active by the signal input to the PU. Also AL
E, MEMW #, and BADDR are signals from the CPU that are converted by the bus interface logic and synchronized with the bus clock, and are address latch enable, memory write, and bus address signals, respectively. Further, READY # is a bus access end signal from the mounted expansion board, and this signal becomes an RDY # signal synchronized with the CPU clock by the bus interface logic and is sent to the CPU.

FIG. 5 shows a status register added to the bus interface logic. This status register exists for each expansion bus slot. Here, a memory accessible bit (Am) 501,
Although a case is shown in which the register accessible bit (Ar) 502 and the bus clock switching bit (C) 503 are shown, this configuration is not fixed. For example, a plurality of memory accessible bits are prepared. It is also possible to support fine addresses or to prepare a plurality of clock switching bits to increase the variation of switchable bus clock frequencies.

Memory accessible bit (Am)
Is set to "1 (H)" by the test program described later when the memory on the expansion board mounted is accessible from the system. Similarly, the register accessible bit (Ar) is set to "1 (H)" when the registers on the mounted expansion board are accessible from the system.

The clock switching bit (C) is a bit for designating switching of different bus clocks,
This bit is also set by the test program described later. In the embodiments of the present invention described below, the value of the clock switching bit (C) is "0".
(L) ”, a bus clock having a frequency defined as an industry standard bus clock (hereinafter referred to as a standard clock)
Is output, and when set to "1 (H)", a bus clock having a frequency twice that of the standard bus clock is output, and this clock having a frequency twice the CPU clock is configured. Has been done.

FIG. 6 shows a flow chart of a test program for setting each bit of the status register.

FIG. 7 shows an example of a circuit added to the bus interface logic together with the status register for implementing the present invention.

FIG. 8 is a timing chart showing the operation of the above circuit example.

Hereinafter, referring to FIG. 5, FIG. 6, FIG. 7 and FIG.
The operation of this embodiment will be described.

The status bits 501, 502 and 503 shown in FIGS. 5 and 7 are set as follows by the test program shown in FIG. First, all status registers are reset to "0 (L)" (601). Next, the status register corresponding to the expansion bus slot 1 is set. A flow chart indicated by 610 is a flow chart of a program for setting the status register for each expansion bus slot. First, "1 (H)" is set in the memory access bit (Am). Next, in step 612, the clock switching bit (C) is set to "1".
(H) ”is set. With these settings, the bus clock supplied to the expansion bus slot 1 is output at twice the frequency of the standard clock. In this state, the bus clock is mounted in the expansion bus slot. The memory on the expansion board is tested.There are various possible memory tests to be performed here, but it is possible to test all memory areas used by actual applications or programs such as OS (operating system). If this is the case, the result of this memory test is
If an error is detected, set the Am bit to "0 (L)"
(614) and the process proceeds to the next step (615). If this memory test is OK, the Am bit remains "1 (H)" and the process proceeds to step 615. The steps from step 615 to step 617 are the test for the register, which is similar to the test for the memory. If no expansion board is installed in this expansion bus slot, the Am and Ar bits will be cleared to "0 (L)" because of an error due to the test program. . The above processing is performed on the status registers corresponding to all other expansion bus slots (603 and 604).

Next, the actual operation after the status register is set by the above processing will be described with reference to FIGS. 7 and 8. As an example of setting the status register, the Am bit is "1 (H)" and the Ar bit is "0".
(L) "and the case where the C bit is" 1 (H) "In this state, the memory access to the expansion board mounted in the corresponding expansion bus slot is performed at a frequency twice the standard clock. It operates, and the register access operates on the normal standard clock.

In FIG. 7, ADS # and M / IO # are C
A signal transmitted by the PU, ADS # is an active "L" address strobe, M / IO # is a signal indicating a memory access when it is "H", and a register access when it is "L". 709, 710, 7
Reference numeral 14 is an AND gate, and the accompanying circle mark (◯) indicates an inverter. Reference numeral 711 is an OR gate, and the accompanying circle mark (◯) also indicates an inverter. 713 and 715 are flip-flops, D is a data input, C is a rising edge clock input, Q is a positive polarity data output, Q # is a negative polarity data output, and R is an active “H” reset input terminal. is there.

A signal name with a # mark indicates that the signal is active "L".

Now, consider the operation in the case of memory access on the mounted expansion board. When accessing the memory,
The signal ADS # from the CPU is "L", M / IO # is "H", and the output timing from the CPU is as shown in the timing chart of FIG. As for the output of the AND gate 709, the M / IO # is “H”, the ADS # is “L”, and the Am bit 501 of the status register is set to “H” by the above-mentioned test program. Output signal 701 is "H", it is "H" during the pulse width of ADS #. On the other hand, the output of the AND gate 710 shows that M / IO # is "H".
Therefore, it is clear that it is “L”. Depending on the output results of the AND gates 709 and 710, O
The output signal 703 from the R gate 712 becomes "H" at the same timing as ADS #, the flip-flop 713 is set to "1" and the output signal 705 becomes "H" at the rising timing of this signal. Since the C bit 503 of the status register has been set to "H" by the above-mentioned test program, the output signal 706 of the AND gate 714 becomes "H" and becomes the select signal of the selector 707. In the circuit of this embodiment, the selector 707 is used.
Selects the CPU clock 108 as the bus clock 716 when the select signal is "H", and selects the bus clock 716 obtained by dividing the CPU clock by two when the select signal is "L". . A clock obtained by dividing the CPU clock by 2 has the same frequency as the standard bus clock. For this reason,
In this case, the bus clock 716 has the same frequency as the CPU clock, which is twice the frequency of the bus clock of the standard bus. The expansion board mounted in the expansion bus slot operates at twice the frequency of the bus clock of the standard bus, and when this access cycle ends, it returns a READY # signal indicating that the access has ended.
The READY # signal is transmitted to the CPU via the bus interface logic, ends the bus cycle of the CPU, and is input to the OR gate 711. OR
Since the output of the gate 711 is connected to the reset terminal of the flip-flop 713, the flip-flop 71
3 is reset by the main READY # signal, and the output signal 705 becomes "L". As a result, the select signal 706 of the selector 707 becomes “L”, the CPU clock divided by two is selected as the bus clock, and the bus clock having the same frequency as the bus clock of the standard bus is output.

Regarding access to the register on the expansion board mounted in the expansion bus slot, since the Ar bit of the status register is set to "L" by the test program, the flip-flop 7
It is clear that 13 is not set to "1" so that the bus clock to the expansion bus has the same frequency as the CPU clock divided by two, i.e. the standard bus bus clock.

The effect of shortening the access cycle of the expansion bus according to the present embodiment is apparent by comparing the timing charts of FIGS. 2 and 8, and the expansion bus cycle time is halved.

[0030]

As described above, according to the present invention, by dynamically changing the frequency of the bus clock for any bus cycle of any expansion bus slot, compatibility with the industry standard expansion bus specifications is achieved. This has the effect of maximizing the performance of the expansion board while maintaining it.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional computer system.

FIG. 2 is a timing chart showing a relationship between a conventional CPU clock and a bus clock.

FIG. 3 is a block diagram showing an improved example of the prior art.

FIG. 4 is a block diagram showing an example system according to the present invention.

FIG. 5 is a block diagram showing a status register added in this embodiment.

FIG. 6 is a flowchart showing the operation of this embodiment.

FIG. 7 is a circuit diagram showing an example of a circuit added in this embodiment.

FIG. 8 is a timing chart showing the relationship between the CPU clock and the bus clock according to this embodiment.

[Explanation of symbols]

 101 ... CPU 102 ... ROM 103 ... Memory 104 ... Bus interface logic 106, 107 ... Expansion board 108 ... CPU clock 111, 112, 113 ... Bus clock

Claims (1)

[Claims] 1. A computer system comprising a CPU, an expansion bus slot for connecting an arbitrary expansion board, and a bus interface circuit for connecting signals of the CPU and the expansion bus slot. Data transfer between the expansion board and the computer system is achieved by providing the bus interface circuit with access speed judgment means for the expansion board connected to the slot and means for holding information on the result of the judgment. A computer system characterized by increasing the speed.