JPH06267978A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To lower a crystallization temperature and shorten a crystallization time by forming a gate electrode, a gate insulating film and a semiconductor layer on a substrate, an active region sandwiched by a pair of impurity regions is provided on the semiconductor layer and concentration of a catalytic element promoting crystallization in the impurity region is made larger than that of the active region. CONSTITUTION:A gate electrode 2 is formed on a substrate and an anode oxide 3 is formed on the gate electrode 2. Further, a silicon nitride film 4 is formed as a gate insulating film by a plasma CVD method, continuously an amorphous silicon film is piled up by a plasma CVD method for forming a semiconductor layer 5 by patterning. Then, a pair of impurity regions 7a, 7b are formed on the semiconductor layer 5 for being further recrystallized by a crystallization promoting catalytic action of nickel larger than the active region. Continuously, a silicon oxide film 8 is formed as an interlayer insulator for forming the source/drain regions 9a, 9b. Thereby, a process of crystallization can be performed at lower temperature of a crystallizationn process so as to shorten crystallization.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a thin film transistor (T
FT) and its manufacturing method. The thin film transistor manufactured by the present invention is formed on either an insulating substrate such as glass or a semiconductor substrate such as single crystal silicon. In particular, the present invention relates to a thin film transistor manufactured through crystallization and activation by thermal annealing.

[0002]

2. Description of the Related Art Recently, research has been conducted on an insulating gate type semiconductor device having a thin film active layer (also called an active region) on an insulating substrate. In particular, thin-film insulating gate transistors, so-called thin film transistors (TFTs), have been eagerly studied. These are intended to be used for controlling each pixel in a display device such as a liquid crystal having a matrix structure formed on a transparent insulating substrate and for a driving circuit. Amorphous silicon TFTs and crystalline silicon TFTs are distinguished by the crystalline state.

Above all, since high temperature is not required for manufacturing an amorphous silicon TFT, the yield when it is manufactured on a large area substrate is high and it has already been put to practical use. The structure of the amorphous silicon TFT which is generally put into practical use is called an inverted stagger type (or bottom gate type), and the gate electrode is located below the active region.

The manufacturing method is as follows.
First, after forming a gate electrode on a substrate, a gate insulating film and an amorphous silicon film as an active layer are formed. Then, an N-type microcrystalline silicon film is formed on the amorphous silicon as the source and drain regions. However, at this time, since there is almost no difference in etching rate between the N-type silicon film and the underlying amorphous silicon film, it is necessary to devise such as providing an etching stopper.

In order to solve this problem, by implanting fast ions such as the ion doping method,
A method has been proposed in which a doping impurity is directly introduced into an amorphous silicon film to be used as a source and a drain.

[0006]

However, since the region into which such fast ions are implanted has a remarkably poor crystallinity, it has a problem that it has a low conductivity and cannot be used as it is. In order to enhance the crystallinity, a method of annealing with light energy of a laser or the like has been proposed, but there is no prospect of mass production.

At present, a possible method that can be practically adopted is a method of crystallizing amorphous silicon by heat. However, annealing at a temperature of at least 600 ° C. is required, which is not practical due to the problem of the substrate. That is, the non-alkali glass substrate used for the amorphous silicon TFT has a strain temperature of 600 ° C. or lower (593 ° C. in the case of Corning 7059).
In annealing at 1, the shrinkage and warpage of the substrate become a problem.

Further, if annealing at 600 ° C. is required, the characteristics of the amorphous silicon TFT which can be manufactured at a low temperature cannot be utilized, and the active region is crystallized. Will be lost. Therefore, it has been desired to carry out the crystallization process at a lower temperature (preferably at a temperature lower than the strain temperature of glass by 50 ° C. or more). The present invention is intended to provide an answer to such a difficult task. An object of the present invention is to solve the above problems while maintaining mass productivity.

[0009]

As a result of the research conducted by the present inventor,
It has been revealed that the addition of a trace amount of a catalyst material to the substantially amorphous silicon coating can promote crystallization, lower the crystallization temperature, and shorten the crystallization time. Suitable catalyst materials are simple substances of nickel (Ni), iron (Fe), cobalt (Co), platinum (Pt), or compounds thereof such as silicides. Specifically, a film, particles, clusters or the like having these catalytic elements are formed in close contact with each other under or on the amorphous silicon film, or these catalytic elements are formed in the amorphous silicon film by a method such as an ion implantation method. Can then be crystallized by thermal annealing at a suitable temperature, typically below 550 ° C.

As a matter of course, there is a relationship that the higher the annealing temperature, the shorter the crystallization time. In addition, the higher the concentration of nickel, iron, cobalt, and platinum, the lower the crystallization temperature and the shorter the crystallization time. According to the research conducted by the present inventors, it is necessary that the concentration of at least one of these elements is 10 ¹⁷ cm ⁻³ or more, preferably 5 × 10 ¹⁸ cm ⁻³ or more in order to promote crystallization. I understood it.

On the other hand, all of the above catalyst materials are unfavorable materials for silicon, so that it is desirable that the concentration thereof be as low as possible. In the study of the present inventors, it is desired that the total concentration of these catalyst materials does not exceed 10 ²⁰ cm ^-3 . Especially when used as an active layer,
1 × 10 ¹⁸ cm ^-3 to obtain sufficient reliability and characteristics
Hereafter, it is required that the concentration is preferably 1 × 10 ¹⁷ cm ⁻³ or less.

The present inventor has paid attention to the effect of this catalytic element and found that the above problem can be solved by utilizing it. The manufacturing process of the TFT in the present invention is generally as follows. Gate electrode formation Gate insulation film formation Amorphous silicon film formation Introducing doping impurities (by ion implantation or ion doping method) 'Forming a substance having a catalytic element on a silicon film Activation of doping impurities (550 ° C Within 8 hours) Source and drain electrode formation

Alternatively, gate electrode formation, gate insulating film formation, amorphous silicon film formation, doping impurity introduction (by ion implantation or ion doping method) 'catalyst element introduction (ion implantation or ion doping method), doping impurity Activation (less than 550 ℃, within 8 hours) Source and drain electrode formation

In these steps, and 'can also reverse their order. In the present invention, the catalyst element mainly introduced into the source / drain region in the above step 'remarkably promotes crystallization of the region. Therefore, a temperature of 550 ° C. or lower, typically 500 ° C. or lower is sufficient for activation, and an annealing time of 8 hours or less, typically 4 hours or less is sufficient. In particular, when the catalytic element is evenly distributed from the beginning by the ion implantation method or the ion doping method like the latter, crystallization was extremely easy to proceed.
In this case, the mask used for introducing the doping impurities may be used for introducing the catalyst element. Such a mask can be obtained in a self-aligned manner by exposing the gate electrode from the back surface.

An advantage of the present invention is that although a catalytic element harmful to silicon is added to the TFT, its concentration is extremely low in the active region (1 × 10 ¹⁸ cm ^-3 or less).
That is, no matter which process is adopted, since the mask used for doping is present on the active region, the catalytic element is not directly adhered to or implanted into the active region. As a result, the reliability and characteristics of the TFT are not impaired. Particularly, if the concentration ratio of nickel in the impurity region and the active region is set to 10 times or more, the impurity region can be activated while maintaining the amorphous property of the active region by optimizing the annealing temperature and time. Hereinafter, the present invention will be described in more detail with reference to examples.

[0016]

[Embodiment 1] FIG. 1 shows a cross-sectional view of a manufacturing process of this embodiment. First, a substrate (Corning 7059) 1 having a thickness of 30
A tantalum film having a thickness of 00 to 8000 Å, for example 5000 Å, was formed and patterned to form the gate electrode 2. Further, the surface of tantalum was anodized to form anodic oxide 3 having a thickness of 1000 to 3000Å, for example 2000Å. Further, the thickness of the gate insulating film is 1000 to 5000 Å, for example 1500 Å by plasma CVD method.
The silicon nitride film 4 is deposited, and subsequently, an intrinsic (I-type) amorphous silicon film having a thickness of 200 to 1500 Å, for example, 500 Å is deposited by the plasma CVD method and patterned to form the semiconductor region 5. (Fig. 1 (A))

Next, a photoresist was applied to the front surface of the substrate, and a mask 6 was formed in accordance with the pattern of the gate electrode by exposing the back surface of the substrate. (FIG. 1B) Then, using this mask 6, an impurity (phosphorus) was implanted into the semiconductor region 5 by an ion doping method. Phosphine (PH ₃ ) was used as a doping gas, and the acceleration voltage was set to 60 to 90 kV, for example, 80 kV. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 2 × 1
It was set to 0 ¹⁵ cm ^-2 . As a result, the N-type impurity region 7a,
7b was formed. (Fig. 1 (C))

Further, nickel ions were implanted by using the mask 6 by the ion doping method. The dose amount is 2 × 10 ¹³ to 2 × 10 ¹⁴ cm ⁻² , for example, 5 × 1
It was set to 0 ¹³ cm ^-2 . As a result, the N-type impurity region 26
The nickel concentration of a and 26b was about 5 × 10 ¹⁸ cm ⁻³ . (Fig. 1 (D))

Then, the impurities were activated by annealing at 500 ° C. for 4 hours in a hydrogen atmosphere (preferably a partial pressure of hydrogen is 0.1 to 1 atm). At this time, recrystallization was easily promoted in the impurity region into which nickel ions were previously implanted due to the crystallization promoting catalytic action of nickel.
Thus, the impurity regions 7a and 7b are activated.

Then, a silicon oxide film 8 having a thickness of 3000 Å is formed as an interlayer insulator by a plasma CVD method, and a contact hole is formed in this film, and a metal material such as, for example,
The electrodes / wirings 9a and 9b in the source region and the drain region of the TFT were formed by a multilayer film of titanium nitride and aluminum. The thin film transistor was completed through the above steps. (FIG. 1 (E)) The concentration of nickel in the impurity region and active region of the obtained thin film transistor was measured by the secondary ion mass spectrometry (SIMS) method, and the former was 1 × 10 ^{18 to} 5 × 10 ^18.
cm ^-3 , the latter was below the measurement limit (1 × 10 ¹⁶ cm ^-3 ).

[Embodiment 2] FIG. 2 shows a cross-sectional view of a manufacturing process of this embodiment. First, the substrate (Corning 7059) 1
A tantalum film having a thickness of 3000 to 8000 Å, for example 5000 Å, was formed on the substrate 1 and patterned to form the gate electrode 12. Further, the surface of tantalum was anodized to form an anodic oxide 13 having a thickness of 1000 to 3000Å, for example 2000Å. Furthermore, a thickness of 1000 to 5000Å is formed as a gate insulating film by the plasma CVD method.
For example, a silicon nitride film 14 having a thickness of 1500 Å is deposited, and subsequently, a thickness of 200 to 1500 Å is formed by plasma CVD
For example, an intrinsic (I-type) amorphous silicon film of 500 Å was deposited and patterned to form a semiconductor region 15.
(Fig. 2 (A))

Next, a photoresist was applied to the front surface of the substrate, and a mask 16 was formed in accordance with the pattern of the gate electrode by exposing the back surface of the substrate. (FIG. 2B) Then, using this mask 16, an impurity (phosphorus) was implanted into the semiconductor region 5 by an ion doping method. Phosphine (PH ₃ ) is used as a doping gas,
The acceleration voltage was 60 to 90 kV, for example 80 kV. The dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ^-2 , for example, 2 ×
It was set to 10 ¹⁵ cm ^-2 . As a result, the N-type impurity region 17
a and 17b were formed. (Fig. 2 (C))

Next, a nickel silicide film (chemical formula NiSi _x , 0.4 ≦ x ≦ 2.5, for example x) having an average thickness of 5 to 200 Å, for example, 20 Å is formed by the sputtering method.
= 2.0) 18 was formed on the entire surface as shown in the figure. 20
At a thickness of about Å, the film was not continuous and rather appeared as an aggregate of particles, but there is no problem in this example. (Fig. 2 (D))

Then, the impurities were activated by annealing at 450 ° C. for 4 hours in a hydrogen atmosphere (preferably a partial pressure of hydrogen is 0.1 to 1 atm). At this time, the nickel silicide film 1 is formed on the N-type impurity regions 17a and 17b.
Nickel atoms diffused from No. 8, and recrystallization easily proceeded by the catalytic action of nickel for promoting crystallization. Thus, the impurity regions 17a and 17b are activated.

Then, a silicon oxide film 19 having a thickness of 3000 Å is formed.
Is formed by plasma CVD as an interlayer insulator,
A contact hole is formed in this, and the TFT is made of a metal material, for example, a multilayer film of titanium nitride and aluminum.
Source / drain region electrodes / wirings 20a, 20
b was formed. The thin film transistor was completed through the above steps. (FIG. 2 (E)) The concentration of nickel in the impurity region and active region of the obtained thin film transistor was measured by the secondary ion mass spectrometry (SIMS) method, and the former was 1 × 10 ^{19 to} 3 × 10 ^19.
cm ⁻³ , the latter was 1 × 10 ^{16 to} 5 × 10 ¹⁶ cm ⁻³ .

[0026]

The present invention is a technique that is indispensable for performing the source and drain regions, which were conventionally formed by forming an N-type silicon film, by the ion doping method. As described above, the present invention is superior in yield and reliability to other competing technologies such as laser annealing technology. Thus, the present invention is an industrially useful invention.

[Brief description of drawings]

1A to 1C are cross-sectional views of a manufacturing process of Example 1.

2A to 2C are cross-sectional views of a manufacturing process of Example 2.

[Explanation of symbols]

 1 ... Substrate 2 ... Gate electrode (tantalum) 3 ... Anodic oxide (tantalum oxide) 4 ... Gate insulating film (silicon nitride) 5 ... Semiconductor region (amorphous silicon) 6 ... Mask 7 ... Source / drain region 8 ... Interlayer insulator (silicon oxide) 9 ... Metal wiring / electrode (titanium nitride / aluminum)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/265 21/324 Z 8617-4M

Claims (9)

[Claims] 1. A gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, and a semiconductor layer formed on the gate insulating film, wherein the semiconductor layer has a pair of impurities. An active region sandwiched between the region and the impurity region is provided,
The concentration of the catalytic element that promotes crystallization in the impurity region is
A thin film transistor which is larger than that of the active region. 2. The thin film transistor according to claim 1, wherein the catalyst element is at least one of nickel, iron, cobalt, and platinum. 3. The thin film transistor according to claim 1, wherein the concentration of the catalytic element in the impurity region is 10 times or more that of the active region. 4. The thin film transistor according to claim 1, wherein the active region is substantially amorphous silicon. 5. A gate electrode formed on a substrate, a gate insulating film formed on the gate electrode, and a semiconductor layer formed on the gate insulating film, wherein the semiconductor layer has a pair of impurities. An active region sandwiched between the region and the impurity region is provided,
The concentration of the catalyst element that promotes crystallization in the impurity region is 1
A thin film transistor having a concentration of × 10 ¹⁷ cm ^-3 or higher. 6. The concentration of the catalytic element according to claim 5,
A thin film transistor having the lowest value measured by secondary ion mass spectrometry. 7. A first step of forming a gate electrode on a substrate, and a second step of forming a gate insulating film to cover the gate electrode.
And a third step of forming an amorphous silicon film on the gate insulating film, and a doping impurity and a catalyst element for promoting crystallization are added to the amorphous silicon film according to the shape of the gate electrode. 4. The method for manufacturing a thin film transistor, comprising: 8. A first step of forming a gate electrode on a substrate, and a second step of forming a gate insulating film to cover the gate electrode.
And a third step of forming an amorphous silicon film on the gate insulating film, a fourth step of adding a doping impurity to the amorphous silicon film according to the shape of the gate electrode, and the amorphous silicon. A fifth step of depositing a material having a catalytic element on the film, the method for manufacturing a thin film transistor. 9. The thin film transistor according to claim 8, wherein the material having a catalytic element is a compound of the catalytic element and silicon.