JPH06243042A - Storage controller - Google Patents

Abstract

PURPOSE:To relieve the frequent occurrence of cache waiting due to a fixed allocation limit value to request and to shorten response time for the input/ output request. CONSTITUTION:A cache management part 33 sets the limit value to cache quantity which can be allocated for a part of the request among the requests using a cache and the allocation of the cache is controlled. A load information management part 34 monitors the load state of the cache and obtains the cache allocation limit value corresponding to the load state. When the change of the limit value becomes necessary, the cache management part 33 changes the limit value and controls the allocation of the cache.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device control device, and more particularly to a storage control device incorporating a cache.

[0002]

2. Description of the Related Art Known examples of cache control technology are shown below.

Japanese Patent Laid-Open No. 55-157053 discloses a write-after processing technique in a control device having a disk cache. In this technique, the control device ends the write request at the stage when the write data received from the processing device is written in the cache. The process of writing the data received from the processing device and stored in the cache to the disk device is performed later by the control device. This write after process speeds up the write process.

A known example of the basic control technology of the disk cache with a write-after function is the control disclosed in Japanese Patent Application No. 3-25994. As a problem caused by the application of the write-after process, there is a cache full state due to a difference in data transfer speed between the channel side and the disk device side.

In the case of read data, since the same data exists in the disk device, it is possible to erase the cache data and store other data at any time. On the other hand, when the write-after process is performed, the updated data exists only in the cache when the write request ends. Therefore, the write data on the cache must be left until it is written to the disk device. In addition, since the data transfer speed on the drive side is slower than the data transfer speed on the channel side, if the frequency of write requests increases, the cache is occupied by write data that cannot be erased.

According to this conventional example, the storage control device detects the amount of write data in the cache, the inflow amount of write data into the cache of each storage device, and the outflow amount of write data by the write-after processing, For the storage device of the inflow amount> outflow amount, the cache allocation limitation for the write data and the data writing to the storage device are executed with priority. With this technique, it is possible to avoid performance degradation of the entire system due to the full state of the cache, and to appropriately allocate the cache memory allocation for each storage device.

[0007]

On the other hand, in the input / output processing of data in the storage device, the difference in time zone or the processing form (online processing / batch processing), and further,
The cache load (access frequency, hit rate, cache usage) changes depending on the type of data (eg, sequential access data, random access data). Therefore, for a write request, it is necessary to set an appropriate cache allocation limit value according to the load state of the cache and allocate the cache.

For example, if a conventional fixed limit value is set for the write data amount on the cache, the cache resources may not be effectively used. If the limit value of the allocation amount for write-pending data on the cache is too smaller than the appropriate value, the response time will be delayed due to the occurrence of cache empty wait, and the effect of the write-after process will be reduced. On the other hand, if the limit value is too large, there is a problem that the read hit rate is lowered.

In the above-mentioned Japanese Patent Application No. 3-25994, there is provided means for setting a limit value for the amount of write data in the cache by an instruction from the central processing unit. No reference is made to changing the value. However, in the case of a storage control device that receives data input / output requests from a plurality of processing devices, it is desirable for the storage control device to set the cache allocation limit value.

An object of the present invention is to set a cache allocation limit value for each use purpose of the cache, and to control the limit value according to the use state of the cache so as to effectively use the resources of the cache. An object is to provide a storage control device.

[0011]

In order to achieve the above object, the storage control device according to the present invention uses the following means.

(1) For requests requiring cache allocation, read / write requests for data in the storage device issued by the central processing unit, and a plurality of requests issued for internal control of the storage control unit. There is. For some of these request types, a limit value is set for the cache amount that can be assigned to the request.

(2) At every unit time, at least one piece of information (absolute amount) of the number of requests issued, the amount of cache allocation, and the number of cache hits of each request requiring cache allocation described in (1) is measured.

(3) A change amount within a unit time is generated from the information (absolute amount) described in (2) measured at a certain time point t and the same information (absolute amount) measured one unit time before t. .

(4) The absolute amount measured in (2) above and the change amount generated in (3) are held as cache load information.

(5) The necessity of changing the limit value set in (1) is judged from the cache load information held in (4) above.

[0017]

The storage control device of the present invention has a cache memory divided into a plurality of fixed-length blocks (cache segments).

When a read request for the data in the storage device is issued, the storage control device determines whether the requested data exists in the cache. Hereinafter, the case where it exists will be described as a hit, the case where it does not exist will be described as a miss, and the judgment will be described as a hit / miss judgment. If there is a hit, the data in the cache is transferred to the processing device. In the case of a miss, the number of cache segments that can store the data of the storage device requested to be read is allocated, the data is loaded into the cache segment, and the data is transferred to the processing device. Similarly, when a write request is issued, in the case of a hit, write data is written to the cache segment. In the case of a miss, a cache segment is allocated, data in the storage device is loaded into the cache, and write processing is performed. Further, the write processing is ended when the write data is written to the cache, and the write data is written to the storage device later (write after processing).

The cache full state described in the prior art is a case where the write data occupies the cache, but this problem is that the allocation of the cache segment is performed for a specific request. Caused by. In order to avoid this problem, in the storage control device of the present invention, first, among the requests requiring a cache according to (1), those that may occupy the cache are arbitrarily limited in the number of allocated segments. Set the value.

However, depending on the state of use of the cache, the cache segment cannot be assigned because the limit value is set even though there are sufficient cache segments that can be assigned to the entire cache. There may be a case where a request to be made occurs. In order to effectively use the cache, it is possible to tune this limit value according to the state of the cache.

Therefore, the storage control device of the present invention is as follows.
The usage state of the cache is measured by (2). The information to be measured is the number of times each request was issued within the unit time,
The number of hits and the number of misses. Next, the amount of change of these pieces of information is generated by (3). These (2)
The information obtained in (3) is held in (4). Based on these information, it is determined by (5) whether the cache segment allocation limit value for each request is appropriate,
When the change is necessary, the limit value is reset according to (1).

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an outline of the control configuration of a storage control device of the present invention will be shown using FIG. The storage control device 3 of this embodiment comprises the following components. Note that the connection of each component in FIG. 1 is indicated by a control line (thin line) or a data transfer path (thick line). Cache memory 3
Reference numerals 1 and 32 denote non-volatile and duplicated cache memories. Since the contents of the two cache memories are the same, the description of the present embodiment will be made mainly using the cache memory 31.

The cache management unit 33 controls cache allocation and has a limit value setting function 302 and a load information measuring function 303, which are features of the present invention.

The load information management unit 34 monitors the usage state of the cache and has a load information generation function 304 and a limit value determination function 306 as features of the present invention.

The control memory 35 is a non-volatile memory for storing control information of the storage control device 3, and stores a table corresponding to the load information holding function 304. Regarding other control information stored in the control memory 35,
It will be described later as necessary.

The channel controller 36 receives and executes a data input / output request of the storage device 2 issued by the processing device 1. The channel control 37 has an interface function between the processing device 1 and the disk control device 3. Input / output request reception from the processing device 1 and data transfer to the processing device 1 are performed via the channel control 37.

The drive controller 38 controls data transfer between the disk device 2 and the disk controller. The drive control 39 has an interface function between the disk control device 3 and the disk device 2. Each of the cache management unit 33, the load information management unit 34, the channel control unit 36, and the drive control unit 38 described above is a program in the microprocessor of the disk control device 3.

The cache memory 31 is divided into fixed length blocks. The limit value setting function 302 is means for setting a limit value for the number of cache block allocations. The load information measuring function 303 is a function of measuring cache load information (request issuance count, hit count, miss count) for each request for each unit time. In the load information generation function 304,
From the cache load information measured by the load information measuring function 303, the change state and the like are obtained. The load information holding function 305 holds the cache load information obtained by the load information measuring function 303 and the load information generating function 304. The limit value determination function 306 determines the cache allocation limit value using the cache load information held in 305.

FIG. 2 shows an outline of the flow of data when the processor 1 issues a read request for data in the disk device 2. The channel control unit 36 that has received the request
First, referring to the control memory 35, it is determined whether the requested data exists in the cache 31 (hit) or does not exist (miss). This is called a hit / miss decision. The hit / miss determination process will be described later. If the result of the determination is a hit, the cache 31
Data is transferred to the processing device 1. When a miss occurs, the data is first transferred from the disk device 2 to the cache 31 and then from the cache 31 to the processing device 1.
The data is transferred to the processing device 2 and the read request ends.

FIG. 3 shows an outline of a data flow when the processing device 2 issues a write request for data in the disk device 2. Channel control unit 3 that received the request
Similarly to the case of the read request, 6 refers to the control memory and makes a hit / miss determination. If it is a hit, the update data is written to the data on the cache 31. If a miss occurs, first, the data is transferred from the disk device 2 to the cache 31, and then the updated data is written. In either case of hit / miss, the write request is terminated when the update data is written in the cache 31. At this time, the data that has been written to the cache 31 and has not been reflected to the disk device 2 is called write pending data. The write-pending data on the cache 31 will be transferred to the disk device 2 by the drive control unit 38 later.
Is written to. This is called write-after control.

Next, the structure and control of the cache memory 31 will be described. The cache memory 31 is divided into blocks called cache slots 311 as shown in FIG. For management of each cache slot, a slot control block (hereinafter referred to as SCB) shown in FIG.
Abbreviated) 50 is used. The maximum length of one cache slot is a length that can store data for one track of the disk device. The SCB 50 has a queue type 500, a forward pointer (FP) 501, a backward pointer (BP) 502,
It also includes slot management information 503. In addition, SCB
50 is stored in the control memory 35. Next, management of a plurality of SCBs in the control memory 35 will be described. The SCB 50 is the forward pointer 50 as shown in FIG.
1 and a backward pointer 502. SCB
All 50 are queue-managed in the control memory 35 by the above-mentioned bidirectional pointers 501 and 502. As shown in FIG. 6, the type of queue is the empty SCB management queue 35.
2, the reusable SCB management queue 354, and the write-pending SCB management queue 356.

The empty SCB management queue 352 is a queue that connects SCBs 50 that manage cache slots that are not assigned to data in the disk device 2. An empty SCB pointer 52 is at the beginning of the queue and N at the end.
It is ull. The corresponding SCB 50 is bidirectionally connected by the forward pointer 501 and the backward pointer 502. When the corresponding SCB does not exist, the empty SCB pointer indicates null.

The reusable SCB management queue 354 holds data in cache slots, but if necessary, an SCB that manages cache slots that can be used to allocate new data. It is a connecting cue. Each cache slot corresponding to each SCB 50 in the reusable SCB queue 352 may have a future cache hit.

The SC to be reused from these SCBs
When selecting B, select SCB that is unlikely to cause a cache hit. Specifically, the S that has not been accessed for the longest time among the SCBs connected to the queue.
Select CB. Therefore, as a method of connecting the reusable SCB management queue 352, LRU (Least Recently Use)
d) Use the method. The head of the reusable SCB management queue 354 is an MRU (Most Recently Used) pointer 54. This pointer points to the most recently accessed SCB. Conversely, the end of the queue is the LRU pointer 57. As mentioned above, this pointer points to the SCB that has not been accessed for the longest time in the queue. When the SCB in this queue has a cache hit, the SCB is replaced on the MRU side. In this queue, the SCB forward pointer 501 points to the MRU side, and the backward pointer 502 points to the LRU side. The write pending SCB management queue 356 is a queue that connects the SCBs corresponding to the slots containing the write pending data on the cache.

Since the storage control device 3 of this embodiment performs the write-after control as described above, the update data on the cache is not written in the disk device 2. Therefore, the write pending SCB management queue 3
The SCB 50 in 56 is an empty SCB until the update data of the cache slot is written to the disk device 2.
Or it cannot be a reusable SCB. Also,
This write pending SCB management queue is also managed by the LRU method, the head is the MRU pointer 56, the tail is the LRU pointer 57, and the forward pointer 501 of the SCB is M.
The RU side indicates the LRU side, and the backward pointer 502 indicates the LRU side.

In this embodiment, when performing the write-after process, the slot to be written is basically selected from those which are less likely to be hit in the future. That is, the selection is made from the LRU side in the write pending SCB management queue. Therefore, the SCB corresponding to the slot written in the disk device 2 by the write-after process is replaced on the LRU side of the reusable SCB management queue 354. Also, S in the write pending SCB management queue 356
When the CB has a cache hit, the SCB is replaced on the MRU side.

As shown in FIG. 7, the control memory 35 includes
In addition to the three types of SCB management queues 352, 354, 356, a cache management table 360 and a cache load information table 362 are prepared. The contents of these two tables are the cache management unit 33 and the load information management unit 34.
Is referred to and updated by. Details of the contents of the table will be described later. In addition, the disk controller 3 of this embodiment
The control information is exchanged via the control memory 35, but the control information other than the control information which characterizes the present invention is not shown.

FIG. 8 shows the contents of the cache management table 360. This table 360 is used by the cache management unit 3
3 writes the load information of the cache, and the load information management unit 34 refers to it. The information written in this table 360 includes the number of empty SCBs 3601, the number of available SCBs 3602, the number of write-pending SCBs 3603, and the number of requests issued per unit time (3605) in the entire cache.
~ 3607) and read hit / miss count (3608,36)
09). The allocation wait occurrence flag 3610 is a flag indicating that a write request in the slot empty wait state is generated due to the slot allocation limit value. When the load information management unit 34 determines to change the limit value,
Limit value change processing is performed using the limit value change flag 3617, the current limit value 3618, and the new limit value 3619 of this table 360.

FIG. 9 shows the cache load information table 362.
Indicates the contents of. In this table 362, the load information management unit 34 records the data history of the cache management table 360,
It is a table for holding a history of information generated by using these data for a fixed time (n unit time). The contents are the issue count history information by request 3620, the issue count change amount history information by request 3621, the read / write ratio history information 3622, the read / write ratio change amount history information 3623,
Queue-specific SCB number history information 3624, queue-specific SCB number change amount history information 3625, read hit rate history information 36
26, read hit rate change amount history information 3627.

The configuration of the embodiment of the storage control device of the present invention has been described. Next, the processing that characterizes the present invention will be described.

The disk control device 3 of this embodiment receives a read / write request for data of the disk device 2 issued by the processing device 1 and performs processing. As aforementioned,
The disk control device 3 performs write-after control. In order to prevent the cache from being occupied by the write pending data on the cache, in this embodiment, a limit is set on the cache slot allocation for the write request. In the case of a read miss, if a free SCB or a reusable SCB exists, a cache slot is assigned.

However, for a write miss, an empty SC
B or even if there is a reusable SCB,
Slots above the limit are not assigned. A write request that cannot be assigned a slot is written in the write pending S
Processing must be waited until the number of CBs falls below the limit value. When a cache hit occurs for a read / write request, read / write is performed for the slot. Therefore, when the number of write pending slots exceeds the limit value, slot allocation is not performed at the time of a write miss, but in the case of a write hit, the number of write pending slots may exceed the limit value. When the number of write pending slots exceeds the limit value, the disk control device 3 increases the frequency of write after processing and performs destage.

FIG. 10 shows the function of the cache management unit 33 which performs such cache allocation control. The limit value initial setting function 331 sets an initial value to the allocation limit value of the number of write pending slots. The cache slot management function 332 performs cache slot allocation (SCB management) based on the above limit value, measures cache load information associated therewith, and writes the cache load information in the cache management table. The limit value change setting function 333 resets the limit value when the initial limit value needs to be changed.

FIG. 11 shows a processing flow of the cache slot management 332. The cache management unit 33 receives the request for the slot in step 3320. If there is a request, a hit / miss decision is made in step 3321.
If the requested slot is on the cache (hit), the SCB queue is replaced in step 3323.

If the requested slot does not exist in the cache (miss), step 3324 determines if the slot can be allocated. Specifically, in the case of a write request, it is determined whether the allocation limit value is exceeded. If it can be assigned, a slot assignment process is performed in step 3325. If the slot cannot be assigned, the write request is placed in a wait state and the assignment wait occurrence flag 3610 of the cache management table 360 is turned on.
To In this process, the number of issues for each request type, the number of hits / misses, and the number of SCBs for each queue type are measured and written in the cache management table.

FIG. 12 shows a processing outline flow of the limit value change setting function. The limit value change setting function 333 of the cache management unit 33 refers to the limit value change flag 3617 of the cache management table 360 in step 3330. If the flag 3617 is off (= 0), it is not necessary to reset the limit value, and the process ends. When on (≠),
Since it is necessary to change the limit value, first, step 333.
At 1, the lock on the cache management table 360 is acquired.

Next, at step 3332, a new limit value 3619 in the cache management table 360 is set as a slot allocation limit value for the write request of the cache management unit 33. Then step 33
At 33, the changed limit value is written in the current limit value 3618. The limit value change flag is turned off in step 3334, the lock is released in step 3335, and the limit value change setting process ends. The subsequent cache allocation control is performed based on the limit value reset in the above process.

It is the load information management unit 34 that writes a new limit value 3619 in the cache management table 360 referred to in the above processing, turns on the limit value change flag 3617, and notifies the necessity of changing the limit value. is there.

FIG. 13 shows a processing outline flow of the load information management unit 34. In step 3400, the unit time is monitored. The load information management unit 34 collects and monitors the cache load information for each unit time, and determines a limit value for effectively using the cache as necessary. If the unit time has elapsed, cache load information is acquired in step 3402. The cache load information is information in the cache management table 360 measured by the cache management unit 33 and information obtained by processing this information, and these are written in the load information management table 362.

Next, at step 3404, the load information management table 362 is referred to, the limit value of the cache slot allocation for the write request is determined, and it is determined whether or not the change is necessary. If it is determined that it is not necessary to change the limit value, the process returns to step 3400. If you need to change
In step 3406, it is determined whether the change is possible. If not possible, the process returns to step 3400. If it can be changed, the limit value is changed in step 3408. Step 3
At 410, it is determined whether to continue the process. If the process is to be continued,
Returning to step 3400, the process ends if it is not to continue.

The details of the processing of the load controller 34 will be further described with reference to FIGS. 14 and 15. The blocks and their numbers shown by dotted lines in this figure correspond to the steps of the outline flow in FIG.

In step 3420, it is monitored whether the unit time has elapsed. This corresponds to step 3400 of the overview flow.

As processing corresponding to step 3402 (acquisition of load information) of the outline flow, steps 3421 to 3421 are executed.
424 is shown. First, in step 3421, the cache management table 360 in the control memory 35 is copied to the internal memory (Data Storage, hereinafter abbreviated as DS) of the microprocessor including the load information management unit 34. Next, at step 3422, the load information table 362 is copied to the DS. In step 3423, the load information is generated by referring to the two tables 360 and 362 copied to the DS. In step 3424, the load information management table 362 on the DS is updated.

The information generated in step 3423 includes the issuance number change amount for each request 3621 and the read / write ratio of 3 shown in the cache load information table 362 of FIG.
622, read / write ratio change amount 3623, queue-specific S
The CB number change amount 3625, the read hit rate 3626, and the read hit rate change amount 3627.

In step 3424, step 3423
And the number of issuances by request (3604 to 360)
7) and the queue-specific SCB count (3624) are written in the load information management table 362. This table is controlled by the FIFO so as to store load information for measurement (generation) n times.

Next, steps (3425 to 3427) corresponding to the processing of step 3404 of the outline flow will be described.

In step 3425, the load information management table 362 is referred to, and the slot allocation limit value for the write request corresponding to the cache usage state is obtained. With regard to this step, two types of algorithms (FIGS. 17 and 18) will be given later and will be described in detail as an example of a method for obtaining the limit value. In step 3426, the limit value obtained in the previous step is compared with the current limit value (see the cache management table 360) to determine whether or not the limit value needs to be changed. If not, step 34
At 27, the updated part of the load information management table 362 on the DS is written in the same table of the control memory 35. If the change is necessary in step 3426, the process proceeds to step 3430 in FIG.

Steps 3430 to 3432 are processes corresponding to the outline flow 3406.

In Step 3430, Step 3426
The current limit value is compared with the limit value (new limit value) obtained in. As a result of the comparison, if the new limit value is larger, that is, if the number of allocatable slots is increased, the process proceeds to step 3433. On the contrary, when the current limit value is larger, that is, when the number of allocatable slots is reduced, in step 3431, the new limit value and the number of write pending SCBs are compared. If the result of comparison is that the new limit value is greater, step 34
Proceed to 33. Conversely, if the new limit is less than the number of write pending SCBs, step 3432
Proceed to. In step 3432, the increase in the frequency of write after processing is notified to the drive control via the control memory 35. By this processing, the frequency of write after control is increased and the amount of write pending slots is decreased, and then the routine proceeds to step 3433.

Steps 3433 and 3434 are processing (change of limit value) corresponding to step 3408 of the general flow. Actually, the change of the limit value is notified to the cache management unit 33 via the control memory 35.

First, in step 3433, the control memory 3
The new limit value 36 is added to the cache management table 360 of
Write 19. Next, in step 3434, the limit value update flag 3617 is set to ON (≠ 0). As described above, the cache management unit 33 refers to the flag 3617 to change the limit value. Next, in step 3435, the same processing as in step 3427 (writing the change in the load information table 362 to the control memory 35)
I do. The next step 3436 is the outline flow 341.
Corresponds to 0. In this step, the load information management unit 34
It is determined whether to continue the process of. If you want to continue processing,
The process returns to step 3420 and ends if not continued.

Next, an example of the processing of step 3425 (processing for obtaining the slot allocation limit value for the write request corresponding to the cache usage state) will be shown. As a premise, FIG. 16 shows a variation range of the slot allocation limit value for a write request. In FIG. 16, A, MAX, and MIN are limit values of the number of slots that can be assigned to a write request when the number of slots in the entire cache is 100%, and the unit is%. In the disk control device of the present invention, the range in which this limit value is changed is between MIN and MAX. A is an initial value set by the limit value initial setting process 331 of the cache management unit 33 shown in FIG. MIN is the minimum limit value. MA
X is the maximum limit value. No matter how the cache is used, MIN% slots of the cache can be allocated to write requests, and conversely, MAX
No more than% slots will be allocated for write requests. Further, α and β in FIG. 16 are changes in the MAX direction (increase direction) and the MIN direction (decrease direction) with reference to A, respectively.

First, a first example will be described with reference to FIG.
In the setting of the limit value in this example, when the read / write ratio is monitored and the ratio of the read request compared to the write request is decreasing and there is a write request in the slot allocation waiting state, Increase the limit value of the number of slots that can be assigned. However, the read hit rate is also monitored at the same time, and if the read hit rate is decreasing, the read hit rate may be further lowered by increasing the slot allocation limit value for write requests. Make a match and increase the frequency of light after processing.

FIG. 17 shows the flow of the above processing. In step 3450, it is determined whether or not there is a write request waiting for slot allocation by referring to the allocation wait occurrence flag 3610. If the flag is off,
No wait state has occurred. In this case, there is no effect even if the limit value is raised, so this processing ends. If it is ON, there is a slot allocation wait, and it is desired to raise the limit value, and therefore the routine proceeds to step 3451.
In this step, it is determined whether the ratio of read requests to write requests is increasing or decreasing. Specifically, this table 3
Of the information measured n times stored in 62, the latest x
With reference to the read / write ratio change amount of (n ≧ x) times, if it is monotonically decreasing, it is regarded as decreasing, and the process proceeds to step 3452. If the lead ratio is not considered to be decreasing,
The limit value is not changed. In this case, step 3454
The process for increasing the frequency of the write after process is performed.

Next, at step 3452, the read hit rate history information 3626 and the change amount history information 3627 are referred to, and it is determined whether the read hit rate is low or in a decreasing direction. Specifically, in the read hit rate history information 3626, when the latest read hit rate is lower than a reference value set for control in advance, it is determined that the read hit rate is low, and the limit value is set. Will not be changed. Even if the read hit rate is higher than the reference value, if it is determined by referring to the change amount history information 3627 that the read hit rate is decreasing, the limit value is not changed, and thus the step 3453 is performed. Then, the process proceeds to the process of increasing the frequency of the write after process. The process of step 3453 is performed in the same manner as step 3432 of FIG.

If the read hit rate is equal to or higher than the reference value and is not in a decreasing state, the process proceeds to the next step 3455. In this step, MAX is compared with the current limit value. Although the limit value is increased in the next step and thereafter, if the current limit value is MAX, further increase is not performed, and therefore the process proceeds to step 3453. The current limit is M
If it is smaller than AX, the process proceeds to the next step 3456.
In step 3455, A is compared with the current limit value. When the current limit value is A or more, in step 3457, (current limit value + α) is set as a new limit value. If the current limit value is smaller than A, in step 3458, (current limit value + β) is set as the new limit value, and the process ends. After this, the process proceeds to step 3426 of FIG.

A second example will be described with reference to FIG. In the limit value setting method in this example, the presence or absence of a sequential write request is monitored. When a sequential write request is executed, the number of write pending slots increases, but these slots are less likely to be referenced (cache hit) thereafter. In cache control, it is important to leave a slot with a high probability of hitting on the cache. Therefore, it is better not to leave the sequential write slot in the cache for a long time and write it to the disk device. Therefore, in this example, when a sequential write request is detected, the slot allocation limit value for the write request is lowered, thereby performing control to prompt writing of write data to the disk device.

First, at step 3460, it is determined from the request-based issuance count history information 3620 of the load information table 362 whether there is a sequential write request. If none,
This process ends. If a request has been issued, compare the current limit with the MIN. If the current limit value is MIN, further limit value reduction is not performed, and the process ends. Next, in step 3464, A is compared with the current limit value. When the current limit value is A or less, (current limit value-β) is set as a new limit value in step 3466. If the current limit value is larger than A, in step 3468, (current limit value-α) is set as the new limit value, and the process ends. After this, step 3 in FIG.
Proceed to 426.

Above, two examples of limit value change determination have been shown.
Further, it is possible to control the setting of the limit value by combining the above two methods.

As in the embodiment of the present invention, the cache allocation limit value is set for each request that uses the cache, and further the limit value is changed according to the usage state of the cache. It is possible to provide a disk control device intended for use.

[0071]

The storage control device of the present invention prevents the occupation of the cache by a specific request by setting a cache allocation limit value in a part of the cache use request,
Further, by monitoring the load state of the cache and controlling the limit value to be changed according to the load state, it is possible to effectively use the resources of the cache memory.

In the embodiment of the present invention, of the read / write requests for the data in the disk device, a limit value is set for the cache slot allocation for the write request. The load information management unit monitors the read / write ratio and the read hit ratio, and raises the allocation limit value for the write request when the read to write ratio decreases and the read hit ratio does not tend to decrease. Further, the write pending slot by sequential write is less likely to hit the cache even if it is left on the cache. Therefore, when it is detected that a sequential write request is issued, the cache slot allocation limit value is lowered and the destage frequency to the disk device is increased. In this way, the cache can be effectively used by setting the limit value according to the load state of the cache. As a result, the number of occurrences of waiting for free cache is reduced, and the response time can be shortened.

[Brief description of drawings]

FIG. 1 is a control block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a flow of read data in the embodiment of the invention.

FIG. 3 is a block diagram showing a flow of write data according to the embodiment of the invention.

FIG. 4 is an explanatory diagram of a cache.

FIG. 5 is an explanatory diagram of a slot control block.

FIG. 6 is an explanatory diagram of management of a slot control block.

FIG. 7 is a block diagram showing an outline of the inside of a control memory.

FIG. 8 is an explanatory diagram showing a cache management table.

FIG. 9 is an explanatory diagram showing a cache load information table.

FIG. 10 is a functional block diagram of a cache management unit.

FIG. 11 is a flowchart of cache slot management.

FIG. 12 is a flowchart of limit value change processing.

FIG. 13 is a flowchart of the processing outline of a load information management unit.

FIG. 14 is a processing flowchart of a load information management unit.

FIG. 15 is a processing flowchart of a load information management unit.

FIG. 16 is an explanatory diagram showing a variation range of a slot allocation limit value with respect to a write request.

FIG. 17 is a flowchart showing an example (1) of limit value change determination.

FIG. 18 is a flowchart showing an example (2) of limit value change determination.

[Explanation of symbols]

3 ... Disk control device, 31 ... Cache memory, 33
... cache management unit, 34 ... load information management unit, 35 ... control memory.

Claims (3)

[Claims] 1. A storage controller, which is connected to a storage device and a processing device and has a cache memory composed of a plurality of blocks, wherein data of the storage device issued by the processing device to the storage control device is issued every unit time. I / O request,
A means for measuring at least one of the number of times of issuance, the number of times that the block containing the requested data did not exist in the cache, or the number of times that the block containing the requested data already existed in the cache; , Means for generating data representing the change or ratio of the data for each unit time from the data, means for holding the data and the data representing the change or ratio as cache load information, and the load information A storage control device comprising: means for obtaining a limit value of the number of blocks allocated to a part of the input / output request using part or all of the above; and means for setting the limit value. 2. The storage control device according to claim 1, wherein the request is a read request or a write request for data in a storage device, and a part of the request is the write request. 3. A means for measuring the number of blocks allocated to write data in a cache according to claim 2,
A storage controller comprising: means for comparing the number of blocks with a limit value; and means for increasing the frequency of processing for writing write data in the cache to a storage device.