JPH06244710A - Outputting circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain an outputting circuit in which the inflow of currents from an outside through an output terminal can be prevented, and plural semiconductor integrated circuits having output signals whose voltage amplitude is different can be mutually connected in a simple and inexpensive constitution. CONSTITUTION:A P type enhancement MOS transistor 17 is connected between an output terminal 16 and a power source Vcc, and an N type enhancement MOS transistor 18 is connected between the output terminal 16 and a ground G. The output signal of the semiconductor integrated circuit is inputted from an input terminal 11 through an NAND circuit 13 and an AND circuit 14 to the gates of the both transistors 17 and 18. Also, an N type depletion MOS transistor 1 is connected between the output terminal 16 and the P type enhancement MOS transistor 17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit having a CMOS (Complementary Metal Oxide Semiconductor) structure which enables interconnection of a plurality of semiconductor integrated circuits having output signals having different voltage amplitudes.

[0002]

2. Description of the Related Art Conventionally, as an output circuit of this type, for example, one shown in FIG. 4 has been known. In this output circuit, a P-type enhancement MOS transistor 17 is connected between the output terminal 16 and the power supply Vcc, and the output terminal 1
An N-type enhancement MOS transistor 18 is connected between 6 and the ground G. The output terminal of the NAND circuit 13 is connected to the gate of the P-type enhancement MOS transistor 17, and the output terminal of the AND circuit 14 is connected to the gate of the N-type enhancement MOS transistor 18. Then, the high level (H) and low level (L) output signals of the semiconductor integrated circuit (not shown) from the input terminal 11 are directly inverted to one input terminal of the NAND circuit 13 and also via the inverter 15 Input to one input terminal of the circuit 14 respectively, and NAND and A
The control terminal 12 is connected to the other input terminals of the ND circuits 13 and 14.
To H and L control signals.

When the H control signal is input to the control terminal 12, when the H signal is input to the input terminal 11, the NAN
Since the output of the D circuit 13 becomes L and the P-type transistor 17 is turned on through the gate and the output of the AND circuit 14 becomes L and the N-type transistor 18 is turned off, the output terminal 16 corresponds to the input. The H signal is output. On the other hand, when an L signal is input to the input terminal 11, on the contrary, N
The output of the AND circuit 13 becomes H and the P-type transistor 1
Since 7 is turned off and the output of the AND circuit 14 becomes H and the N-type transistor 18 is turned on, the L signal corresponding to the input is output from the output terminal. Further, when an L control signal is input to the control terminal 12, when an H signal is input to the input terminal 11, the output of the NAND circuit 13 becomes H and the output of the AND circuit 14 becomes L, so that P Type and N-type transistors 17 and 18 are both turned off, and input terminal 1
Even if the signal of L is input to 1, the output of the NAND circuit 13 is H, the output of the AND circuit 14 is L, and both transistors 1
Both 7 and 18 are off, that is, the output terminal 16 is in a high impedance state.

[0004]

However, the output circuit of the conventional semiconductor integrated circuit described above is similar to the general output circuit.
Since a signal line having a bus structure is connected to the output terminal 16, a voltage signal having a large amplitude exceeding the level of the power supply Vcc or the level of the ground G is output from the semiconductor integrated circuit (not shown) connected to the signal line. Then, since the parasitic diode 19 or 20 shown by the broken line in FIG. 4 exists, a current flows into the power supply Vcc or the ground G, an invalid current flows and the power supply battery is exhausted. Occur. On the other hand, although it is not a CMOS output circuit, there is an output circuit in which N-type enhancement MOS transistors used in DRAM or the like are connected in series. In this circuit, a voltage signal from another semiconductor integrated circuit keeps the power supply Vcc level. If it exceeds, there is no problem, but if the voltage signal is below the ground G level, the same problem as described above occurs. Further, in this output circuit, since the H output signal is driven by the N-type enhancement MOS transistor, the output level is (Vcc-Vth).
However, in order to obtain the output level of Vcc, a pre-stage circuit for raising the gate voltage of this transistor is required, resulting in an increase in cost.

Therefore, the output circuit of the above-mentioned CMOS structure which does not have such a problem of cost increase, and the current does not flow even if a large amplitude voltage signal from another semiconductor integrated circuit is applied to the output terminal. Is absolutely necessary. Therefore, an object of the present invention is to provide a means for cutting off an inflowing current when a large-amplitude voltage signal is applied to the output terminal from another circuit. An object of the present invention is to provide an output circuit of a semiconductor integrated circuit, which can connect a plurality of semiconductor integrated circuits having signals to each other.

[0006]

To achieve the above object, a first output circuit of a semiconductor integrated circuit according to the present invention has a P-type enhancement MOS transistor connected between an output terminal and a power source, An N-type enhancement MOS transistor is connected between the output terminal and the P-type enhancement MOS transistor, and a signal is input to the gates of the P-type and N-type enhancement MOS transistors, respectively. An N-type depletion MOS transistor is connected to the. On the other hand, in the second output circuit of the present invention, instead of connecting the N-type depletion MOS transistor, a P-type depletion MOS transistor is connected between the output terminal and the N-type enhancement MOS transistor. is doing. In addition, the third output circuit of the present invention has a P-type depletion MOS transistor connected between the output terminal and the N-type enhancement MOS transistor in addition to the first output circuit.

[0007]

In the output circuit according to the first aspect of the present invention, an N-type transistor is provided between the output terminal and the P-type enhancement MOS transistor on the power supply side.
A type depletion MOS transistor is connected. For example, the gate of the N-type depletion MOS transistor is connected to a power source, and the semiconductor integrated circuit signal is input to the gate of the P-type enhancement MOS transistor and the gate of the ground-side N-type enhancement MOS transistor. Therefore, when the output signal of the semiconductor integrated circuit is H, the inverted L signal turns on the P-type enhancement MOS transistor instead of the N-type, and the N-type depletion MOS transistor also receives the power supply voltage applied to the gate. Since it is turned on at, an H signal is output from the output terminal. Here, since the N-type depletion MOS transistor is turned on even when the gate voltage (Vcc) is the same as the source voltage (output terminal voltage), at least the output level of Vcc can be obtained from the output terminal. Further, when a voltage of Vcc or more is applied to the output terminal from the outside, as soon as the voltage value exceeds the sum of Vcc and the absolute value of the threshold voltage Vth (<0) of the N-type depletion MOS transistor, this transistor is turned off. Turns off and shuts off the current flowing from the output terminal. Therefore, if the absolute value │Vth│ of the threshold voltage is set to be equal to or lower than the forward voltage of the parasitic diode existing between the output terminal and the ground, the inflow of current when the positive side of the voltage of Vcc or more is applied to the output terminal. Can be blocked. On the other hand, when the output signal of the semiconductor integrated circuit is L, the inverted H signal turns on the N-type enhancement MOS transistor instead of the P-type, so that the L signal is output from the output terminal.

According to another aspect of the output circuit, the P-type depletion MOS transistor is connected between the output terminal and the ground-side N-type enhancement MOS transistor. For example, the P-type depletion MOS
The gate of the transistor is connected to the ground, and the above N
The inverted output signal from the semiconductor integrated circuit is input to the gate of the type enhancement MOS transistor and the gate of the power source side P type enhancement MOS transistor. Therefore, when the output signal of the semiconductor integrated circuit is H, the inverted L signal turns on the P-type enhancement MOS transistor instead of the N-type, so that the H signal is output from the output terminal. On the other hand, when the output signal of the semiconductor integrated circuit is L, the inverted H signal causes P
The N-type enhancement MOS transistor is turned on instead of the N-type, and the P-type depletion MOS transistor is turned on even if the gate voltage is the same as the source voltage (G), so the L signal (≤G) is output from the output terminal. Is output. When a voltage below ground is applied to the output terminal from the outside, the voltage value is Vcc and P-type depletion MO.
As soon as the sum with the threshold voltage Vth (> 0) of the S-transistor is exceeded, this transistor is turned off, interrupting the current flowing from the output terminal. Therefore, when the threshold voltage Vth is set to be equal to or lower than the forward voltage of the parasitic diode existing between the output terminal and the power supply, it is possible to prevent the inflow of current when the negative side of the voltage higher than Vcc is applied to the output terminal. it can.

In the output circuit of the third aspect, the same N-type depletion MOS transistor as in the first aspect is provided between the output terminal and the P-type enhancement MOS transistor on the power supply side, and the N-type enhancement on the output terminal and the ground side. The same P-type enhancement MOS transistor as in claim 2 is connected between the MOS transistor and the MOS transistor. Therefore, similar to the above, when the output signal of the semiconductor integrated circuit is H, the P-type enhancement MOS transistor on the power supply side is turned on and the signal of H is output, and when the output signal of the semiconductor integrated circuit is L, the signal of ground side is output. The N-type enhancement MOS transistor is turned on and the L signal is output from each output terminal. Further, since the actions and effects described in the output circuit of claims 1 and 2 are exhibited, Vcc is applied to the output terminal.
Regardless of whether the above voltage is applied to the positive side or the negative side, the inflow of current from the output terminal can be prevented.

[0010]

The present invention will be described in detail below with reference to the embodiments shown in the drawings. FIG. 1 is a circuit diagram showing an example of a first output circuit of a semiconductor integrated circuit of the present invention. This output circuit is
The structure is the same as that of the conventional example described in FIG. 4 except that one type depletion MOS transistor is added, and the same members are denoted by the same reference numerals and description thereof is omitted. As shown in FIG. 1, the N-type depletion MOS transistor 1 is connected between the output terminal 16 and a P-type enhancement MOS transistor 17 on the side of the power supply Vcc, and its gate is connected to the power supply Vcc and its P well is connected. They are connected to the ground G respectively. Reference numeral 19 is a parasitic diode connected to the output terminal 16 by the output of another semiconductor integrated circuit (not shown).

The output circuit configured as described above operates as follows. First, in the state where the H control signal indicating that the operation is performed is input to the control terminal 12 of the output circuit, the input terminal 1
It is assumed that an H signal is input to 1 from a semiconductor integrated circuit (not shown). Then, the output of the NAND circuit 13 becomes L and the P-type enhancement MOS transistor 17 is turned on via the gate, and the N-type depletion MOS transistor 1 is also turned on at the power supply voltage Vcc applied to the gate, while the AND Since the output of the circuit 14 becomes L and the N-type enhancement MOS transistor 18 is turned off, the H signal corresponding to the input is output from the output terminal 16. Since the N-type depletion MOS transistor 1 is turned on even when the gate voltage is the same as the source voltage, the output voltage level of Vcc can be obtained from the output terminal 16. In other words, a high output voltage level of Vcc can be secured without an expensive front-end circuit for increasing the gate voltage of the transistor like the output circuit in which N-type enhancement MOS transistors described in the conventional example are connected in series. .

On the other hand, when an L signal is input to the input terminal 11 from the semiconductor integrated circuit, the NAND circuit 13 is turned on the contrary.
Output becomes H to turn off the P-type enhancement MOS transistor 17, and the output of the AND circuit 14 becomes H to turn on the N-type enhancement MOS transistor 18, so that the L signal corresponding to the input from the output terminal 16 Is output. Next, the control terminal 12 has an L indicating non-operation.
If the H signal is input to the input terminal 11 when the control signal is input to the input terminal 11, the output of the NAND circuit 13 becomes H and the output of the AND circuit 14 becomes L, so that the P type, N
The type enhancement MOS transistors 17 and 18 are both turned off. On the other hand, even if the L signal is input to the input terminal 11, the output of the NAND circuit 13 is H, the output of the AND circuit 14 is L, and both transistors 17 and 18 are Turns off. That is, when the L control signal is input to the control terminal 12, the output terminal 16 is in a high impedance state.

It is also assumed that a positive voltage of Vcc or more is externally applied to the output terminal 16 while the P-type enhancement MOS transistor 17 is turned on and the H signal is output. Then, the applied voltage value is Vcc
As soon as the sum of the absolute value of the threshold voltage Vth (<0) of the N-type depletion MOS transistor 1 is exceeded, the gate voltage (Vcc) of the transistor 1 becomes lower than the source voltage by Vth or more. Is turned off, and the current that is about to flow from the output terminal 16 is cut off. Therefore, if the absolute value | Vth | of the threshold voltage is set to be equal to or lower than the forward voltage (approximately 0.7V) of the parasitic diode 19 existing between the output terminal 16 and the ground G by another semiconductor integrated circuit, it is equal to or higher than Vcc. Even when a positive voltage is applied to the output terminal 16, it is possible to prevent the current from flowing into the output circuit.

FIG. 2 shows an example of a second output circuit of the semiconductor integrated circuit of the present invention. This output circuit has a P-type depletion MOS transistor on the ground G side.
The conventional example described in FIG. 4 has the same configuration except that the number is added, and the same members are denoted by the same reference numerals and description thereof is omitted. The P-type depletion MOS transistor 2
2, is connected between the output terminal 16 and the N-type enhancement MOS transistor 18 on the side of the ground G, and has its gate connected to the ground G and its substrate connected to the power supply Vcc, respectively. In addition, 20 is an output terminal 16
It is a parasitic diode due to the output of another semiconductor integrated circuit (not shown) connected to.

The output circuit configured as described above operates as follows. First, at the control terminal 12 of the output circuit, H
When the control signal is input, it is assumed that the H signal is input to the input terminal 11 from a semiconductor integrated circuit (not shown).
Then, the output of the NAND circuit 13 becomes L and turns on the P-type enhancement MOS transistor 17 via the gate, while the output of the AND circuit 14 becomes L and becomes N.
Since the type enhancement MOS transistor 18 is turned off, the H signal corresponding to the input is output from the output terminal 16. On the other hand, when an L signal is input to the input terminal 11 from the semiconductor integrated circuit, the output of the NAND circuit 13 becomes H, the P-type enhancement MOS transistor 17 is turned off, and the output of the AND circuit 14 becomes H. Then, the N-type enhancement MOS transistor 18 is turned on, and the P-type depletion MOS transistor 2 is turned on even when the gate voltage is the same as the source (ground side) voltage, so that at least the ground G level input from the output terminal 16 is made. It is possible to obtain an L signal corresponding to. That is, the low output voltage level of the ground G can be secured without separately requiring an expensive pre-stage circuit for adjusting the gate voltage of the transistor 2.

Next, when an L control signal indicating non-operation is input to the control terminal 12, either the H or L signal is input to the input terminal 11 as described in the embodiment of FIG. Both transistors 17 and 18 are turned off, and the output terminal 16 is in a high impedance state. Also,
When the N-type enhancement MOS transistor 18 is turned on and the L signal is output,
It is assumed that a negative voltage of Vcc or more is applied from the outside. Then, as soon as the applied voltage value exceeds the sum of Vcc and the threshold voltage Vth (> 0) of the P-type depletion MOS transistor 2, the gate voltage (G) of the transistor 2 is higher than the source voltage by Vth. Since it becomes higher than the above, the transistor 2 is turned off, and the current flowing from the output terminal 16 is shut off. Therefore, when the threshold voltage Vth is set to be equal to or lower than the forward voltage of the parasitic diode 20 existing between the output terminal and the ground by another semiconductor integrated circuit, Vcc
Even when the negative side of the above voltage is applied to the output terminal 16, it is possible to prevent the current from flowing into the output circuit.

FIG. 3 shows a third output circuit of the semiconductor integrated circuit of the present invention. This output circuit is the same output circuit as that of FIG. 1 having the N-type depletion MOS transistor 1, but has an output terminal 16 And N-type enhancement M
The same P-type depletion MOS transistor 2 as in FIG. 2 is connected between the OS transistor 18 and the OS transistor 18. Therefore, as described with reference to FIG. 1 and FIG. 2, when the output signal of the semiconductor integrated circuit (not shown) is H, the P-type enhancement MOS transistor 17 on the power supply Vcc side is turned on and the H signal becomes the above output signal. When L is L, the N-type enhancement MOS transistor 18 on the ground side is turned on, and L signals are output from the output terminals 16, respectively. Further, the N-type and P-type depletion MOS transistors 1 and 2 are connected to the output terminal 1 from the outside, as already described in FIGS.
Since the inflow of the current when a large amplitude voltage is applied to 6 is cut off, the output terminal 16 is simple and inexpensive.
Regardless of whether a positive or negative voltage signal of Vcc or more is applied to, the inflow of current from the output terminal 16 to the output circuit can be reliably prevented.

When a system is composed of a plurality of semiconductor integrated circuits, generally, either the power supply Vcc or the ground G is set to the reference level, so that the output terminal 16 is
Since either a high voltage of Vcc or higher or a low voltage of G or lower is applied, the measure of either FIG. 1 or FIG. 2 is sufficient. Since it is necessary to add masks one by one to manufacture the N-type and P-type depletion MOS transistors 1 and 2, the measure of FIG. 3 should be adopted only when the system is complicated. Incidentally, according to the embodiment shown in FIG. 3, it is a matter of course that all the measures can be taken.

[0019]

As is apparent from the above description, in the first output circuit of the semiconductor integrated circuit of the present invention, a P-type enhancement MOS transistor is provided between the output terminal and the power supply, and a P-type enhancement MOS transistor is provided between the output terminal and the ground. N-type enhancement MOS
In the case of connecting the transistors to each other and inputting signals to the gates of the P-type and N-type enhancement MOS transistors, respectively, an N-type depletion MOS transistor is connected between the output terminal and the P-type enhancement MOS transistor. Therefore, even if a positive voltage signal higher than the power supply voltage is applied to the output terminal, it is possible to block the inflow of current from the outside, and with a simple and inexpensive configuration, there are multiple output signals with different voltage amplitudes. The semiconductor integrated circuits can be connected to each other.

In the second output circuit of the present invention, instead of connecting the N-type depletion MOS transistor of the first output circuit, a P-channel is provided between the output terminal and the N-type enhancement MOS transistor. Since a type depletion MOS transistor is connected, even if a negative voltage signal higher than the power supply voltage is applied to the output terminal, the inflow of current from the outside can be blocked, and the configuration is simple and inexpensive. A plurality of semiconductor integrated circuits having output signals of voltage amplitude can be connected to each other. Furthermore, a third output circuit of the present invention is added to the first output circuit having an N-type depletion MOS transistor, and a P-type depletion MOS transistor is provided between the output terminal and the N-type enhancement MOS transistor. Since a transistor is connected, even if a positive or negative voltage signal higher than the power supply voltage is applied to the output terminal in a complicated system, the inflow of current from the outside can be blocked more reliably, and the output with different voltage amplitudes can be output. A plurality of semiconductor integrated circuits having signals can be connected to each other more reliably.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a first output circuit of a semiconductor integrated circuit of the present invention.

FIG. 2 is a circuit diagram showing a second output circuit of the present invention.

FIG. 3 is a circuit diagram showing a third output circuit of the present invention.

FIG. 4 is a circuit diagram showing an output circuit of a conventional semiconductor integrated circuit.

[Explanation of symbols]

1 ... N-type depletion MOS transistor, 2 ... P
Type depletion MOS transistor, 11 ... Input terminal, 12 ... Control terminal, 13 ... NAND circuit, 14 ... AN
D circuit, 15 ... Inverter, 16 ... Output terminal, 17 ... P
Type enhancement MOS transistor, 18 ... N type enhancement MOS transistor.

Claims (3)

[Claims] 1. A P-type enhancement MOS transistor is connected between an output terminal and a power supply, an N-type enhancement MOS transistor is connected between the output terminal and a ground, and the P-type and N-type enhancement MOS transistors are also connected. In the output circuit of the semiconductor integrated circuit in which signals are respectively input to the gates of the N-type depletion MOS transistor, the N-type depletion MOS transistor is connected between the output terminal and the P-type enhancement MOS transistor. Output circuit. 2. A P-type enhancement MOS transistor is connected between an output terminal and a power source, an N-type enhancement MOS transistor is connected between the output terminal and a ground, and the P-type and N-type enhancement MOS transistors are connected. In the output circuit of the semiconductor integrated circuit in which signals are respectively inputted to the gates of the P-type depletion MOS transistor, the P-type depletion MOS transistor is connected between the output terminal and the N-type enhancement MOS transistor. Output circuit. 3. A P-type enhancement MOS transistor is connected between the output terminal and the power supply, an N-type enhancement MOS transistor is connected between the output terminal and the ground, and the P-type and N-type enhancement MOS transistors are connected. In an output circuit of a semiconductor integrated circuit in which signals are respectively input to the gates of the N-type depletion MOS transistor, the N-type depletion MOS transistor is connected between the output terminal and the P-type enhancement MOS transistor, and the output terminal and the N-type depletion MOS transistor are connected. Enhancement M
P-type depletion MOS between OS transistor
An output circuit of a semiconductor integrated circuit characterized by connecting a transistor.