JPH06224213A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the reverse bias breakdown strength property by forming a first conductivity type of semiconductor region on the surface. CONSTITUTION:In this drive in process, impurities introduced into the vicinity of the surface of a p<->-type collector region 12 diffuse into the p<->-type collector region 12 so as to form the first n-type base region, and the ions of impurities being implanted into a specified depth diffuse in such a way as to widen the width of the n-type region, and form the second n<->-type base region 14. And, this diffusion connects the n<+>-type first base region 13 with the n<->-type second base region 14, and the region surrounded by the n<+>-type first base region 13 and the n<->-type second base region 14 is separated from the p<->-type collector region 12. Hereby, the breakdown strength between the emitter and the base and the breakdown strength between the collector and the emitter can be raised. A second conductivity type of semiconductor region is formed, which connects the impurities implanted into a specified depth with the impurities introduced into the surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as a transistor and a thyristor.

[0002]

2. Description of the Related Art Semiconductor devices are used in all technical fields, and among them, transistors and thyristors are the most basic ones and are used for various purposes. Semiconductor devices satisfying required characteristics such as amplification factor, switching characteristics, capacitance, and breakdown voltage are manufactured by various manufacturing methods according to their applications.

FIG. 7 is a sectional view showing the structure of a general vertical pnp transistor as an example of the semiconductor device. In the figure, p ⁻ is formed on the surface of the p ⁺ type collector region 1.
A type collector region 2 is formed, and an n ⁺ type first base region 3 is formed on the surface portion of the p ⁻ type collector region 2 at a predetermined distance from each other. An n ⁻ -type second base region 4 is formed between the n ⁺ -type first base regions 3 and 3, and a p ⁺ -type is selectively formed on the surface portion of the n ⁻ -type second base region 4. An emitter region 5 is formed.

[0004] p the region is formed ^- -type collector region 2 of the surface, a field oxide film 6 are uniformly formed, n ⁺ -type first base region 3 and the p ⁺ -type emitter region 5 The field oxide film 6 is selectively removed on the surface. Then, the field oxide film 6
In the portion where is removed, the base electrode 7 is formed on the surface of the n ⁺ type first base region 3, and the emitter electrode 8 is formed on the surface of the p ⁺ type emitter region 5.
A collector electrode 9 is uniformly formed on the lower surface of the p ⁺ type collector region 1.

Next, an example of the manufacturing process of the above transistor will be briefly described with reference to FIGS. 8 (a) to 8 (e). First, as shown in FIG. 8A, a p ⁻ -type collector region 2 is formed by epitaxial growth on the surface of a p ⁺ -type collector region 1 which is a semiconductor substrate, and the surface of the p ⁻ -type collector region 2 is made uniform. Initial oxidize.

Next, as an impurity introduction process, FIG.
As shown in (b), the n ⁺ -type first base region 3 and the n ⁻ -type second base region 4 are formed on the surface of the p ⁻ -type collector region 2.
In order to form, the n-type impurity such as arsenic is implanted at a predetermined surface impurity concentration.

Then, as shown in FIG.
Drive-in is performed in order to diffuse the type impurities into the p ⁻ type collector region 2 at a predetermined depth to form the n ⁺ type first base region 3 and the n ⁻ type second base region 4. The formation of the above-mentioned two regions 3 and 4 may be carried out separately in different steps depending on their depth. After that, the surface of the p ⁻ type collector region 2 in which the two regions 3 and 4 have been formed is uniformly oxidized.

Next, p^-Oxidation of the surface of the mold collector region 2
The film is formed into n as shown in FIG. ^-Mold second base area
No.4 surface selectively removes its oxide film
Diffused p-type impurities from the⁺Type emitter region 5
To form.

Finally, the field oxide film 6 is uniformly formed, and the field oxide film 6 is selectively removed above the n ⁺ -type first base region 3 and the p ⁺ -type emitter region 5, to obtain the structure shown in FIG. As shown in (e), a base electrode 7 and an emitter electrode 8 are formed respectively. Further, a collector electrode 9 is formed on the lower surface of the p ⁺ type collector region 1.

An example of the structure and manufacturing process of a general transistor has been described above, but the same applies to a thyristor. Since the operation of the above semiconductor device is widely known, its description is omitted.

[0011]

By the way, in the pnp-type transistor shown in FIG. 7, when the oxide film is formed after the impurities are driven in in the step shown in FIG. 8C, the oxide film is formed of silicon. It is formed so as to erode the surface of the layer, and the impurity concentration changes (redistribution) in the silicon surface layer. The cause of the change in the impurity concentration is mainly due to segregation between the silicon surface layer and the silicon oxide film, and the segregation coefficient k indicating the degree of segregation is

[0012]

[Equation 1]

Is given by Usually, a group III atom such as boron, which is used as a p-type impurity, has a strong affinity for oxygen in the silicon oxide film, and thus easily enters the silicon oxide film, and the segregation coefficient k is small.

On the other hand, the value of the segregation coefficient k of group V atoms such as phosphorus and arsenic used as n-type impurities is large. Therefore, when the silicon oxide film is formed, the n-type impurities are swept from the silicon oxide film side to the silicon surface layer. Therefore, the impurity concentration of the silicon surface layer near the interface with the silicon oxide film becomes higher than that before the formation of the silicon oxide film. The impurity concentration distribution at this time is shown in FIG.

FIG. 9 shows the pnp transistor of FIG.
It is a figure which shows the distribution of the impurity concentration when it cut | disconnects by a -X 'line. In the figure, the impurity concentration of the n ⁻ type second base region 4 sharply increases near the interface with the field oxide film 6. On the other hand, since the p ⁺ -type emitter region 5 is formed on the surface of the n ⁻ -type second base region 4, the pn junction between these two regions 4 and 5 near the surface is a p-type with a high impurity concentration. It is formed by a region and an n-type region.

Therefore, in the pn junction formed by the n ⁻ -type second base region 4 and the p ⁺ -type emitter region 5, the depletion layer is unlikely to spread near the surface when a reverse bias is applied. There arises a problem that the breakdown voltage, that is, the breakdown voltage between the emitter and the base becomes low.

In order to solve this problem, FIG.
In the impurity introduction step shown in FIG. 3, a method of implanting n-type impurities for forming the n ⁻ -type second base region 4 while setting the surface impurity concentration to be low may be considered. However,
Since it is necessary to form the n ⁻ -type second base region 4 to a predetermined depth when designing a transistor, in order to diffuse the n-type impurities introduced with a low surface impurity concentration to the above-described predetermined depth, as described above. You have to drive in for a long time.

As described above, when the drive-in time is extended to form the n ⁻ -type second base region 4 with a predetermined depth, the drive-in step heats the entire semiconductor substrate, so that the p ⁺ -type is formed. p-type impurities present in large amounts collector region 1 is p ^- diffused into type collector region 2, p ^- impurity concentration type collector region 2 is increased. As a result, the p ⁻ type collector region 2 and the n ⁺ type first base region 3 are formed.
Since the depletion layer is unlikely to spread in the pn junction between and during reverse bias, the collector-base breakdown voltage and the collector-emitter breakdown voltage are reduced.

Further, in order to secure the breakdown voltage between the emitter and the base, an n-type impurity for forming the n ⁻ -type second base region 4 is implanted with the surface impurity concentration set low, and
Unless the drive-in time is lengthened in order to prevent the collector-base breakdown voltage and the collector-emitter breakdown voltage from decreasing, the depth of the n ⁻ -type second base region 4 formed is shallower than a predetermined depth. turn into. Thus, when the n ⁻ -type second base region 4 is shallowly formed, p ⁺
Since the n-type semiconductor region having a low impurity concentration and a small width is provided between the type emitter region 5 and the p ⁻ type collector region 2, punch-through is likely to occur between them. Occurs.

As described above, conventionally, there is a trade-off relationship between the emitter-base breakdown voltage of a transistor, and the collector-base breakdown voltage and the collector-emitter breakdown voltage. However, there is a problem that is likely to occur.

Incidentally, this problem does not occur only in the transistor but also in the thyristor.
The present invention solves the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device with improved reverse bias withstand voltage characteristics.

[0022]

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a second conductivity type impurity is selectively implanted into a first conductivity type semiconductor substrate by ion implantation to a predetermined depth. Impurities of the second conductivity type are introduced into the surface of the semiconductor substrate facing the region surrounding the end of the position where the impurities are introduced by the ion implantation. Then, the impurity implanted into the predetermined depth and the impurity introduced into the surface are thermally diffused to form a second conductivity type semiconductor region to be connected. 3. The method for manufacturing a semiconductor device according to claim 2, further comprising forming a semiconductor region of the first conductivity type on a surface portion of a region surrounded by the semiconductor region, wherein the second conductivity type is formed on the surface of the semiconductor substrate of the first conductivity type. Semiconductor layer is formed, and impurities of the first conductivity type are selectively implanted into the semiconductor layer to a predetermined depth by ion implantation, and the semiconductor layer is opposed to a region surrounding the end portion where the impurities are introduced by the ion implantation. Impurities of the first conductivity type are introduced into the surface of the semiconductor substrate. Then, the impurities implanted into the predetermined depth and the impurities introduced into the surface are thermally diffused to form a first conductivity type semiconductor region to be connected. Further, a semiconductor region of the second conductivity type is formed on the surface of the region surrounded by the semiconductor region.

[0023]

A method of manufacturing a semiconductor device according to claim 1, wherein the second conductive type semiconductor region (second base, SIT in the second conductive type SIT) is located below the first conductive type semiconductor region (emitter, source in the SIT). An impurity for forming a channel is implanted by an ion implantation method. Therefore, in order to form the second base region with a desired impurity concentration only at a desired depth, the ion implantation acceleration voltage and its dose amount are controlled. It does not depend on the time for thermally diffusing the ion-implanted impurities.

As a result, since the second base region is not formed on the surface, the first conductivity type emitter region can be formed without being joined to the second conductivity type semiconductor region having a high impurity concentration. Therefore, the reverse bias breakdown voltage between the emitter and the base becomes high.

Since it is not necessary to increase the time for thermally diffusing the ion-implanted impurities, the impurities in the first-conductivity-type semiconductor substrate (collector, drain in SIT) have the second-conductivity-type impurities. There is no large diffusion to the vicinity of the semiconductor region (first base, gate in SIT), and the reverse bias breakdown voltage between the collector and the base becomes high.

Furthermore, since the impurity concentration of the second base region can be set to a desired concentration, the breakdown voltage against punch-through between the emitter region and the collector region can be increased.

If the method of implanting the impurities for forming the second base region by the ion implantation method in the above-mentioned manufacturing method is applied to the method of manufacturing a semiconductor device according to claim 1, the breakdown voltage is equivalent. To raise.

[0028]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 shows a vertical structure p according to an embodiment of the present invention.
It is sectional drawing of an np type transistor.

In the figure, a p ⁻ type collector region 12 is formed on the surface of the p ⁺ type collector region 11, and an n ⁺ type first base region 13 is formed on the surface portion of the p ⁻ type collector region 12. It is formed with a predetermined distance. Then, the n ⁺ -type on the surface portion between the first base region 13, 13, n ⁺ -type and the first base region 13 selectively p ⁺ -type emitter region 16 at a predetermined distance is formed, further A p ⁻ type emitter peripheral region 15 is formed so as to surround the p ⁺ type emitter region 16. Further, under the p ⁻ type emitter peripheral region 15, an n ⁻ type second base region for connecting the n ⁺ type first base regions 13 and 13 to each other at a predetermined depth from the surface of the p ⁻ type collector region 12. A base region 14 is formed.

A field oxide film 17 is uniformly formed on the surface of the p ⁻ type collector region 12 in which the above region is formed, and the field oxide film 17 is formed in the n ⁺ type first base region 13 and the p ⁺ type emitter region 16. On the surface, the field oxide film 17 is selectively removed. Then, in the portion where the field oxide film 17 is removed, the base electrode 18 is formed on the surface of the n ⁺ type first base region 13, and the emitter electrode 19 is formed on the surface of the p ⁺ type emitter region 16. ing. In addition, the p ⁺ type collector region 11
A collector electrode 20 is uniformly formed on the lower surface of the.

Next, an example of a manufacturing process of the transistor shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 2 (e). First, as shown in FIG. 2A, ap ⁻ type collector region 12 is formed by epitaxial growth on the surface of the p ⁺ type collector region 11 which is a silicon semiconductor substrate. Then, once an oxide film is uniformly formed on the surface of the p ⁻ type collector region 12, the oxide film is selectively removed. Here, n-type impurities, such as arsenic ions, are accelerated by a predetermined acceleration voltage and implanted into the p ⁻ -type collector region 12 at a desired depth using the oxide film as a mask. After this,
The oxide film is removed.

Next, an oxide film is again uniformly formed on the surface of p ⁻ type collector region 12, and the oxide film is removed at a position facing the region surrounding the end of the region where arsenic ions are implanted. Then, as shown in FIG. 2B, arsenic, for example, is introduced (deposited) in the vicinity of the surface of p ⁻ type collector region 12 using the oxide film as a mask. After that, the oxide film is removed. The p ⁻ type collector region 12
The order of the step of introducing impurities into the vicinity of the surface and the step of implanting ions in FIG. 2A may be reversed.

In the next step, as shown in FIG.
The impurities implanted as described above are thermally diffused (drive-in). In the drive-in process, p ^- type impurity introduced into the vicinity of the surface of the collector region 12 is p ^- type collector region diffuse to 12 into the interior of the n ⁺ -type first base region 13
Then, the impurities ion-implanted to a predetermined depth are diffused to widen the width of the n-type region to form the n ⁻ -type second base region 14. And this diffusion causes n ⁺
Type first base region 13 and n ^- to connect the mold the second base region 14, n ⁺ -type first base region 13 and the n ^- region surrounded by the mold the second base region 14 is p ^- isolated from type collector region 12 To be done. This separated p ⁻ type region is referred to as a p ⁻ type emitter peripheral region 15. Further, an oxide film is formed on the surface of the p ⁻ type collector region 12 in which the above region is formed.

Next, as shown in FIG. 2D, the oxide film is selectively removed on the surface of the p ⁻ -type emitter peripheral region 15, and p-type impurities are removed from the removed oxide film.
For example, boron is diffused to form the p ⁺ -type emitter region 16.

Finally, the field oxide film 17 is uniformly formed.
Made, n⁺Mold first base region 13 and p⁺Type emitter
Selectively the field oxide film 17 above the region 16
Remove. Then, as shown in FIG.
N through the portion where the field oxide film 17 is removed.⁺Type 1
A base electrode 18 is formed on the surface of the base region 13, and p ⁺
Forming an emitter electrode 19 on the surface of the mold emitter region 16
It Also, p⁺A collector is provided on the lower surface of the mold collector region 11.
The electrode 20 is formed.

Next, as shown in FIG.
FIG. 3 shows the impurity concentration distribution when the pnp-type transistor of FIG. In the figure, a p ⁻ -type emitter peripheral region 15 is formed in a region in contact with the field oxide film 17, and n is provided on the right side (downward in FIG. 1) thereof.
^The -type second base region 14 is formed. Thus, n ^- implantation of impurities for forming the mold the second base region 14, p ^- not performed by thermal diffusion from the surface of type collector region 12, p by ion implantation ^- type collector region 12 Since it is distributed only at a predetermined depth from the surface, n is formed around the p ⁺ -type emitter region 16.
There is no semiconductor region of the type.

Therefore, the breakdown voltage between the emitter and the base of the pnp type transistor shown in FIG. 1 is between the p ⁻ type emitter peripheral region 15 and the n ⁺ type first base region 13, or p
^- type emitter peripheral region 15 and the n ^- -type second base region 14
There is a problem with the expansion of the depletion layer in the pn junction between the and p ^- type junctions. Further, in the conventional manufacturing method, the oxidation treatment is performed after the thermal diffusion from the vicinity of the surface of the p ⁻ type collector region 12 in order to form the n ⁻ type second base region 14, so that the silicon surface layer and the silicon are formed. The segregation with the oxide film causes a problem of a change in the impurity concentration of the silicon surface layer of the n-type semiconductor region, but in the present embodiment, p
Since there is no n-type semiconductor region around the ⁺ type emitter region 16, it is not necessary to consider the above problem.

Further, in this embodiment, n^-Type 2
P forming the base region 14^-Table of mold collector region 12
Acceleration of arsenic ions by implanting the depth from the surface
Can be determined accurately by controlling the voltage
It Therefore, the above n^-P of the mold second base region 14^-
The depth from the surface of the mold collector region 12 and n^-Type 2
In order to drive in the base area 14 to a predetermined depth
It becomes irrelevant to the time of
⁺Impurities in the type collector region 11 are p^-Type collector area
It is possible to do it in a time that does not flow into 12
It Thus, p ⁺Mold collector region 11 to p^-Type
It is possible to suppress the inflow of impurities into the rector region 12 to a small amount.
When possible, p^-The impurity concentration of the type collector region 12 is
It remains low, so p^-Type collector region 12 and
n⁺Withstand voltage between the mold first base region 13 becomes high,
Collector-base breakdown voltage and collector-emitter breakdown voltage
The pressure increases. In other words, a predetermined value for the above breakdown voltage
When you want to secure p^-Make the width of the mold collector region 12 thin
ON voltage of the transistor.
Becomes smaller.

Further, in this embodiment, by controlling the dose amount of arsenic ions for performing ion implantation,
The impurity concentration of the n ⁻ type second base region 14 can be determined. Therefore, it is possible to control the impurity concentration of the n ⁻ -type second base region 14 and increase the breakdown voltage against punch-through between the emitter and the collector. Since the impurity concentration of the n ⁻ -type second base region 14 is controlled independently without affecting the impurity concentration of the other regions by ion implantation, this allows the breakdown voltage between the emitter and the base and the collector.・ The breakdown voltage between emitters does not decrease.

In the above embodiment, the p ⁺ type emitter region 16 and the n ⁻ type second base region 14 are not directly connected to each other, and the p ⁻ type emitter peripheral region 15 is formed between them, but it is necessary. When the breakdown voltage between the emitter and the base may be relatively small, the two regions 16 and 14 may be formed in contact with each other.

Next, another embodiment of the present invention will be described. FIG. 4 is a diagram showing a sectional structure when the present invention is applied to an npn-type transistor. The npn-type transistor in the figure is formed by inverting the conductivity type of each region of the pnp-type transistor shown in FIG. 1, and its manufacturing process is shown in FIGS. 2 (a) to 2 (e). It is similar to the process.

In FIG. 1 and FIG. 4, the bipolar type transistor is taken up for explanation, but the present invention is also applicable to a static induction transistor (SIT). In the SIT, impurity implantation for forming a channel region located under the source region is performed by ion implantation to a predetermined depth.

FIG. 5 is a diagram showing a sectional structure when the present invention is applied to a thyristor. In the figure, p to the upper surface of the n ⁺ -type anode region 31 is a semiconductor substrate ^- -type base region 32 is formed, the p ^- type base region 32
The n ⁺ -type first gate regions 33 are formed on the surface of the n-type first gate regions 33 at predetermined intervals. Then, the n ⁺ -type on the surface portion between the first gate region 33, 33, n ⁺ -type and the first gate region 33 and selectively p ⁺ -type cathode region 36 at a predetermined distance is formed, further A p ⁻ type cathode peripheral region 35 is formed so as to surround the p ⁺ type cathode region 36. In addition, below the p ⁻ -type cathode peripheral region 35, the n ⁻ -type second gate regions 33, 33 connecting the n ⁺ -type first gate regions 33, 33 to each other at a predetermined depth from the surface of the p ⁻ -type base region 32 are connected. The gate region 34 is formed.

A field oxide film 37 is uniformly formed on the surface of the p ⁻ type base region 32 where the above-mentioned region is formed, and the field oxide film 37 is formed in the n ⁺ type first gate region 33 and the p ⁺ type cathode region 36. On the surface, the field oxide film 37 is selectively removed. In the portion where the field oxide film 37 is removed, the gate electrode 38 is formed on the surface of the n ⁺ type first gate region 33, and the cathode electrode 3 is formed on the surface of the p ⁺ type cathode region 36.
9 is formed. Further, the anode electrode 40 is uniformly formed on the lower surface of the n ⁺ type anode region 31.

FIG. 6 is a diagram showing a sectional structure of a thyristor formed by inverting the conductivity type of each region of the thyristor shown in FIG. The manufacturing process of the thyristor in FIGS. 5 and 6 is basically the same as the process shown in FIGS. 2 (a) to 2 (e). However, in the manufacture of the transistor, the semiconductor region of the same conductivity type as that of the semiconductor substrate is formed on the semiconductor substrate in FIG. 2A, but in the manufacture of the thyristor, the semiconductor region opposite to the semiconductor substrate is formed. A conductive type semiconductor region is formed.

[0046]

As described above, according to the present invention,
Since the impurity implantation for forming the base region located under the emitter region is performed by ion implantation, the depth for forming the base region and the impurity concentration thereof can be set without affecting other regions. Therefore, both the emitter-base breakdown voltage and the collector-emitter breakdown voltage can be increased. Also, the same effect can be obtained in the static induction transistor and the thyristor.

[Brief description of drawings]

FIG. 1 is a sectional view of a pnp-type transistor according to an embodiment of the present invention.

FIG. 2 is a schematic manufacturing process diagram of the pnp-type transistor shown in FIG.

3 is a diagram showing an impurity concentration distribution when the pnp transistor shown in FIG. 1 is cut along a line YY '.

4 is a cross-sectional view of an npn-type transistor in which the conductivity type of each region of the pnp-type transistor shown in FIG. 1 is inverted.

FIG. 5 is a sectional view of a thyristor to which the present invention is applied.

6 is a cross-sectional view of the thyristor in which the conductivity type of each region of the thyristor shown in FIG. 5 is reversed.

FIG. 7 is a cross-sectional view of a pnp-type transistor manufactured by a conventional manufacturing method.

FIG. 8 is a schematic manufacturing process diagram of the conventional pnp-type transistor shown in FIG. 7.

9 is a diagram showing an impurity concentration distribution when the pnp-type transistor shown in FIG. 7 is cut along line XX ′.

[Explanation of symbols]

11 p ⁺ type collector region 12 p ⁻ type collector region 13 n ⁺ type first base region 14 n ⁻ type second base region 15 p ⁻ type emitter peripheral region 16 p ⁺ type emitter region 17 field oxide film 18 base electrode 19 emitter Electrode 20 Collector electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 29/74 MQ 29/804 7376-4M H01L 29/80 V

Claims (2)

[Claims] 1. An impurity of the second conductivity type is selectively implanted into a first conductivity type semiconductor substrate by ion implantation to a predetermined depth, and a region surrounding an end portion of the position where the impurity is introduced by the ion implantation is opposed. A second conductivity type semiconductor region is formed by introducing impurities of the second conductivity type into the surface of the semiconductor substrate, thermally diffusing the impurities, and connecting the impurities implanted into the predetermined depth and the impurities introduced into the surface. A method of manufacturing a semiconductor device, which comprises forming a semiconductor region of a first conductivity type on a surface portion of a region surrounded by the semiconductor region. 2. A semiconductor layer of a second conductivity type is formed on the surface of a semiconductor substrate of a first conductivity type, and an impurity of the first conductivity type is selectively implanted into the semiconductor layer to a predetermined depth by ion implantation. Impurities of the first conductivity type are introduced into the surface of the semiconductor layer facing the region surrounding the end of the position where the impurities are introduced by ion implantation, and the impurities are thermally diffused and implanted into the predetermined depth and the surface. A semiconductor region of a first conductivity type that is connected to the impurities introduced into the semiconductor region, and a semiconductor region of a second conductivity type is formed on the surface of the region surrounded by the semiconductor region. Production method.