JPH06216207A - Inspection of wafer - Google Patents

Abstract

PURPOSE:To provide a technique for detecting a defect generated in a wafer and for designating a layer wherein the defect is generated readily. CONSTITUTION:Dummy patterns 4, 5, 6 for defect detection are provided in a scribe line, a defect 7 generated in a dummy pattern is detected by inspecting the dummy pattern visually or electrically and a defect of a semiconductor device is detected by inspecting an area near the defect 7. A dummy pattern is provided for each of a plurality of layers such as a wiring layer and influence by defects is compared between dummy patterns. Since other patterns are not formed in a scribe line, visual observation is not obstructed. Furthermore, since a dummy pattern itself is formed flat to a simple shape, the inspection is easy. A layer wherein a defect is generated can be designated by comparing influence by a defect of a dummy pattern provided to a plurality of layers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a wafer on which a semiconductor device is patterned, and is particularly effective when applied to an inspection for finding defects in a wafer by a visual inspection with a microscope or an electrical inspection. Technology.

[0002]

2. Description of the Related Art A semiconductor device is formed by patterning a plurality of semiconductor devices on a single wafer by a wafer process, and cutting the wafer into chips of each semiconductor device in an assembling process.
Each chip is packaged into a product. The wafer on which the pattern has been formed is subjected to a selection inspection of semiconductor devices in a wafer state by using an LSI tester or the like before being sent to the next assembly process. This inspection is performed by a comparison inspection method for finding defects by comparing patterns of each semiconductor device or an electric inspection method for performing a DC characteristic test, a logic function test, or the like. Although these inspections are highly accurate and can detect even minute defects, they are performed for each semiconductor device and require a considerable amount of time.

Among the defects generated in the wafer, a scratch formed by the contact between the wafers or the contact between the wafer and the wafer carrier becomes a comparatively large defect and damages a plurality of adjacent semiconductor devices. Since many semiconductor devices are defective when such a defect occurs, it is possible to reduce the time required for the inspection by excluding these defective semiconductor devices from the highly accurate inspection. Since such a large defect is visually recognizable, such a defect is found in advance by a visual inspection using a metallurgical microscope, and a defective semiconductor device caused by the large defect is excluded from high-precision inspection. Therefore, the method of improving the inspection efficiency is adopted.

[0004]

The present inventor has found the following problems as a result of examining the above-mentioned prior art.

In response to the increase in the number of elements due to high integration,
L having a multi-layered wiring layer for connecting the respective elements in the semiconductor device
SI (large scale integrated)
In the circuit), defects in the lower layer are covered by the pattern in the upper layer, which makes it difficult to detect defects in the lower layer by visual inspection. In particular, the power supply wiring, which has the widest wiring width because the maximum current flows, is often placed on the top layer in consideration of heat dissipation.
In such a case, the lower layer portion is almost obstructed by the power supply wiring and cannot be seen, and it becomes extremely difficult to find a defect.

When a defect is found by the visual inspection, in order to take measures to prevent the defect from occurring, it is specified in which layer the defect is generated, that is, in which process. There is a need. In order to identify such a defective portion, it is necessary to peel off each layer of the LSI from the surface by etching or planar polishing and perform an inspection, and repeat this until the layer in which the defect occurs is reached. There is a problem that it takes time.

An object of the present invention is to provide a technique capable of easily finding a defect in a semiconductor device in a wafer state and easily identifying a layer in which the defect has occurred.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

A dummy pattern for detecting a defect is provided on a scribe line between the semiconductor device patterns, and the dummy pattern is visually inspected or the electrical continuity is inspected to find a defect generated in the dummy pattern. Determining the defect of the semiconductor device adjacent to the defect.
A dummy pattern is provided for each of a plurality of layers such as a wiring layer, and the influence of the defect is compared between the dummy patterns to identify the layer in which the defect has occurred.

[0011]

According to the above-mentioned means, the dummy pattern provided on the scribe line of the wafer on which the semiconductor device is formed is inspected, and if there is a dummy pattern in which a defect occurs, the vicinity of the defect in the dummy pattern is inspected. By doing so, the defect of the semiconductor device can be easily found. No other pattern is formed on the scribe line, so that the visual inspection is not hindered. In addition, the dummy pattern itself is formed in a flat shape with a simple shape, so that the inspection is easy.

Further, by comparing the effects of the defects of the dummy patterns provided in the plurality of layers, it is possible to easily identify the layer in which the defect has occurred.

The structure of the present invention will be described below together with embodiments.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[0015]

(Embodiment 1) FIG. 1 is a plan view showing a wafer after pattern formation.

1, 2 is a semiconductor device having a pattern formed thereon, and 3 is a scribe line. The scribe line 3 is a portion that serves as a cutting margin when the semiconductor devices 2, ..., 2 are diced into individual chips in the next assembly process, and usually has a width of about 400 μm to 500 μm. , 2 between the two.

FIG. 2 is an enlarged plan view showing a part of the wafer 1 provided with the dummy patterns 4, 5 and 6 used in the first embodiment of the present invention. In this embodiment, electrical continuity of the dummy pattern is inspected by electrically performing an open check or a short check.

The dummy patterns 4, 5 and 6 have measuring pads 4a and 5 for facilitating electrical connection to the ends.
a and 6a are formed in a long and narrow rectangular shape, and are provided on the scribe line 3 between the semiconductor devices 2 ,. In this embodiment, the semiconductor device 2 has three wiring layers (not shown), and the dummy patterns 4, 5 and 6 are also provided at different positions for each wiring layer. Reference numeral 4 is a dummy pattern formed at the same time as the first wiring layer, 5 is a dummy pattern formed at the same time as the second wiring layer, and 6 is a dummy pattern formed at the same time as the third wiring layer. These dummy patterns 4, 5 and 6 are formed at the same time when each wiring layer is formed by patterning the photomask used for forming each wiring layer. Finally, the measurement pads 4a, 5
An opening for connecting a and 6a with the test apparatus is opened in the scribe line 3.

The inspection method of this embodiment will be described below.

Reference numeral 7 is a scratch on the wafer 1 after the formation of the second wiring layer and before the formation of the third wiring layer. When the dummy patterns 4, 5 and 6 are subjected to the conduction test, the dummy pattern 5 does not conduct due to the influence of the scratch 7, but the dummy pattern 6 does not undergo the influence of the scratch 7 and therefore conducts. From this, wound 7
Can be judged to have come after the formation of the second wiring layer and before the formation of the third wiring layer. Regarding the dummy pattern 4, it can be seen that the scratch has not reached the wiring layer of the first layer if there is conduction, and that the scratch 7 has reached the wiring layer of the first layer if there is no conduction. Therefore, it is possible to estimate the depth of the scratch 7.

In the above-mentioned embodiment, the test is conducted after all the wiring layers are formed, but the test may be conducted every time each wiring layer is formed. In this case, it is not necessary to provide the opening in the wiring interlayer film, and each dummy pattern can be embedded in the next step. Even if a test is performed between the steps, it is a simple test that only checks the conduction of the dummy patterns 4, 5, and 6 and can be performed in a short time, so that there is little time effect on the entire step. In this test, if the number of defective semiconductor devices exceeds the number determined in consideration of profitability, the manufacturing process can be configured so that the subsequent processes are not performed, and unnecessary processes can be omitted. Is.

Further, in this embodiment, since the dummy patterns are provided at different positions, it is possible to perform a visual appearance inspection which will be described later in detail.

(Embodiment 2) FIG. 3 is an enlarged plan view showing a part of the wafer 1 provided with the dummy patterns 14, 15 and 16 used in the second embodiment of the present invention.

In this embodiment, the dummy patterns 14 and 1
5 and 16 are measurement pads 14a and 15 provided at the ends.
In order to shift the positions of a and 16a, the end portions are offset and formed, and provided on the scribe line 3 between the semiconductor devices 2 ,. In the present embodiment, the semiconductor device 2 has three wiring layers, and dummy patterns 14, 15 and 16 are also provided so as to be aligned with each wiring layer, and the measurement pads 14 are provided.
The positions a, 15a, 16a are provided at different positions. 14
Is a dummy pattern formed at the same time as the first wiring layer, 1
5 is a dummy pattern formed at the same time as the second wiring layer,
Reference numeral 16 is a dummy pattern formed at the same time as the third wiring layer. These dummy patterns 14, 15 and 16 are formed at the same time as the formation of each wiring layer by patterning the photomask used for the formation of each wiring layer, and finally, the measurement pads 14a, 15a and 16a are formed. Open the scribe line 3 to connect to the test equipment.
Leave it open.

The inspection method of this embodiment will be described below.

In the present embodiment, if a defect occurs in the dummy pattern 14, for example, the conduction of the dummy pattern 14 is cut off by the defect. Therefore, the dummy pattern 14 is tested by conducting the conduction. It is possible to know the defect, and it is possible to identify the layer in which the defect has occurred from the conductive state of the other dummy patterns 15 and 16 adjacent to the dummy pattern 14 in which the defect has occurred.

Further, it is difficult to find a defect in the wiring interlayer film (insulating film between wiring layers) by visual observation of the conventional appearance because the wiring interlayer film is transparent. Defects in the wiring interlayer film process not only cause a short circuit between the wiring layers, but also may cause a fatal defect due to a wear failure during use of the semiconductor device depending on the degree of occurrence of scratches. According to this embodiment, it is possible to find such a defect.

In this embodiment, the dummy pattern 1 is formed on the upper and lower sides.
4, 15 and 16 are provided so as to face each other with the wiring interlayer film interposed therebetween. Therefore, for example, when a defect occurs in the wiring interlayer film between the dummy patterns 14 and 15, the conductive material forming the dummy pattern 15 is deposited in the space above the dummy pattern 14 caused by the defect, and the dummy patterns 14 and 15 above and below are formed. 1
5 will be conducted. Therefore, by examining the conduction between the upper and lower dummy patterns 14 and 15, a defect in the wiring interlayer film can be easily found.

Further, in the present embodiment, if the test is performed for each treatment of each layer, the measurement pads 14a, 15a,
It may be formed by stacking the positions of 16a without shifting.

Further, in the present embodiment, the dummy patterns 14, 15 and 16 are formed to have the same width. However, if the dummy patterns 14, 15 and 16 are formed to have a narrower width in order from the lower layer, Even if the dummy patterns 14, 15 and 16 are provided in an overlapping manner, the dummy pattern 1 which is visually located below
A part of 4, 15 can be observed even after the dummy pattern 16 is formed. As a result, it is possible to perform a visual inspection in addition to the inspection of the wiring interlayer film by the above-mentioned conduction.

(Embodiment 3) FIG. 4 is an enlarged plan view showing a part of the wafer 1 provided with the dummy patterns 24, 25 and 26 used in the third embodiment of the present invention. In this embodiment, the semiconductor device 2 has three wiring layers, dummy patterns 24, 25, and 26 are also provided for each wiring layer, and are formed in a grid shape along the scribe lines 3. These dummy patterns 24, 25 and 26 are formed simultaneously with the formation of the wiring layers by patterning the photomask used for forming the wiring layers. 24 is a dummy pattern formed at the same time as the first wiring layer, and 25 is a second dummy pattern.
A dummy pattern formed at the same time as the wiring layer of the third layer, and a dummy pattern 26 formed at the same time as the wiring layer of the third layer.

The inspection method of this embodiment will be described below.

In this embodiment, a visual inspection using a metallurgical microscope is carried out instead of the continuity inspection. 27 is a wafer 1 after the formation of the first wiring layer and before the formation of the second wiring layer.
It is a scratch on the. Dummy pattern 2 by visual inspection
A discontinuous portion due to the influence of the scratch 27 is observed in No. 4, and the defect generated in the wafer can be found by observing the vicinity of this discontinuous portion. Further, such a discontinuous portion does not occur in the dummy patterns 25 and 26 adjacent to the dummy pattern 24. From this, it can be judged that the scratch 27 was formed after the formation of the first wiring layer and before the formation of the second wiring layer.

In the visual inspection, only the dummy patterns 24, 25 and 26 are formed on the scribe line 3 at different positions, and the visual inspection is not obstructed by other patterns. Further, the scribe line 3 is formed by a regular layer of material deposited on the entire surface, and in addition to being flat over the entire surface and having no change in color, the dummy patterns 24, 25, 26 themselves are combined with simple linear shapes. Since the dummy patterns 24, 25, and 26 change in continuity on the scribe line 3, the change appears clearly and can be easily found. it can.

For example, even when foreign matter such as dust is present, changes occur such that the dummy patterns 24, 25, and 26 are partially raised, and the changes can be easily identified.

Further, it is difficult to find a defect generated in the wiring interlayer film by visual observation of the conventional appearance because the wiring interlayer film is transparent. However, in this embodiment, for example, when a defect occurs in the wiring interlayer film between the dummy patterns 24 and 25, the dummy pattern 2 is formed in the space caused by the defect.
The conductive material forming 5 is deposited, and the dummy pattern 25 is formed in a depressed shape. Therefore, a defect in the wiring interlayer film can be easily found from the change in the shape of the dummy pattern 25.

Further, the visual inspection can be automated by means such as a comparison inspection method. When the dummy patterns 24, 25, 26 are inspected by the comparison inspection method, the dummy patterns 24, 25, 26 are simply and regularly arranged and no other pattern is formed on the scribe line 3. Therefore, the inspection is completed in an extremely short time.

The inventions made by the present inventors are as follows.
Although the specific description has been given based on the above-described embodiments, the present invention is not limited to the above-described embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

For example, although the dummy pattern is formed in the wiring layer in the above-mentioned embodiment, it is also possible to form other conductor layers and semiconductor layers as the dummy pattern, and the importance of each layer or the possibility of causing defects, etc. Considering the condition of
A dummy pattern may be selectively formed.

[0040]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) Since the dummy pattern for defect detection is provided on the scribe line where no other pattern is formed, the defect can be easily detected by visual inspection or electrical inspection. Automation is also possible.

(2) Even when the wiring is multi-layered, only the dummy patterns of each layer are formed in the scribe line at different positions, so that even a defect occurring in the lower layer can be easily found by visual inspection. is there.

(3) When the wiring layers and the like are multi-layered, it is possible to easily identify the layer in which the defect has occurred by comparing the effects of the defects of the dummy patterns provided in the respective layers.

(4) In the visual inspection, the scribe line is flat and does not change in color, and the dummy pattern is a combination of simple linear shapes and is formed flat. If there is a change in the continuity of the dummy pattern in, the change clearly appears and can be easily found.
Even when a foreign substance such as dust is present, a change occurs such that the dummy pattern is partially raised, and the change can be easily identified.

(5) It is difficult to find a defect generated in the wiring interlayer film by visual inspection because the wiring interlayer film is transparent. However, according to the present invention, it is possible to locate the defect on the wiring interlayer film having the defect. It can be easily found by investigating a change in the shape of the dummy pattern or a short circuit between the upper and lower dummy patterns.

(6) Since the inspection can be performed even in the middle of the wafer processing step, it becomes possible to stop the subsequent steps for a wafer in which a large number of semiconductor devices are found due to defects, and it is possible to omit a wasteful step. it can.

[Brief description of drawings]

FIG. 1 is a plan view showing a wafer on which a semiconductor device is patterned.

FIG. 2 is a partially enlarged plan view showing a wafer used in the first embodiment,

FIG. 3 is a partially enlarged plan view showing a wafer used in a second embodiment,

FIG. 4 is a partially enlarged plan view showing a wafer used in a third embodiment.

[Explanation of symbols]

1 ... Wafer, 2 ... Semiconductor device, 3 ... Scribe line, 4, 5, 6, 14, 15, 16, 24, 25, 26
... Dummy patterns 4a, 5a, 6a, 14a, 15
a, 16a ... Pads for measurement, 7, 27 ... Scratches.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Morishita 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hiritsu Cho-LS Engineering Co., Ltd.

Claims (2)

[Claims] 1. A method for inspecting a wafer in which a plurality of semiconductor devices are formed, wherein a defect generated in the dummy pattern is found by inspecting a dummy pattern provided on a scribe line of the wafer, and a defect caused in the dummy pattern. A wafer inspection method characterized by finding defects in a wafer from a wafer. 2. A method of inspecting a wafer in which a plurality of semiconductor device patterns each having a plurality of layers are formed, wherein a defect generated in the dummy pattern is inspected by inspecting a dummy pattern provided by changing layers to a scribe line of the wafer. A method of inspecting a wafer, characterized in that a defect of a wafer is found from defects found in a dummy pattern, and a layer in which a defective dummy pattern is formed is specified to identify a layer in which a defect is generated. .