JPH0619958B2 - Electron beam writer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charged beam generator, and more particularly to an electron beam drawing apparatus that emits an electron beam from a thin substrate to directly draw an actual element pattern on a wafer or the like. Regarding

[Prior Art] As a source of electrons in a charged beam apparatus or the like, one utilizing thermionic emission from a hot cathode has been conventionally used.
Electron emission using such a hot cathode is said to have a large energy loss due to heating, the need to form a heating means, the time required for preheating to a considerable extent, and the system being easily destabilized by heat. There was a problem in terms.

Therefore, research on an electron-emitting device that does not rely on heating has been advanced, and several types of devices have been proposed.

For example, a type in which a reverse bias voltage is applied to a PN junction to cause an electron avalanche breakdown phenomenon and electrons are emitted to the outside of the element (see JP-A-54-111272, US Pat. No. 4,259,678) or metal-insulation. A type (MIM type) which has a structure of a body layer and a metal layer and emits electrons passing through the insulating layer by tunnel effect from the metal layer to the outside of the element by applying a voltage between the two metals. Voltage to a high resistance thin film, a surface conduction type device that applies a voltage to the high resistance thin film in a direction perpendicular to the film thickness direction to emit electrons from the thin film surface to the outside of the element, A field effect type (FE type) type in which a high-density electric field is locally generated by applying an electric field and electrons are emitted from the metal to the outside of the element, and other types have been proposed.

As an application example of these electron-emitting devices, a plurality of electron-emitting sources are arranged to form an electron-emitting device, and ON-OFF of the electron emission from each electron-emitting source is controlled to perform electron emission in a desired pattern. Then, it is conceivable to collide with a medium, for example, the surface of an object to be processed to perform surface processing or surface alteration by electron beam exposure. As such an electron emitting device, a device in which a large number of electron emitting devices are densely arranged can be considered. According to such an electron-emitting device, the workpiece can be exposed by electron beam exposure in a two-dimensional pattern by simply arranging the workpiece so as to face each other and then controlling ON-OFF of each electron-emitting device. .

[Problems to be Solved by the Invention] However, at present, it is difficult to mass-produce an electron-emitting device in which a large number of such electron-emitting sources are densely arranged with high yield. There are also problems such as heat generation and interference between adjacent electron beams.

Further, in the above-mentioned conventional example, the accuracy cannot be improved because the device becomes large or complicated and the individual parts are separated.

On the other hand, for example, in electron beam drawing of a semiconductor wafer, an electron beam apparatus or the like that can perform beam irradiation or the like more efficiently and accurately is required in order to cope with high integration of circuits.

Based on such a viewpoint, an object of the present invention is to improve the electron beam generation efficiency in an electron beam generation source in an electron beam drawing apparatus, and to easily change the line width of drawing by an electron beam. It is to ensure processing efficiency.

[Means and Actions for Solving Problems] In order to achieve the above-mentioned object, an electron beam drawing apparatus of the present invention includes a means for storing pattern data to be drawn on a medium and a plurality of means arranged close to each other. At least one unit electron beam source having an electron beam source as one unit, means for deflecting an electron beam emitted by the unit electron beam source, and based on the stored pattern data are included therein. Drive control means for selectively driving the plurality of electron beam generation sources in each unit electron beam generation source according to the data of the line width to be generated and controlling the deflection means to perform drawing on the medium. Is characterized by.

According to this, since a plurality of electron beam generators are combined as one unit, a large amount of electrons can be emitted even at low voltage drive, the electron beam generation efficiency can be improved, and a plurality of electron beam generators can be generated. It is possible to easily change the drawing line width of the beam by selectively driving.

[Example] The present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing a configuration when a charged particle beam system according to an embodiment of the present invention is applied to exposure of a semiconductor wafer. In the figure, WF is a wafer made of a semiconductor such as silicon or gallium, to which a resist sensitive (exposed) to an electron beam is applied. CP1 to CPn indicate a plurality of exposure areas, which are parts that are cut off after writing is completed to form one chip. M1 to M8 are marks for pre-alignment or fine alignment provided on the wafer WF. MB is a head for generating an electron beam (hereinafter referred to as EB), which is mounted on the stage MS and adsorbed. The alignment marks M1 to M8 are drawn by the EB of this head in the first drawing process. The stage MS can be finely moved in the x, y and θ (rotation) directions by the piezo pressure current collecting elements Px, Py and Pθ. Each element Px, P
y and Pθ are used for alignment with the wafer WF. The head MB is provided with EB generation sources ES0 to ES15.

The EB sources ES0 and ES15 are dedicated to alignment, and the EB sources ES1 to ES14 are dedicated to exposure or shared for alignment. Here, the exposure EB generation sources ES1 to ES14 are
Two pieces are allocated for writing each chip row in the X direction on the wafer WF. That is, for example, a chip (exposure area)
The upper half area CP1U of CP1 is drawn by the EB generation source ES1, and the lower half area CP1L is drawn by the EB generation source ES2. Similarly, in the exposure regions CP2 to CP5, the upper half of the exposure regions CP2 to CP5 is the EB generation source ES1 and the lower half is the EB generation source ES2.
Drawn by. EB deflection electrodes X1, X2, Y1, Y are respectively provided in the EB generation sources ES0 to ES15 in the X and Y directions.
2 is provided. Further, sensors S1 to S9 and the like are provided. These sensors may be light sensitive or electronically sensitive.

KB is a keyboard, DP is a display, and CAD is a controller. A circuit pattern of one chip is designed by these, and when the information is sent to the one-chip pattern generator PG, the pattern generator PG divides the drawing information of one chip into the upper half and the lower half of the drawing information, and halves each. It is sent to the chip memories MU and ML. Each memory M
U and ML use this drawing information for the EB that is in charge of the upper half of the chip.
Source ES1, ES3, ES5 to ES13 and E corresponding to the lower half
B sources ES2, ES4, ES6 to ES14 are simultaneously sent. However, two memories MU and two MLs are provided, respectively, and by alternately using them, the loss of the data transfer time from the pattern generator PG is substantially eliminated.

Based on the drawing information from the memories MU and ML, each EB source deflects in the X direction by its X direction deflection electrodes X1 and X2, thereby performing the drawing in the X direction within the range that can be covered by the deflection, and the wafer WF and the head. By continuously moving MB and Y in the Y direction, all pixels in the Y direction in the 1/2 area are drawn. However, since the movement in the Y direction is continuous, a deviation in the Y direction occurs when drawing is performed in the X direction for each pixel in the Y direction.
This is corrected using Y2. Then, this drawing is further repeated while intermittently moving the wafer WF and the head MB relatively in the X direction to draw one chip row in the Y direction.

In this way, each EB source is substantially simultaneous with one chip row in the Y direction of the wafer WF, for example, CP6, CP13, CP2.
High speed drawing is possible because 0, CP27, CP34 are drawn.

The deflection electrodes X1, X2, Y1 and Y2 are commonly used for initial alignment of the axis of the EB and alignment with the wafer or chip. For example, the alignment mark M of the chip CP1
Sensors S4 and S5 read the positions of M4 and M5, and X and Y of EB sources ES1 and ES are read based on the read information.
EB by correction driving of the deflection electrodes X1, X2, Y1, Y2
Correct the irradiation position of. This chip alignment mark is, for example, like the mark M6, the chips CP6 and CP.
It may be shared by 13 people.

On the other hand, as the pre-alignment mark, the mark M1,
M2, M7, M8 and the like are provided. Then, for example, the position of the mark M1 is read by the sensor S1, and the position of the mark M2 is read by a sensor (not shown). Based on this, the initial alignment of the head MB is performed by the piezoelectric elements Px, Py, P.
Perform by θ. Then, in that state, the displacement amount is measured using the chip alignment mark M3, the sensor S3, etc., and the deflection electrodes X1, X2, Y are based on the measurement result.
Drawing is performed with the position corrected by 1, Y2. It is also possible to temporarily stop during drawing and perform realignment using the marks M7 and M8.

Although various mark detection methods are possible in these cases, for example, a well-known reflection or secondary electron detection method can be used. That is, for example, the position of the mark M7 can be known by irradiating the mark EB from the EB source ES0 toward the mark EB and detecting the reflection or secondary electron thereof by the sensor S7. As the sensor 7, for example, a semiconductor PN junction is used.

However, in the case of such mark detection by EB, E
It is necessary to set the intensity of B and the irradiation time to values that do not hinder the reading of marks.

Further, when a plurality of marks are detected at one time, it is preferable to perform EB irradiation at different timings for each mark and to detect at different timings.
B irradiation can be easily differentiated and detected by a single signal processing means.

Further, when a light sensitive element such as a CCD is used as the sensor, it is obvious that a light source may be prepared instead of the EB source.

FIG. 2 (a) is a partial bottom view showing an example of the EB emitting head MB and shows one EB emitting source. Fig. 2 (b)
2 and FIG. 2 (c) are sectional views taken along the line BB and CC, respectively.
FIG.

In FIG. 2, GL is an insulating substrate, which is made of glass, ceramics, crystals, or the like. The substrate GL
The surface conduction type EB emission source shown in FIG.
Many are arranged in one row in the B direction. This EB emission source has a high resistance thin film RS and electrodes D1 and D2 attached to the lower surface of the substrate GL. The high resistance thin film RS is, for example, Pt,
It is formed by energizing a metal thin film of Au, Mo, C, Pd, or the like or a metal oxide thin film of SnO ₂ , In2O ₃ , TiO, or the like at high temperature to cause film breakdown. The thickness of the high resistance thin film RS is, for example, 100.
The resistance is, for example, about several KΩ to several hundreds MΩ. As illustrated, electrodes D1 and D2 are connected to both ends of the high resistance thin film RS in the CC direction. The electrode is a general thin film electrode made of a metal such as Pt, Au, Ag or the like.

An insulating layer IS is formed on the lower surface of the substrate GL so as to cover the electrodes D1 and D2, except for the portion below the high resistance thin film RS. The insulating layer is, for example, SiO ₂ , SiN, Si ₃ N ₄ ,
It consists of AlN, BN, etc. On the lower surface of the insulating layer IS, a pair of deflection electrodes X1-X2 and Y1-Y2 are arranged in parallel with each other in the BB and CC directions of the high resistance thin film RS. The deflection electrode is also made of the same material as the electrodes D1 and D2.

S9 and S10 are the above-mentioned optical sensor or electronic sensor.
This sensor may be further provided in the 1-to-Y direction, or may be provided in an annular shape. When the EB generation source and the sensor are integrally formed in this way, the positional accuracy between the sensor and the EB generation source is fixed, so that the detection accuracy is improved. When an optical sensor is used, it is preferable that the alignment light source LP is also incorporated in the head MB as shown in FIG. 2 (c).
When a solid state element such as a light emitting diode is used as the light source LP, a semiconductor manufacturing technique or a thick film
It can be formed at the same time by the thin film manufacturing technology.

Further, when an ultraviolet light source or a far ultraviolet light source is used as the light source LP, it can be used also for stimulating the resist WR on the wafer WF. If this is done before the EB exposure, a thin hardly soluble layer is formed on the surface of the resist WR.
B exposure makes it more difficult to dissolve. According to this, since the ratio of the film thickness to the drawn line width can be increased, the sensitivity or resolution (aspect ratio) is improved, which is preferable. As the resist, for example, a trade name “RD20
00N "(manufactured by Hitachi Chemical Co., Ltd.) can be used. Further, when the light source LP is built in the head MB, there is an advantage that the entire apparatus can be downsized because pre-exposure can be performed when moving relative to the wafer WF.

Furthermore, the thin-film RS (electron emitting portion) may be irradiated with the far-ultraviolet light source LP during exposure. This is preferable because the number of emitted electrons increases. Further, when the light source LP is a visible light source, the same effect can be obtained by using the thin film RS as a so-called photocathode material. As the photocathode material, for example, a material having a semiconductor property of a composite material of an alkali metal and Ag, Bi, Sb, a silver-cesium material, an antimony-mosium material, a bismuth-cesium material, a multi-alkali material, and the like can be used. .

Further, as an EB generation source, in addition to this, JP-A-54-111272
It is also possible to use the semiconductors disclosed in Japanese Patent Publication (USP 4259678) and the like. Further, the thin film RS may be irradiated with the light source LP only when drawing a thick line width.

In the present invention, a plurality of such EB generation sources are arranged close to each other and configured as one unit of EB source. FIG. 3 is a partial cross-sectional view showing an example of an EB emission head in which a plurality of EB sources ES1 and ES2 are set as one unit of EB sources. According to this example, a large amount of electrons can be emitted even at low voltage driving, which is preferable. Further, according to the line width data of the drawn line included in the drawing information sent from the memories MU and ML, the thin line is drawn by only one EB generation source, and the thick line is drawn by both EB generation sources. Is drawn with. Thereby, a thick line can be drawn at once and the line width can be changed during drawing, so that the drawing speed is improved. Also here, if the light irradiation is added as in the previous case, the efficiency is further improved.

Further, a focusing lens FC, a deflection electrode AD, etc. may be attached. Furthermore, if the member to which the lens FC and the electrode AD are attached has a multi-chamber structure and the degree of vacuum is lowered, EB exposure in the atmosphere becomes possible. That is, as shown in the figure, the members V1, V2, V3 and the like form multiple chambers, and the degree of vacuum may be lowered in the order of 1st, 2nd, 3rd. In this way, the vacuum chuck VC can be used for attracting the wafer WF. At this time, the sensors S11 and S12 may be attached to the lower surface of the member V1 or the like.

FIG. 4 is a partial sectional view showing still another example of the EB emitting head. In the figure, BG is the EB emission source as described above, but as described above, when the electron beam EB is irradiated from here to the wafer mark WM, secondary electrons and reflected electrons 2E are generated from the wafer WF. . And
A sensor, such as P /
The wafer mark WM is detected by receiving at the N junction PN. However, here, in order to detect electrons efficiently, the annular electrodes C1 and C2 are attached to the substrate MB side. The voltage Vex is applied between the electrode C1 and the EB generation source BG, the voltage Vd is applied to the electrode C2, and the EB generation source B is applied.
A voltage Vc is connected between G and the wafer WF as shown.

Therefore, for example, Vex = 10 to 100 V, Vc = 1 to 10
By applying KV and Vd = 100V, respectively, the secondary electrons and backscattered electrons 2E can be efficiently collected at the P / N junction portion PN.

FIG. 5 is a schematic view showing a modification of the apparatus shown in FIG.

In the figure, the head MB1 has four EBs for each chip.
The sources ES1 to ES4 are made correspondingly. That each E
The B source is equipped with X and Y deflection electrodes as in the device of FIG. In this case, for each chip, 4
Since one divided area can be simultaneously drawn by the X and Y deflection electrodes according to the same principle as in FIG. 1, the drawing speed is further improved. Further, the head MB1 is provided with an alignment mark MM, and this mark is aligned with the wafer alignment mark WMR by light irradiation.

After this alignment, drawing is first performed on all the chips in the Y-direction chip row located under the head MB1 at this time. Then, the other chip rows are also moved intermittently (step by step) after this, and similar alignment and drawing are repeated.

However, since the wafer WF is usually circular, the wafer alignment mark WMR may not be provided for all the Y-direction chip rows. At this time, the alignment may be performed for only one column at the center of the wafer first, and then the exposure may be performed without feedback. Or first the wafer WF
After using the mark WMR in the center of the
The exposure is advanced in the right direction, and when the right half is completed, it is inverted in the left direction and either the mark WMR is used again or the alignment mark WML of the unexposed portion is used for alignment again, and then the left exposure is performed. May be.

A head MB2 is shown in FIG. 5 to show still another alignment exposure method.

In this case, the head MB2 is initially located at the left end portion of the wafer WF, and first, the mark SM provided on the wafer stage is detected by the sensor S1 to perform prealignment. Next, in this state, the marks M1 and M2 and the sensor S are
The amount of deviation is measured by 2 and S3. Then, at the time of exposure, the X and Y deflection electrodes are used or both of them are used to perform the exposure while correcting the amount of deviation. In the next column, the mark M3 is used to measure the amount of deviation as in the previous case, and exposure is performed based on the result. Similarly, the shift amount is measured and the exposure is performed in the next row, but the re-prealignment may be performed using the mark WML before that.

Further, using the mark M4, the displacement amount of the head positioned in that row is measured, and after exposing the area covered by each EB source ES and the electrodes X1 and X2 at that position, the head or wafer is continuously moved. Exposure is carried out, and when the chip row is completed, the head or wafer is marked M
It is also possible to stop at the position 5 and perform the same operation as before. This can be said to be an intermediate type between the so-called step-and-repeat and step-and-scan exposure methods.

FIG. 6 shows another modification of the apparatus shown in FIG.

FIG. 10A shows an example in which a plurality of heads MB1 and MB2 are provided and the wafer WF is in charge of the right half and the left half, respectively, which makes it possible to further improve the throughput.

FIG. 3B shows an example in which the small diameter wafers WF1 and WF2 are exposed by a single head MB, and the throughput can be improved.

FIG. 6C shows an example in which short heads MB1, MB2, MB3 are arranged in the Y direction so that it is possible to suitably cope with a large-diameter wafer WF of 8 inches or more when it is difficult to manufacture a long head. At this time, since it is usual that each end portion needs the alignment mark detecting portion and the portion for strengthening the strength as described above, it is preferable to arrange them in a zigzag shape as shown in FIG.

In the same figure (d), a plurality of EB sources are provided in a single head MB, and the diameters of the emitted EBs are made different. That is, the EB sources ES1 and ES2 have a large diameter and the EB source E
S3 and ES4 are medium apertures, EB sources ES5 to ES8 ... Are small aperture EB sources, and usually, EB sources ES5 to ES8 ... are used to perform exposure for the time being, with the middle and large portions of the line width remaining. , EB source E for medium or large line width
It exposes using S4, ES2, etc. At this time, the head or wafer is moved so that the corresponding line width portion of each chip can be exposed.

FIG. 7 is a schematic view showing still another modified example. This E
The B emission head is designed to detect the wafer mark by the magnitude of the current absorbed by the wafer WF, not by the sensor provided on the head side.

In the figure, WF is a wafer containing a semiconductor. GL
Is a single substrate provided with respective sources BG1 to BG7 of a plurality of electron beams EB1 to EB7. For example, glass and semiconductor described in JP-A-54-111272 and JP-A-56-15529. A substrate such as can be used. BS is a selection drive circuit for the electron beam generators BG1 to BG7, CC is an overall control unit, and AS is an electron beam absorption current detection circuit for detecting the alignment marks WM1 to WM7 on the wafer WF. Further, an electron lens, a deflection electrode or a blanking electrode (not shown) as described with reference to FIGS. 2 and 3 are provided if necessary.

In this configuration, when the alignment mark on the wafer WF is at the positions of the solid lines WM2 and WM6, the actual circuit element pattern is inside thereof. So in this case, first,
Electron beams EB3 and E for drawing actual circuit element patterns
The selection circuits BS select the electron beams EB2 and EB6 for detecting alignment marks B4 and EB5. Next, the electron beams EB2 and EB6 are emitted to emit the wafer W.
The positions of the marks WM2 and WM6 are detected by absorbing with F and detecting the magnitude of the current by a known method. However, as described above, the electron beams EB2 and EB6
Are emitted and detected at different timings so that they can be distinguished. Then, based on this, the wafer WF is aligned,
Then, the electron beams EB3, EB4, EB5
Alternatively, as shown in FIG. 5, the circuit pattern is exposed.

On the other hand, when the alignment marks are the broken lines WM3 and WM5, the electron beams EB3 and EB5 are used for alignment, and the electron beams EB4 and / or EB1 and EB are used.
2, EB6 and EB7 are used for exposure. Also, the broken line W
When M1 and WM7 are alignment marks, the electron beams EB1 and EB7 are for alignment and the electron beam EB2 is for alignment.
~ EB6 is for exposure.

[Applicable Range of the Invention] The present invention is applicable not only to the exposure (drawing) of the semiconductor circuit pattern by the electron beam described in the above embodiments, but also to the data writing to the recording medium using the charged beam sensitive medium. It is also possible to apply to the reading of such data by combining with a charged particle sensor.

Specifically, for example, in the recording and tracking of a magneto-optical recording medium such as an optical disk and an optical card or microfilm, it can be selectively used for writing and reading.

Also, as an electron beam probe tester for semiconductor function inspection, it can be used by selecting an electron beam generation source according to a chip size and a measurement point. At this time, output may be prohibited except for the electron beam generator for measurement.

Further, when used for a plurality of purposes, it is easy to make the output energy different for each application and also for each electron beam source, which is suitable for use in the previous embodiment.

[Effects of the Invention] As described above, the present invention has the following effects.

(1) Since exposure etc. can be performed by multiple charged beam sources,
The processing is quick.

(2) By properly arranging a plurality of charged beam generation sources, problems of heat generation and interference between beams can be avoided. Further, since the heat generation can be minimized, the durability of the device is excellent.

(3) Since a plurality of electron sources and the like can be integrally formed on a single substrate, the device can be downsized and the accuracy can be improved.

(4) By constructing one charged particle beam generation source with a plurality of charged particle beam emitters, a large amount of electrons can be emitted even at low voltage driving. In addition, the beam intensity can be easily adjusted. For example, the drawing speed can be improved by making it possible to draw thin lines and thick lines.

(5) By providing the deflection means in each charged beam generation source, it is possible to irradiate the charged beam over a wide range even in a stationary state, and it is possible to precisely and easily perform fine adjustment of the beam direction.

(6) By providing a means for detecting the charged beam or secondary or reflected electrons of the charged beam, alignment can be performed without providing a special light source and its detecting means, and the apparatus can be made smaller and simpler. Can be converted.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing the configuration of a charge beam device according to an embodiment of the present invention when applied to the exposure of a semiconductor wafer, and FIG. 2 is a specific example of a head that can be used in the device of FIG. FIG. 2A is a bottom view and FIG. 2B is a B view of FIG.
-B sectional view, the same figure (c) is a CC sectional view of the same figure (a), FIGS. 3 and 4 are partial sectional views showing other examples of the head that can be used in the apparatus of FIG. 5 is a schematic diagram showing a modification of the apparatus of FIG. 1, FIG. 6 is a schematic view showing another modification of the apparatus of FIG. 1, and FIG. 7 is a schematic view of the apparatus of FIG. It is a schematic diagram which shows another modification. MB, MB1, MB2, MB3: electron beam emission head, ES, ES0 to ES15: electron beam generation source, WF,
WF1, WF2: Wafer, M1 to M8, WM, WM1
WM7, WMR: alignment mark, S1 to S12: sensor, X1, X2, Y1, Y2, AD: deflection electrode, CP
1 to CP34, CPn: exposure area corresponding to one chip, M
S: Stage, Px, Py, Pθ: Piezoelectric element, CP1
U: upper half area, CP1L: lower half area, PG: 1 chip pattern generator, MU, ML: memory, GL:
Substrate, RS: High-resistance thin film, D1, D2: Electrode, IS: Insulating layer, LP: Light source, WR: Resist, FC: Focusing lens, PN: P / N junction, EB, E
B1 to EB7: electron beam, CC: control unit, AS: detection circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication H01L 21/027 (72) Inventor Takeo Tsukamoto 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. In-house (72) Inventor Akira Suzuki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Tetsuya Kaneko 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72 ) Inventor Toshihiko Takeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Mitsuaki Seki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) References Special Kai 56-98827 (JP, A) JP 53-82257 (JP, A) JP 60-17832 (JP, A)

Claims (2)

[Claims] 1. A means for storing pattern data to be drawn on a medium, and a plurality of electron beam generating sources arranged in proximity to each other.
At least one or more unit electron beam generators as a unit, means for deflecting the electron beam emitted by the unit electron beam generator, and data of a line width included therein based on the stored pattern data. Accordingly, each unit electron beam generation source is provided with drive control means for selectively driving the plurality of electron beam generation sources and controlling the deflection means to perform drawing on the medium. Drawing device. 2. The electron beam drawing apparatus according to claim 1, wherein the medium is a semiconductor wafer coated with a resist.