JPH06195272A - Bus arbitration circuit - Google Patents

Abstract

PURPOSE:To detect a device in which a fault that a bus cycle is not started even if permission for using a bus is received occurs. CONSTITUTION:When an encoding part 2 selects one of bus use request signals 21 to 23 from input/output devices 11 to 13, it sends that selection information to a decoding part 3 and a discrimination circuit 4. The decoding part 3 outputs a bus use permission signals 31 to 33 corresponding to that selection information to the input/output devices 11 to 13. In the input/output dices 11 to 13, the bus use request signals 21 to 23 is reset in response to the input of the bus use permission signals 31 to 33. When the discrimination circuit 4 detects that a bus busy signal is not sent from the input/output devices 11 to 13 even if definite time (t) elapses after the bus use permission signals 31 to 33 is inputted, it sends the information of the device in which the fault has occurred to a register 5 on the basis of the selection information from the encoding part 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration circuit, and more particularly to a method for detecting and recovering a faulty device that does not start using a bus even though a bus use permission is output.

[0002]

2. Description of the Related Art Conventionally, in a bus arbitration circuit, in response to a bus use request from an input / output device connected to a common bus, the right to use the common bus is arbitrated based on priority information of each input / output device. However, the bus use permission signal is output to the device that is permitted to use the common bus.

In a system using the bus arbitration circuit as described above, there is a high possibility that the system will go down when a failure occurs in each device connected to the common bus or the bus arbitration circuit itself. Therefore, various measures are taken. Has been.

For example, in the technique disclosed in Japanese Patent Laid-Open No. 61-32162, arbitration circuits are provided in a distributed manner in each module constituting the system, and the arbitration circuits connected to the bus cooperate as a whole. Therefore, a method is proposed in which the system does not go down even if a failure occurs in one arbitration circuit.

Further, according to the technique disclosed in Japanese Patent Laid-Open No. 32-32446, when a state in which a memory access request is still output from a faulty line unit is detected, the memory access request is forced. A method of minimizing the influence of the failure on the system is proposed.

Further, in the technique disclosed in Japanese Patent Laid-Open No. 2-123448, the time measuring means outputs the control signal by the bus usage right control means in accordance with the time relating to the output state of the control signal by the bus usage right control means. By instructing the stop of the processing device, there is proposed a method of avoiding occupation of the bus by the processing device when a failure occurs in the processing device.

Furthermore, in the technique disclosed in Japanese Patent Laid-Open No. 2-158854, the bus arbiter and the slave unit monitor the error state of data being transferred,
When an exception occurs, the failure unit is notified of that fact and the data transfer is stopped, and when a protocol error for the bus usage right issuance request is detected, the unit that issued the bus usage right issuance request is notified. A method has been proposed for preventing the entire system from being stopped by a failed unit by notifying.

In addition to the above-mentioned methods, while the master unit is sending out individual information, the slave unit or the bus arbiter sends a response, and when a failure occurs, the failure and the content of the failure are reported. By using the response to notify that the bus is released early when a failure occurs, a method is disclosed in Japanese Patent Laid-Open No. 2-1.
It is proposed by the technique disclosed in Japanese Patent Publication No. 59658.

Although various methods are used to prevent the system from going down when a failure occurs, the conventional bus arbitration circuit is used when a failure occurs such that an input / output device that has received a bus use permission does not start a bus cycle. Only notifies the upper device of the failure as an error report.

[0010]

In the above-mentioned conventional bus arbitration circuit, when an input / output device which receives a bus use permission does not start a bus cycle, it simply reports an error to the host device. There is a problem that it is difficult to determine which input / output device the failure has occurred.

Therefore, an object of the present invention is to solve the above problems and to provide a bus arbitration circuit capable of detecting a device in which a failure occurs that a bus cycle is not started even when a bus use permission is received.

[0012]

A bus arbitration circuit according to the present invention arbitrates the right to use the common bus in response to a bus use request from a plurality of input / output devices connected to the common bus. Is a bus arbitration circuit that outputs a bus use permission signal to a device that has been permitted to use the bus, and monitors whether or not a bus busy signal is output from the device in response to the bus use permission signal within a predetermined time. The monitoring means and the storage means for storing the information of the device when the monitoring means detects that the bus busy signal is not output within the predetermined time.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, the encoding unit 2 of the bus arbitration circuit 1 selects one of the bus use request signals 21 to 23 received from the input / output devices 11 to 13, and sends the selection information to the decoding unit 3 and the determination circuit 4. .

The decoding unit 3 outputs the bus use permission signals 31 to 33 to the input / output devices 11 to 13 according to the selection information from the encoding unit 2. Further, the determination circuit 4 holds the selection information from the encoding unit 2, and the input / output devices 11 to 13 corresponding to the selection information and the bus use permission signals 31 to 33.
I / O device 11 depending on whether there is a bus busy signal from
It is determined whether or not a failure has occurred in any one of to 13. Here, a bus busy signal from the input / output devices 11 to 13 corresponding to the bus use permission signals 31 to 33 is input to the determination circuit 4 via the encoding unit 2.

Discrimination information from the discrimination circuit 4 is written in the register 5 when a failure occurs in one of the input / output devices 11 to 13. That is, the register 5 holds information indicating which input / output device 11 to 13 has failed, and outputs the information in response to an access from a host device (not shown).

Each of the input / output devices 11 to 13 has an input / output bus 6
Bus connection request signal 21
.About.23 signal lines and bus use permission signals 31 to 33, respectively.

2 and 3 are timing charts showing the operation of one embodiment of the present invention. 2 shows a normal operation in one embodiment of the present invention, and FIG. 3 shows an operation when a failure occurs in one embodiment of the present invention. The operation of the embodiment of the present invention will be described with reference to FIGS.
Hereinafter, the bus use request signal 21 output from the input / output device 11
On the other hand, the case where the bus arbitration circuit 1 outputs the bus use permission signal 31 will be described.

When a normal bus arbitration operation is performed, when the encoding unit 2 selects the bus use request signal 21 from the bus use request signals 21 to 23 from the input / output devices 11 to 13, the encode unit 2 causes the decode unit to perform decoding. 3 and discrimination circuit 4
The selection information indicating that the bus use request signal 21 has been selected is sent to.

When the selection information is sent from the encoding section 2, the decoding section 3 outputs a bus use permission signal 31 corresponding to the bus use request signal 21 to the input / output device 11.
The input / output device 11 resets the bus use request signal 21 in response to the input of the bus use permission signal 31. After that, the input / output device 11 sends a bus busy signal to the bus arbitration circuit 1 via the input / output bus 6, and performs data transfer using the input / output bus 6.

When the bus busy signal is output from the input / output device 11 to the bus arbitration circuit 1, the encoder 2 outputs the information that the bus busy signal is input to the decoder 3 and the discrimination circuit 4. When the information is sent from the encoding unit 2, the determining circuit 4 determines that the arbitration of the bus is normally completed, and the decoding unit 3 resets the bus use permission signal 31 to the input / output device 11 (see FIG. 2).

On the other hand, in the case of a bus arbitration, when a failure occurs in which the input / output device 11 permitted to use the bus does not output the bus busy signal, the following operation is performed. When the encoder unit 2 selects the bus use request signal 21 from the bus use request signals 21 to 23 from the input / output devices 11 to 13, the decoder unit 3 and the discrimination circuit 4 receive the bus use request signal 2
The selection information that 1 has been selected is transmitted.

When the selection information is sent from the encoding section 2, the decoding section 3 outputs a bus use permission signal 31 corresponding to the bus use request signal 21 to the input / output device 11.
The input / output device 11 resets the bus use request signal 21 in response to the input of the bus use permission signal 31.

After that, if the input / output device 11 does not send the bus busy signal to the bus arbitration circuit 1 even after a certain time (t) has elapsed after the bus use permission signal 31 is input, the discrimination circuit 4 is kept constant. An internal timer (not shown) indicates that the bus busy signal is not transmitted from the input / output device 11 within the time (t).
Detect by.

The discriminating circuit 4 discriminates a failure when the bus use request signal 21 is selected based on the detection result and the information from the encoding section 2, and sends the information to the register 5. When the information is sent from the discrimination circuit 4 to the register 5, the decoding unit 3 resets the bus use permission signal 31 to the input / output device 11 (see FIG. 3).

The register 5 has a bit width corresponding to the number of the input / output devices 11 to 13 connected to the input / output bus 6.
When the information from the discriminating circuit 4 is received, a flag is set to the relevant bit. In this case, the register 5 holds the information that the I / O device 11 has failed.

At this time, since the bus arbitration circuit 1 reports an error to the host device, the host device accesses the register 5 of the bus arbitration circuit 1 according to the error report, so that which input / output device fails. Can be read.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention. In the figure, another embodiment of the present invention has the same configuration as that of the first embodiment of the present invention except that the bus arbitration circuit 1 has a function of masking a bus use request signal of a failed input / output device. The same components are designated by the same reference numerals. The operation of those same constituent elements is similar to the operation of the embodiment of the present invention.

The mask circuit 7 includes the discrimination circuit 4 through the register 5
The bus use request signals 21 to 23 from the input / output devices 11 to 13 are masked based on the information transmitted to the input / output device, that is, the information indicating which input / output device has failed.

Therefore, when the discriminating circuit 4 detects by the internal timer that the bus busy signal is not transmitted from the input / output device within the fixed time (t), the bus use request signal from the input / output device is subsequently sent to the bus. Since it is not accepted by the arbitration circuit 1, the input / output device is disconnected from the input / output bus 6.

FIG. 5 is a timing chart showing the operation when a failure occurs in another embodiment of the present invention. In another embodiment of the present invention with reference to FIGS. 4 and 5, a failure occurs when the bus arbitration circuit 1 outputs the bus use permission signal 31 in response to the bus use request signal 21 output from the input / output device 11. The operation at that time will be described.

When a failure occurs in the bus arbitration, in which the input / output device 11 permitted to use the bus does not output the bus busy signal, the following operation is performed. The encoding unit 2 uses the bus use request signal 21 from the input / output devices 11 to 13.
23 to 23, the bus use request signal 21 is selected, and selection information indicating that the bus use request signal 21 is selected is sent to the decoding unit 3 and the determination circuit 4.

When the selection information is sent from the encoding section 2, the decoding section 3 outputs a bus use permission signal 31 corresponding to the bus use request signal 21 to the input / output device 11.
The input / output device 11 resets the bus use request signal 21 in response to the input of the bus use permission signal 31.

After that, if the input / output device 11 does not send the bus busy signal to the bus arbitration circuit 1 even after a lapse of a certain time (t) after the bus use permission signal 31 is input, the determination circuit 4 determines the certain time. The internal timer detects that the bus busy signal is not transmitted from the input / output device 11 within (t).

The discriminating circuit 4 discriminates a failure when the bus use request signal 21 is selected based on the detection result and the information from the encoding section 2, and sends the information to the register 5 and the mask circuit 7. When the mask circuit 7 receives the information from the determination circuit 4, the mask circuit 7 masks the bus use request signal 21 of the input / output device 11 so that the bus use request signal 21 from the input / output device 11 is not accepted thereafter. At this time,
The decoding unit 3 uses the bus use permission signal 3 to the input / output device 11.
1 is reset (see FIG. 5).

When the register 5 receives the information from the discriminating circuit 4, it sets a flag in the corresponding bit and holds the information that the failure has occurred in the input / output device 11. Since the bus arbitration circuit 1 reports an error to the host device, the host device can access the register 5 of the bus arbitration circuit 1 according to the error report to read which input / output device has failed. it can.

After that, the bus arbitration circuit 1 keeps masking the bus use request signal 21 and outputs another bus use request signal 22,
Bus arbitration is performed only by 23. For example, in this state, when the encoder 2 selects the bus use request signal 22 from the bus use request signals 22 and 23 from the input / output devices 12 and 13, the encoder 2 requests the decoder 3 and the determination circuit 4 to use the bus. The selection information that the signal 22 has been selected is transmitted.

When the selection information is sent from the encoding unit 2, the decoding unit 3 outputs a bus use permission signal 32 corresponding to the bus use request signal 22 to the input / output device 12.
The input / output device 12 resets the bus use request signal 22 in response to the input of the bus use permission signal 32. After that, the input / output device 12 sends a bus busy signal to the bus arbitration circuit 1 via the input / output bus 6 and transfers data using the input / output bus 6.

When the bus busy signal is output from the input / output device 12 to the bus arbitration circuit 1, the encoding unit 2 outputs the information that the bus busy signal is input to the decoding unit 3 and the discrimination circuit 4. When the information is sent from the encoding unit 2, the determination circuit 4 determines that the arbitration of the bus is normally completed, and the decoding unit 3 resets the bus use permission signal 32 to the input / output device 12 (see FIG. 5).

As described above, when a failure occurs in the bus arbitration of the bus arbitration circuit 1, the failure input / output device is determined by the determination circuit 4 using the selection information from the encoding unit 2 and the internal timer. By storing the information of the faulty device in the register 5 based on the determination result, it is possible to detect the faulty device that does not start the bus cycle even if the bus use permission is received and to disconnect the device from the system. Become. Therefore, even if a failure occurs that the bus cycle is not started even when the bus use permission is received, it is possible to continue the system operation and improve the maintainability.

[0041]

As described above, according to the present invention, it is monitored whether the bus busy signal is output from the device within a predetermined time in response to the bus use permission signal, and the predetermined time is monitored by the monitoring. By storing the device information when it detects that the bus busy signal was not output in the device, it is possible to detect a device that has a fault that it does not start a bus cycle even if a bus use permission is received. There is an effect that.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a timing chart showing a normal operation in one embodiment of the present invention.

FIG. 3 is a timing chart showing an operation when a failure occurs in the embodiment of the present invention.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a timing chart showing an operation when a failure occurs in another embodiment of the present invention.

[Explanation of symbols]

 1 bus arbitration circuit 2 encoder part 3 decoder part 4 discrimination circuit 5 register 6 input / output bus 7 mask circuit 11-13 input / output device 21-23 bus use request signal 31-33 bus use permission signal

Claims (2)

[Claims] 1. A arbitration of the right to use the common bus in response to a bus use request from a plurality of input / output devices, each of which is connected to the common bus, and a bus use permission signal is sent to a device permitted to use the common bus. A bus arbitration circuit for outputting, and monitoring means for monitoring whether or not a bus busy signal is output from the device within a predetermined time in response to the bus use permission signal,
A bus arbitration circuit comprising: storage means for storing information of the device when the monitoring means detects that the bus busy signal is not output within the predetermined time. 2. When the monitoring means detects that the bus busy signal is not output within the predetermined time, it has means for prohibiting acceptance of the bus busy request from the device. The bus arbitration circuit according to claim 1.