JPH06151850A - Thin film transistor - Google Patents
Thin film transistorInfo
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- JPH06151850A JPH06151850A JP4295763A JP29576392A JPH06151850A JP H06151850 A JPH06151850 A JP H06151850A JP 4295763 A JP4295763 A JP 4295763A JP 29576392 A JP29576392 A JP 29576392A JP H06151850 A JPH06151850 A JP H06151850A
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- Prior art keywords
- insulating film
- film
- insulating
- active layer
- tft
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶ディスプレイやイ
メージセンサー等にスイッチ素子として用いられる薄膜
トランジスタ（以下「ＴＦＴ」と略称する）に関し、特
にＸ線あるいは放射線等の高エネルギー粒子（以下「高
エネルギー粒子」と略称する）の照射に対して低感度の
ＴＦＴに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter abbreviated as "TFT") used as a switch element in a liquid crystal display, an image sensor or the like, and particularly to high energy particles such as X-rays or radiation (hereinafter "high energy"). Abbreviated as “particle”).
【０００２】[0002]
【従来の技術】従来のＴＦＴの代表的な構造を図６ない
し図８に示す。（１０１），（１１１）及び（１２１）
はガラス基板、（１０２），（１１２）及び（１２２）
はゲート電極、（１０３），（１１３）及び（１２３）
はゲート絶縁膜、（１０４），（１１４）及び（１２
４）は半導体活性層、（１０５），（１１５）及び（１
２５）はオーミックコンタクト層、（１０６），（１１
６）及び（１２６）はソース・ドレイン層、（１０
７），（１１７）は保護絶縁膜、（１０８），（１１
８）はバックゲート電極、（１１９）はバック絶縁膜、
（１１０），（１２０）及び（１３０）はソース・ドレ
イン配線である。2. Description of the Related Art A typical structure of a conventional TFT is shown in FIGS. (101), (111) and (121)
Is a glass substrate, (102), (112) and (122)
Is a gate electrode, (103), (113) and (123)
Is a gate insulating film, (104), (114) and (12
4) is a semiconductor active layer, (105), (115) and (1
25) is an ohmic contact layer, (106), (11
6) and (126) are source / drain layers, and (10)
7) and (117) are protective insulating films, and (108) and (11).
8) is a back gate electrode, (119) is a back insulating film,
(110), (120) and (130) are source / drain wirings.
【０００３】このうち、図６及び図７に示すＴＦＴは、
ゲート電極（１０２），（１１２）がそれぞれ底部に形
成されていることから「ボトムゲート型」、図８のＴＦ
Ｔはゲート電極（１２２）が上方に形成されていること
から「トップゲート型」と呼ばれる。Of these, the TFTs shown in FIGS. 6 and 7 are
Since the gate electrodes (102) and (112) are formed on the bottoms, respectively, "bottom gate type", TF of FIG.
T is called "top gate type" because the gate electrode (122) is formed above.
【０００４】また、図６のＴＦＴと図７のＴＦＴとは、
チャネルの形成方法が異なる。すなわち、図６のＴＦＴ
はエッチングにより形成され、図７のＴＦＴはバック絶
縁膜（１１９）によりチャネルが形成されている。The TFT shown in FIG. 6 and the TFT shown in FIG.
The channel formation method is different. That is, the TFT of FIG.
Are formed by etching, and the TFT of FIG. 7 has a channel formed by the back insulating film (119).
【０００５】ＴＦＴは、ゲート電極／ゲート絶縁膜／活
性層／絶縁物を積層してなる半導体構造で、ゲート電極
に電圧を印加することにより、ゲート絶縁膜と活性層と
の界面近傍の活性層内にキャリアが誘起され、電流がソ
ース・ドレイン電極間を流れるＯＮ状態となる。ＯＮ状
態時の電流は、キャリア密度とキャリアの移動度によっ
て決定される。一方、ゲート電極に電圧が印加されない
ＯＦＦ状態のソース・ドレイン電極間を流れる電流は、
主に活性層の抵抗値で決まる。The TFT has a semiconductor structure in which a gate electrode / gate insulating film / active layer / insulator is laminated. By applying a voltage to the gate electrode, the active layer near the interface between the gate insulating film and the active layer is formed. Carriers are induced therein, and an electric current flows between the source / drain electrodes to be in an ON state. The current in the ON state is determined by the carrier density and carrier mobility. On the other hand, the current flowing between the source and drain electrodes in the OFF state where no voltage is applied to the gate electrode is
It is mainly determined by the resistance value of the active layer.
【０００６】前述の図６ないし図８に示した３種の構造
は、それぞれ電極の配置等に多少の差異はあるものの、
活性層を絶縁膜で挟み込んでいるという構造において共
通している。The above-described three types of structures shown in FIGS. 6 to 8 have some differences in the arrangement of electrodes, etc.
It has a common structure in which the active layer is sandwiched by insulating films.
【０００７】[0007]
【発明が解決しようとする課題】ＴＦＴの特性は、ＯＮ
状態時の電流とＯＦＦ状態時の電流との比が大きいこと
が要求される。ＯＮ状態時の電流の増大は、ゲート絶縁
膜や活性層の膜質改善によってなされてきた。他方、Ｏ
ＦＦ状態時の電流を低減させるためには、活性層の膜厚
を薄くして抵抗値をできるだけ大きくしていた。The characteristics of the TFT are ON.
It is required that the ratio of the current in the state and the current in the OFF state is large. The increase in current in the ON state has been made by improving the film quality of the gate insulating film and the active layer. On the other hand, O
In order to reduce the current in the FF state, the film thickness of the active layer is reduced and the resistance value is increased as much as possible.
【０００８】しかしながら、上述した従来のＴＦＴで
は、高エネルギー粒子の照射によってＯＦＦ状態時の電
流が増加する問題があった。図９に、Ｘ線照射によるＴ
ＦＴのゲート電極に対するソース・ドレイン電極間の電
流変化を示す。図９において、（１４１）は線量率１０
ｍＲ／ｍｉｎのＸ線を照射した際のＴＦＴのゲート電圧
とドレイン電流の関係、（１４２）はＸ線非照射時にお
けるＴＦＴのゲート電圧とドレイン電流の関係を示して
いる。この現象を図１０により説明する。図１０は、図
６のＴＦＴのフラットバンド状態におけるエネルギーバ
ンド図である。同図において、（１５１）はバックゲー
ト電極、（１５２）は保護絶縁膜、（１５３）は活性
層、（１５４）はゲート絶縁膜、（１５５）はゲート電
極、（１５６）は正孔、（１５７）は伝導電子、そして
（１５８）はエネルギーｈνを有する高エネルギー粒子
である。高エネルギー粒子（１５８）のエネルギーｈν
は、保護絶縁膜（１５２）、ゲート絶縁膜（１５４）の
禁制帯幅に比べて十分大きいため、前記両絶縁膜の価電
子帯の電子を伝導帯にまで叩き上げ、電子−正孔対を作
ることが可能である。従って、前記電子−正孔対が拡散
して活性層（１５３）の伝導帯（価電子帯）に達するこ
とにより、ＯＦＦ状態時の電流が増大している。However, the conventional TFT described above has a problem that the current in the OFF state increases due to the irradiation of the high energy particles. Fig. 9 shows T by X-ray irradiation.
The change in current between the source and drain electrodes with respect to the gate electrode of the FT is shown. In FIG. 9, (141) is the dose rate 10
The relationship between the gate voltage and drain current of the TFT when irradiated with mR / min of X-ray, (142) shows the relationship between the gate voltage and drain current of the TFT when not irradiated with X-ray. This phenomenon will be described with reference to FIG. FIG. 10 is an energy band diagram in the flat band state of the TFT of FIG. In the figure, (151) is a back gate electrode, (152) is a protective insulating film, (153) is an active layer, (154) is a gate insulating film, (155) is a gate electrode, (156) is a hole, ( 157) is a conduction electron, and (158) is a high energy particle having energy hν. Energy hν of high energy particles (158)
Is sufficiently larger than the forbidden band widths of the protective insulating film (152) and the gate insulating film (154), the electrons in the valence band of both insulating films are pushed up to the conduction band to form an electron-hole pair. It is possible. Therefore, the electron-hole pair diffuses and reaches the conduction band (valence band) of the active layer (153), so that the current in the OFF state increases.
【０００９】また、従来のＴＦＴ構造では活性層の膜厚
に比較して絶縁膜の膜厚が大きいため、高エネルギー粒
子によって伝導電子が発生する確率を無視できない。こ
のような問題は、例えば宇宙空間での使用やＸ線像の直
接撮像等の場合に顕著である。Further, in the conventional TFT structure, since the thickness of the insulating film is larger than that of the active layer, the probability that conduction electrons are generated by high energy particles cannot be ignored. Such a problem is prominent in use in outer space and direct imaging of X-ray images, for example.
【００１０】本発明は、かかる従来の問題点を解決する
ためになされたもので、絶縁膜中に発生した伝導電子や
正孔を活性層側に拡散させないようにし、ＯＦＦ状態時
の電流を低減させたＴＦＴを提供することを目的とす
る。The present invention has been made to solve the above-mentioned conventional problems, and prevents conduction electrons and holes generated in the insulating film from diffusing to the active layer side, and reduces the current in the OFF state. It is an object of the present invention to provide such a TFT.
【００１１】[0011]
【課題を解決するための手段】すなわち本発明は、半導
体活性層が、それぞれ異なる禁制帯幅を有する第１絶縁
膜及びその外側に形成された第２絶縁膜の少なくとも２
層からなる一対の絶縁膜間に挟持されたＴＦＴであっ
て、該第１絶縁膜が該第２絶縁膜より広い禁制帯幅を有
することを特徴とするＴＦＴである。That is, according to the present invention, the semiconductor active layer has at least two of a first insulating film having a different forbidden band width and a second insulating film formed outside thereof.
A TFT sandwiched between a pair of insulating films made of layers, wherein the first insulating film has a wider band gap than the second insulating film.
【００１２】本発明において、前記第１絶縁膜は、膜厚
が薄い程、伝導電子や正孔の発生を少なくできるので好
ましい。しかしながら、膜厚が１ｎｍ未満の場合には絶
縁膜の均一性を得にくくなる。このため、前記第１絶縁
膜の膜厚は１ｎｍ以上とするのが好ましい。また、前記
第１絶縁膜は、その膜厚を絶縁膜全体の膜厚の１／４以
下とするのが好ましい。このような前記第１絶縁膜とし
ては、例えばＳｉＯ2、Ａｌ2Ｏ3等の禁制帯幅の広い絶
縁物を用いることができる。なお、前記絶縁膜が２層か
らなる場合、第２絶縁膜は半導体活性層と反対側に設け
られる。In the present invention, it is preferable that the first insulating film has a smaller film thickness because the generation of conduction electrons and holes can be reduced. However, if the film thickness is less than 1 nm, it becomes difficult to obtain uniformity of the insulating film. Therefore, the thickness of the first insulating film is preferably 1 nm or more. Further, it is preferable that the film thickness of the first insulating film is ¼ or less of the film thickness of the entire insulating film. As such a first insulating film, an insulator having a wide band gap such as SiO 2 or Al 2 O 3 can be used. When the insulating film has two layers, the second insulating film is provided on the side opposite to the semiconductor active layer.
【００１３】また、第１絶縁膜と半導体活性層の間に良
好な絶縁膜界面状態を得るため、前記第１絶縁膜と前記
半導体活性層間に第３絶縁膜を設けることもできる。こ
の場合、前記第３絶縁膜の膜厚は前記絶縁膜全体の膜厚
の１／４以下とするのが好ましく、薄くすることで伝導
電子や正孔の発生をより少なくすることができる。ま
た、従来より非晶質シリコン膜（ＳｉＯ2）と非晶質窒
化珪素膜（Ｓｉ3Ｎ4）間においては良好な界面を得られ
ることが知られている。このため、本発明において前記
半導体活性層として非晶質シリコン膜（ＳｉＯ2）を用
いた場合には、第３絶縁膜として窒化珪素膜（Ｓｉ
3Ｎ4）を用いることが好ましい。Further, in order to obtain a good insulating film interface state between the first insulating film and the semiconductor active layer, a third insulating film may be provided between the first insulating film and the semiconductor active layer. In this case, it is preferable that the film thickness of the third insulating film is ¼ or less of the film thickness of the entire insulating film, and by making it thin, the generation of conduction electrons and holes can be further reduced. Further, it has been conventionally known that a good interface can be obtained between an amorphous silicon film (SiO 2 ) and an amorphous silicon nitride film (Si 3 N 4 ). Therefore, when an amorphous silicon film (SiO 2 ) is used as the semiconductor active layer in the present invention, a silicon nitride film (Si) is used as the third insulating film.
3 N 4 ) is preferably used.
【００１４】また、前記第２絶縁膜の外側に任意の禁制
帯幅を有する第４絶縁膜を設けることも可能である。It is also possible to provide a fourth insulating film having an arbitrary band gap outside the second insulating film.
【００１５】以下に、代表的な絶縁物の禁制帯幅を挙げ
る。（単位：ｅＶ） ＳｉＯ2 ； ８．０ ＳｒＯ ； ５．８ Ｃ（ダイヤモンド）； ５．４７ Ａｌ2Ｏ3 ； ＞５．０ Ｓｉ3Ｎ4 ； ５．０ Ｇａ2Ｏ3 ； ４．４ ＧａＮ ； ３．４ ＺｎＯ ； ３．２ ＴｉＯ2 ； ３．０ また、各絶縁膜の層構成の組み合わせを例示する。The forbidden band widths of typical insulators are listed below. (Unit: eV) SiO 2 ; 8.0 SrO; 5.8 C (diamond); 5.47 Al 2 O 3 ;> 5.0 Si 3 N 4 ; 5.0 Ga 2 O 3 ; 4.4 GaN 3.4 ZnO; 3.2 TiO 2 ; 3.0 Moreover, the combination of the layer constitution of each insulating film is illustrated.
【００１６】[0016]
【表１】 [Table 1]
【００１７】[0017]
【作用】本発明のＴＦＴは、禁制帯幅の異なる少なくと
も２層からなる絶縁膜で半導体活性層を挟んでおり、該
絶縁膜のうち半導体活性層に近い層が広い禁制帯幅を有
しているので、高エネルギー粒子によって絶縁膜中に生
じた伝導電子や正孔が半導体活性層側に拡散することを
確実に防止し、高エネルギー粒子照射によるＴＦＴ特性
へ及ぼす悪影響を低減することができる。In the TFT of the present invention, the semiconductor active layer is sandwiched between the insulating films composed of at least two layers having different forbidden band widths, and the layer near the semiconductor active layer has a wide forbidden band width. Therefore, it is possible to reliably prevent conduction electrons and holes generated in the insulating film by the high-energy particles from diffusing to the semiconductor active layer side, and reduce the adverse effect of the high-energy particle irradiation on the TFT characteristics.
【００１８】[0018]
【実施例】 （実施例１）ガラス基板（１）上に厚さ５０ｎｍのＣｒ
をスパッタリング法により成膜し、パターニングしてゲ
ート電極（２）を形成し（図３（ａ））、その上に厚さ
５００ｎｍの非晶質窒化珪素（Ｓｉ3Ｎ4）膜のゲート絶
縁膜（第２絶縁膜）（３）、前記ゲート絶縁膜（第２絶
縁膜）（３）より禁制帯幅が広く、厚さ１０ｎｍの非晶
質二酸化珪素（ＳｉＯ2）膜の第１絶縁膜（１１）をス
パッタリング法で形成し、さらに前記第１絶縁膜（１
１）より禁制帯幅が狭く、厚さ１０ｎｍの非晶質窒化珪
素（Ｓｉ3Ｎ4）膜の第３絶縁膜（１２）、厚さ１００ｎ
ｍの非晶質珪素（Ｓｉ）膜の半導体活性層（４）、厚さ
２０ｎｍのリン添加非晶質珪素膜をプラズマＣＶＤ法で
成膜した。さらに、厚さ３００ｎｍのＣｒをスパッタリ
ング法で成膜した（同図（ｂ））。その後、前記Ｃｒ膜
をパターニングし、さらに前記リン添加非晶質珪素膜を
エッチングしてソース・ドレイン層（６）とオーミック
コンタクト層（５）とを形成した（同図（ｃ））。Example 1 Example 1 Cr having a thickness of 50 nm was formed on a glass substrate (1).
Is formed by sputtering and patterned to form a gate electrode (2) (FIG. 3A), and a gate insulating film of an amorphous silicon nitride (Si 3 N 4 ) film having a thickness of 500 nm is formed thereon. (Second insulating film) (3), first insulating film of amorphous silicon dioxide (SiO 2 ) film having a band gap wider than the gate insulating film (second insulating film) (3) and a thickness of 10 nm ( 11) is formed by a sputtering method, and the first insulating film (1
A third insulating film (12) of amorphous silicon nitride (Si 3 N 4 ) film having a narrower band gap than that of 1) and a thickness of 10 nm, and a thickness of 100 n
A semiconductor active layer (4) of m amorphous silicon (Si) film, and a phosphorus-doped amorphous silicon film having a thickness of 20 nm were formed by plasma CVD. Further, a 300 nm-thick Cr film was formed by a sputtering method (the same figure (b)). After that, the Cr film was patterned, and the phosphorus-added amorphous silicon film was further etched to form a source / drain layer (6) and an ohmic contact layer (5) (FIG. 7C).
【００１９】次に、厚さ１０ｎｍの非晶質窒化珪素（Ｓ
ｉ3Ｎ4）膜、厚さ１０ｎｍの非晶質二酸化珪素（ＳｉＯ
2）膜、厚さ５００ｎｍの非晶質窒化珪素（Ｓｉ3Ｎ4）
膜を、前記ソース・ドレイン層（６）と露出している半
導体活性層（４）上にプラズマＣＶＤ法で連続成膜した
（同図（ｄ））。その後、保護絶縁層（第２絶縁膜）
（７）、第１絶縁膜（１４）、第３絶縁膜（１３）の３
層からなる保護絶縁膜をパターニングし、最後にＡｌ膜
をスパッタリング法で成膜し、前記Ａｌ膜をパターニン
グしてバックゲート電極（８）及びソース・ドレイン配
線（９）を形成した（同図（ｅ））。Next, amorphous silicon nitride (S
i 3 N 4 ) film, amorphous silicon dioxide (SiO 2 ) with a thickness of 10 nm
2 ) Film, amorphous silicon nitride (Si 3 N 4 ) with a thickness of 500 nm
A film was continuously formed on the semiconductor active layer (4) exposed from the source / drain layer (6) by a plasma CVD method (FIG. 7 (d)). After that, a protective insulating layer (second insulating film)
(7), the first insulating film (14), the third insulating film (13) 3
The protective insulating film consisting of layers is patterned, and finally an Al film is formed by a sputtering method, and the Al film is patterned to form a back gate electrode (8) and source / drain wirings (9). e)).
【００２０】このように形成したＴＦＴを図１に示す。
また、図１のＴＦＴのフラットバンド状態を図２のエネ
ルギーバンド図で説明する。図２において、（２Ａ）は
保護絶縁層であって第２絶縁膜（２２），第１絶縁膜
（２５）及び第３絶縁膜（２６）の３層からなる。ま
た、（２Ｂ）はゲート絶縁層であって第２絶縁膜（２
３），第３絶縁膜（２７）及び第１絶縁膜（２８）の３
層からなる。さらに、（２１）はバックゲート電極、
（２９）は半導体活性層、（２４）はゲート電極、（３
１）は正孔、（３２）は伝導電子、そして（３３）はエ
ネルギーｈνを有する高エネルギー粒子である。The TFT thus formed is shown in FIG.
The flat band state of the TFT of FIG. 1 will be described with reference to the energy band diagram of FIG. In FIG. 2, (2A) is a protective insulating layer and is composed of three layers of a second insulating film (22), a first insulating film (25) and a third insulating film (26). Further, (2B) is a gate insulating layer which is the second insulating film (2B).
3), the third insulating film (27) and the first insulating film (28) 3
Consists of layers. Further, (21) is a back gate electrode,
(29) is a semiconductor active layer, (24) is a gate electrode, (3)
1) is a hole, (32) is a conduction electron, and (33) is a high energy particle having an energy hν.
【００２１】外部からＴＦＴにエネルギーｈνを及ぼす
と、第２絶縁膜（２２），（２３）において伝導電子
（３２）及び正孔（３１）は、それぞれ半導体活性層
（２９）に向かって拡散しようとするが、禁制帯幅の広
い第１絶縁膜（２５），（２８）の存在により拡散する
ことができない。When the energy hν is applied to the TFT from the outside, the conduction electrons (32) and the holes (31) in the second insulating films (22) and (23) respectively diffuse toward the semiconductor active layer (29). However, it cannot diffuse due to the existence of the first insulating films (25) and (28) having a wide band gap.
【００２２】一方、第１絶縁膜（２５），（２８）及び
第３絶縁膜（２６），（２７）において発生した電子−
正孔対は、拡散して半導体活性層（２９）の伝導帯に達
することができる。しかしながら、実際には第１絶縁膜
（２５），（２８）及び第３絶縁膜（２６），（２７）
の膜厚は、第２絶縁膜（２２），（２３）の膜厚に比較
して非常に小さいので、高エネルギー粒子（３３）によ
って発生した伝導電子（３２）及び正孔（３１）の大部
分が半導体活性層（２９）に向かって拡散せず、この結
果高エネルギー粒子（３３）の照射によるＯＦＦ状態時
の電流増加を抑制することができる。On the other hand, electrons generated in the first insulating films (25) and (28) and the third insulating films (26) and (27)-
The hole pairs can diffuse and reach the conduction band of the semiconductor active layer (29). However, in reality, the first insulating films (25), (28) and the third insulating films (26), (27)
Since the film thickness of is much smaller than the film thickness of the second insulating films (22) and (23), the large number of conduction electrons (32) and holes (31) generated by the high-energy particles (33). The portion does not diffuse toward the semiconductor active layer (29), and as a result, it is possible to suppress an increase in current in the OFF state due to irradiation of the high energy particles (33).
【００２３】なお、本実施例ではボトムゲート／バック
エッチ型ＴＦＴについて説明したが、これに限定される
ものではない。Although the bottom gate / back etch type TFT has been described in this embodiment, the present invention is not limited to this.
【００２４】また、第２絶縁膜（３），（７）／第１絶
縁膜（１１），（１４）／第３絶縁膜（１２），（１
３）の積層構成材料の組み合わせは、第１絶縁膜（１
１），（１４）を構成する絶縁物の禁制帯幅が第２絶縁
膜（３），（７）及び第３絶縁膜（１２），（１３）を
構成する絶縁物の禁制帯幅より広い（数値の大きい）絶
縁材料であれば、本実施例のＳｉ3Ｎ4膜（第２絶縁膜
（３），（７））／ＳｉＯ2膜（第１絶縁膜（１１），
（１４））／Ｓｉ3Ｎ4膜（第３絶縁膜（１２），（１
３））の組み合わせに限定されることなく種々選択可能
である。 （実施例２）実施例１の場合と同様に、ガラス基板
（１）上に厚さ５０ｎｍのＣｒをスパッタリングにより
成膜し、パターニングしてゲート電極（２）を形成し、
その上に厚さ５００ｎｍの非晶質二酸化珪素（Ｓｉ
Ｏ2）膜のゲート絶縁膜（第２絶縁膜）（３）、前記ゲ
ート絶縁層（第２絶縁膜）（３）より禁制帯幅が狭く、
厚さ１０ｎｍの非晶質窒化珪素（Ｓｉ3Ｎ4）膜の第４絶
縁膜（５１）、前記第４絶縁膜（５１）より禁制帯幅が
広く、厚さ１０ｎｍの非晶質二酸化珪素（ＳｉＯ2）膜
の第１絶縁膜（５２）、厚さ１００ｎｍの非晶質珪素
（Ｓｉ）膜の半導体活性層（４）、厚さ２０ｎｍのリン
添加非晶質珪素膜及び厚さ３００ｎｍのＣｒ膜をスパッ
タリング法で連続成膜した。その後、前記Ｃｒ膜をパタ
ーニングし、さらに前記リン添加非晶質珪素膜をエッチ
ングしてソース・ドレイン層（６）とオーミックコンタ
クト層（５）とを形成した。The second insulating films (3), (7) / first insulating films (11), (14) / third insulating films (12), (1
The combination of the laminated constituent materials of 3) is the same as the first insulating film (1
The forbidden band width of the insulators forming 1) and (14) is wider than the forbidden band width of the insulators forming the second insulating films (3) and (7) and the third insulating films (12) and (13). If it is an insulating material (having a large numerical value), the Si 3 N 4 film (second insulating film (3), (7)) / SiO 2 film (first insulating film (11),
(14)) / Si 3 N 4 film (third insulating film (12), (1
Various combinations are possible without being limited to the combination of 3)). (Example 2) As in the case of Example 1, a 50 nm thick Cr film was formed on the glass substrate (1) by sputtering and patterned to form a gate electrode (2).
On top of that, 500 nm thick amorphous silicon dioxide (Si
The gate insulating film (second insulating film) (3) of the O 2 ) film has a narrower band gap than the gate insulating layer (second insulating film) (3),
A fourth insulating film (51) made of an amorphous silicon nitride (Si 3 N 4 ) film having a thickness of 10 nm, and an amorphous silicon dioxide (10 nm thick having a wider band gap than the fourth insulating film (51). First insulating film (52) of SiO 2 ) film, semiconductor active layer (4) of amorphous silicon (Si) film of 100 nm thickness, phosphorus-doped amorphous silicon film of 20 nm thickness and Cr of 300 nm thickness The film was continuously formed by a sputtering method. Then, the Cr film was patterned, and the phosphorus-added amorphous silicon film was further etched to form a source / drain layer (6) and an ohmic contact layer (5).
【００２５】次に、厚さ１０ｎｍの非晶質二酸化珪素
（ＳｉＯ2）膜、厚さ１０ｎｍの非晶質窒化珪素（Ｓｉ3
Ｎ4）膜、厚さ５００ｎｍの非晶質二酸化珪素（Ｓｉ
Ｏ2）膜を前記ソース・ドレイン層（６）と露出してい
る半導体活性層（４）上にスパッタリング法で連続成膜
した。その後、保護絶縁膜（第２絶縁膜）（７）、第１
絶縁膜（５３）、第４絶縁膜（５４）の３層からなる保
護絶縁膜をパターニングし、最後にＡｌ膜をスパッタリ
ング法で成膜し、前記Ａｌ膜をパターニングしてバック
ゲート電極（８）及びソース・ドレイン配線（９）を形
成して図４に示すＴＦＴを得た。なお、本実施例におい
ては、第３絶縁膜を設けなかった。Next, a 10 nm thick amorphous silicon dioxide (SiO 2 ) film and a 10 nm thick amorphous silicon nitride (Si 3
N 4 ) film, 500 nm thick amorphous silicon dioxide (Si
An O 2 ) film was continuously formed on the source / drain layer (6) and the exposed semiconductor active layer (4) by a sputtering method. Then, the protective insulating film (second insulating film) (7), the first
The protective insulating film consisting of three layers of the insulating film (53) and the fourth insulating film (54) is patterned, and finally the Al film is formed by the sputtering method, and the Al film is patterned to form the back gate electrode (8). Then, the source / drain wiring (9) was formed to obtain the TFT shown in FIG. In this example, the third insulating film was not provided.
【００２６】また、図４のＴＦＴのフラットバンド状態
を図５のエネルギーバンド図で説明する。図５におい
て、（６Ａ）は保護絶縁層であって第２絶縁膜（６
２），第４絶縁膜（６５）及び第１絶縁膜（６６）の３
層からなる。また、（６Ｂ）はゲート絶縁層であって第
２絶縁膜（６３），第４絶縁膜（６８）及び第１絶縁膜
（６７）の３層からなる。さらに、（６１）はバックゲ
ート電極、（６９）は半導体活性層、（６４）はゲート
電極、（７１）は正孔、（７２）は伝導電子、そして
（７３）は高エネルギー粒子である。The flat band state of the TFT of FIG. 4 will be described with reference to the energy band diagram of FIG. In FIG. 5, (6A) is a protective insulating layer and is the second insulating film (6
2), 3rd of 4th insulating film (65) and 1st insulating film (66)
Consists of layers. Further, (6B) is a gate insulating layer and is composed of three layers of a second insulating film (63), a fourth insulating film (68) and a first insulating film (67). Further, (61) is a back gate electrode, (69) is a semiconductor active layer, (64) is a gate electrode, (71) is a hole, (72) is a conduction electron, and (73) is a high energy particle.
【００２７】外部からＴＦＴに高エネルギー粒子（７
３）のエネルギーｈνを及ぼすと、第２絶縁膜（６
２），（６３）において伝導電子（７２）及び正孔（７
１）は、それぞれ半導体活性層（６９）に向かって拡散
しようとするが、禁制帯幅の狭い第４絶縁膜（６５），
（６８）に捕まり拡散することができない。High energy particles (7
When the energy hν of 3) is exerted, the second insulating film (6
2) and (63), conduction electrons (72) and holes (7)
1) tries to diffuse toward the semiconductor active layer 69, but has a narrow forbidden band width of the fourth insulating film 65,
It cannot be diffused by being caught by (68).
【００２８】一方、第１絶縁膜（６６），（６７）にお
いて発生した電子−正孔対は、拡散して半導体活性層
（６９）の伝導帯に達することができる。On the other hand, the electron-hole pairs generated in the first insulating films (66) and (67) can diffuse and reach the conduction band of the semiconductor active layer (69).
【００２９】しかしながら、実際には第１絶縁膜（６
６），（６７）の膜厚は保護絶縁層（６Ａ），（６Ｂ）
の膜厚に比較して非常に小さいので、高エネルギー粒子
（７３）によって発生した伝導電子（７２）及び正孔
（７１）の大部分は半導体活性層（６９）に向かって拡
散せず、この結果高エネルギー粒子（７３）の照射によ
るＯＦＦ状態時の電流増加を抑制することができる。However, in practice, the first insulating film (6
The film thicknesses of 6) and (67) are the protective insulating layers (6A) and (6B).
Since it is very small compared with the film thickness of, the majority of conduction electrons (72) and holes (71) generated by the energetic particles (73) do not diffuse toward the semiconductor active layer (69). As a result, it is possible to suppress an increase in current in the OFF state due to the irradiation of the high energy particles (73).
【００３０】なお、本実施例においてもボトムゲート／
バックエッチ型ＴＦＴについて説明したが、これに限定
されるものではない。Note that the bottom gate /
Although the back-etch type TFT has been described, the present invention is not limited to this.
【００３１】また、第２絶縁膜（３），（７）／第４絶
縁膜（５１），（５４）／第１絶縁膜（５２），（５
３）の積層構成材料の組み合わせは、第４絶縁膜（５
１），（５４）を構成する絶縁物の禁制帯幅が第１絶縁
膜（５２），（５３）及び第２絶縁膜（３），（７）を
構成する絶縁物の禁制帯幅より狭い（数値の小さい）絶
縁材料であれば、本実施例のＳｉＯ2膜（第２絶縁膜
（３），（７））／Ｓｉ3Ｎ4膜（第４絶縁膜（５１），
（５４））／ＳｉＯ2膜（第１絶縁膜（５２），（５
３））の組み合わせに限定されることなく種々選択可能
である。The second insulating films (3), (7) / the fourth insulating films (51), (54) / the first insulating films (52), (5)
The combination of the laminated constituent materials of 3) is the fourth insulating film (5
The forbidden band width of the insulating material that forms the first insulating film (54) is narrower than that of the insulating material that forms the first insulating films (52) and (53) and the second insulating films (3) and (7). If it is an insulating material (having a small numerical value), the SiO 2 film (second insulating film (3), (7)) / Si 3 N 4 film (fourth insulating film (51),
(54)) / SiO 2 film (first insulating film (52), (5
Various combinations are possible without being limited to the combination of 3)).
【００３２】[0032]
【発明の効果】以上説明したように、本発明のＴＦＴ
は、半導体活性層以外の部分において高エネルギー粒子
により発生した伝導電子や正孔（キャリア）が半導体活
性層側に拡散することを防止し、高エネルギー粒子照射
によるＴＦＴ特性へ及ぼす悪影響を低減することができ
る。As described above, the TFT of the present invention
Is to prevent conduction electrons and holes (carriers) generated by high-energy particles in the portion other than the semiconductor active layer from diffusing to the semiconductor active layer side, and reduce adverse effects on TFT characteristics due to high-energy particle irradiation. You can
【図１】本発明の第１実施例の断面図FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】本発明の第１実施例におけるフラットバンド状
態のエネルギーバンド図FIG. 2 is an energy band diagram of a flat band state in the first embodiment of the present invention.
【図３】本発明の第１実施例の概略工程図FIG. 3 is a schematic process diagram of the first embodiment of the present invention.
【図４】本発明の第２実施例の断面図FIG. 4 is a sectional view of a second embodiment of the present invention.
【図５】本発明の第２実施例におけるフラットバンド状
態のエネルギーバンド図FIG. 5 is an energy band diagram of a flat band state in the second embodiment of the present invention.
【図６】従来のボトムゲート型／バックエッチ型ＴＦＴ
の断面図FIG. 6 Conventional bottom gate type / back etch type TFT
Cross section of
【図７】従来のボトムゲート型／バック絶縁膜型ＴＦＴ
の断面図FIG. 7 Conventional bottom gate type / back insulating film type TFT
Cross section of
【図８】従来のトップゲート型ＴＦＴの断面図FIG. 8 is a sectional view of a conventional top gate type TFT.
【図９】Ｘ線照射によるＴＦＴのゲート電圧に対するソ
ース・ドレイン電流の変化を示す図FIG. 9 is a diagram showing changes in source / drain current with respect to a gate voltage of a TFT due to X-ray irradiation.
【図１０】Ｘ線照射によるＴＦＴのフラットバンド状態
のエネルギーバンド図FIG. 10 is an energy band diagram of a flat band state of TFT by X-ray irradiation.
１ 絶縁基板 ２ ゲート電極 ３ ゲート絶縁層 ４ 半導体活性層 ５ オーミックコンタクト層 ６ ソース・ドレイン層 ７ 保護絶縁層 ８ バックゲート電極 ９ ソースドレイン配線 １１ 第１絶縁膜 １２ 第３絶縁膜 １３ 第３絶縁膜 １４ 第１絶縁膜 1 Insulating Substrate 2 Gate Electrode 3 Gate Insulating Layer 4 Semiconductor Active Layer 5 Ohmic Contact Layer 6 Source / Drain Layer 7 Protective Insulating Layer 8 Back Gate Electrode 9 Source / Drain Wiring 11 First Insulating Film 12 Third Insulating Film 13 Third Insulating Film 14 First insulating film
Claims (3)
幅を有する第１絶縁膜及びその外側に形成された第２絶
縁膜の少なくとも２層からなる一対の絶縁膜間に挟持さ
れた薄膜トランジスタであって、該第１絶縁膜が該第２
絶縁膜より広い禁制帯幅を有することを特徴とする薄膜
トランジスタ。1. A thin film transistor in which a semiconductor active layer is sandwiched between a pair of insulating films composed of at least two layers of a first insulating film having different forbidden band widths and a second insulating film formed outside thereof. The first insulating film is
A thin film transistor having a wider band gap than an insulating film.
り、しかも該第１絶縁膜の膜厚が前記絶縁膜全体の膜厚
の１／４以下である請求項１記載の薄膜トランジスタ。2. The thin film transistor according to claim 1, wherein the film thickness of the first insulating film is 1 nm or more, and the film thickness of the first insulating film is 1/4 or less of the film thickness of the entire insulating film.
の膜厚が前記絶縁膜全体の膜厚の１／４以下である第３
絶縁膜が、前記半導体活性層と前記第１絶縁膜との間に
形成されている請求項１記載の薄膜トランジスタ。3. The forbidden band width is narrower than that of the first insulating film, and the film thickness thereof is ¼ or less of the film thickness of the entire insulating film.
The thin film transistor according to claim 1, wherein an insulating film is formed between the semiconductor active layer and the first insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4295763A JPH06151850A (en) | 1992-11-05 | 1992-11-05 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4295763A JPH06151850A (en) | 1992-11-05 | 1992-11-05 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151850A true JPH06151850A (en) | 1994-05-31 |
Family
ID=17824855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4295763A Pending JPH06151850A (en) | 1992-11-05 | 1992-11-05 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151850A (en) |
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|---|---|---|---|---|
| JP2004363320A (en) * | 2003-06-04 | 2004-12-24 | Sharp Corp | Oxide semiconductor light emitting element |
| JP2008166716A (en) * | 2006-12-05 | 2008-07-17 | Canon Inc | Bottom gate type thin film transistor, manufacturing method of the same, and display device |
| JP2011228689A (en) * | 2010-04-02 | 2011-11-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| CN102593164A (en) * | 2011-01-12 | 2012-07-18 | 索尼公司 | Radiation imaging device, radiation imaging display system, and transistor |
| JP2018164106A (en) * | 2010-04-02 | 2018-10-18 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
1992
- 1992-11-05 JP JP4295763A patent/JPH06151850A/en active Pending
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| JP2004363320A (en) * | 2003-06-04 | 2004-12-24 | Sharp Corp | Oxide semiconductor light emitting element |
| US10714627B2 (en) | 2006-12-05 | 2020-07-14 | Canon Kabushiki Kaisha | Bottom gate type thin film transistor, method of manufacturing the same, and display apparatus |
| US9905699B2 (en) | 2006-12-05 | 2018-02-27 | Canon Kabushiki Kaisha | Thin film transistor, method of manufacturing the same, and display apparatus |
| JP2008166716A (en) * | 2006-12-05 | 2008-07-17 | Canon Inc | Bottom gate type thin film transistor, manufacturing method of the same, and display device |
| JP2018164106A (en) * | 2010-04-02 | 2018-10-18 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US9059295B2 (en) | 2010-04-02 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor having an oxide semiconductor and metal oxide films |
| JP2016184746A (en) * | 2010-04-02 | 2016-10-20 | 株式会社半導体エネルギー研究所 | Manufacturing method for semiconductor device |
| JP2011228689A (en) * | 2010-04-02 | 2011-11-10 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US9842937B2 (en) | 2010-04-02 | 2017-12-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having an oxide semiconductor film and a metal oxide film |
| US10608116B2 (en) | 2010-04-02 | 2020-03-31 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US10714626B2 (en) | 2010-04-02 | 2020-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US11380800B2 (en) | 2010-04-02 | 2022-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US11411121B2 (en) | 2010-04-02 | 2022-08-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| US12119406B2 (en) | 2010-04-02 | 2024-10-15 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP2012146805A (en) * | 2011-01-12 | 2012-08-02 | Sony Corp | Radiation imaging apparatus, radiation imaging display system and transistor |
| CN102593164A (en) * | 2011-01-12 | 2012-07-18 | 索尼公司 | Radiation imaging device, radiation imaging display system, and transistor |
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