JPH06151750A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory device which is suitable for an enhancement in degree of integration and wherein a capacitor is enhanced in capacity and a leakage current is prevented from flowing between the adjacent memory elements and a manufacturing device thereof. CONSTITUTION:A high melting point metal film 6 is formed on an impurity- doped diffusion layer 4 which serves as a source or a drain through a chemical vapor deposition method under prescribed conditions, whereby the surface of the metal film 6 becomes rugged. The high melting point metal film 6 is made to serve as a capacitor electrode of a capacitor which composes a memory element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRA).
The present invention relates to a structure capable of improving the capacitance of a capacitor due to the miniaturization of M) and a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have grown rapidly due to the remarkable spread of information equipment such as computers. Further, functionally, it is required to have a large-scale storage capacity and be capable of high-speed operation.
Along with this, technological developments relating to high integration and high-speed response or high reliability of semiconductor memory devices are being advanced.

The structure of a memory element of a conventional DRAM will be described below with reference to the drawings. FIG. 10 is a sectional structural view of a memory element of a conventional DRAM. A MOS (Metal Oxide Semiconducto) is formed on the silicon substrate 1 which is a p-type conductive layer.
r) Two diffusion layers 4 serving as the source or drain of the transistor are formed, and the region sandwiched between the two diffusion layers 4 serves as a channel portion in which carriers flow. Form a thin silicon oxide film to be an insulating film on the surface of this channel part,
One MOS transistor is formed by forming the gate electrode 3 serving as the gate of the MOS transistor on it. The gate electrode 3 is a conductive layer containing a polycrystalline silicon film containing phosphorus or arsenic, and the diffusion layer 4 is an n-type conductive layer containing phosphorus or arsenic as an impurity.

Next, on one of the two diffusion layers 4, a first capacitor electrode 11 serving as a capacitor electrode is formed.
Is formed, the capacitor insulating film 7 is formed on the first capacitor electrode 11, and the second capacitor electrode 8 is further formed thereon, thereby forming one capacitor and The diffusion layer 4 and the first capacitor electrode 11 of the capacitor are electrically connected. The first capacitor electrode 11 and the second capacitor electrode 8 are polycrystalline silicon films containing phosphorus or arsenic, and the capacitor insulating film 7 is a silicon oxide film or a composite film of a silicon nitride film and a silicon oxide film.

With the above structure, a storage element of a DRAM is constructed in which one charge input / output control MOS transistor and one charge storage capacitor are connected in series, and information is stored as the charge stored in the capacitor. .

Next, a method of manufacturing a memory element of a conventional DRAM will be described with reference to the drawings. First, as shown in FIG. 11, a thick silicon oxide film 2 for electrically separating adjacent memory elements is locally formed on a silicon substrate 1, and then a MOS is formed.
A gate electrode 3 of the transistor and a diffusion layer 4 serving as a source or a drain are formed. Here, the silicon substrate 1 is a p-type conductive layer, the diffusion layer 4 is an n-type conductive layer using phosphorus or arsenic as an impurity, and the gate electrode 3 is a conductive layer in which a polycrystalline silicon film contains phosphorus or arsenic. Is.

Next, as shown in FIG. 12, a thin silicon oxide film 5 is formed on the entire surface of the substrate and processed so that a part of the surface of the diffusion layer 4 is exposed.

Next, as shown in FIG. 13, a first capacitor electrode 11 made of a polycrystalline silicon film containing phosphorus or arsenic is formed and processed into a desired pattern. Here, the first capacitor electrode 11 is electrically connected to one side of the diffusion layer 4 serving as the source or drain of the MOS transistor and serves as an electrode on one side of the capacitor.

Next, as shown in FIG. 14, a capacitor insulating film 7 is formed on the entire surface of the substrate. Usually, the capacitor insulating film 7 is made of a silicon oxide film or a composite film of a silicon nitride film and a silicon oxide film, and is formed by a chemical vapor deposition method. However, thermal diffusion is performed at a high temperature of several hundred degrees or more. As a result, phosphorus or arsenic contained in the first capacitor electrode 11 passes through the diffusion layer 4 and diffuses into the silicon substrate 1 to form a deep diffusion layer 12.

Finally, a second capacitor electrode 8 made of a polycrystalline silicon film containing phosphorus or arsenic is formed on the substrate.

Through the above steps, the DRAM shown in FIG.
Storage element is manufactured.

[0012]

In order to further increase the integration of the conventional semiconductor memory device configured as described above, it is necessary to miniaturize each memory element and miniaturize the capacitor section. . The miniaturization of the capacitor portion reduces the surface area of the capacitor electrode and reduces the capacitance of the capacitor.
As a result, the operation of the memory element becomes unstable, the reliability of the semiconductor memory device is deteriorated, and it is difficult to realize higher integration.

When the distance between the memory elements is narrowed to achieve high integration, the width S of the thick silicon oxide film 2 which electrically separates the memory elements becomes small as shown in FIG. On the other hand, in the conventional method for manufacturing a semiconductor memory device, since the capacitor insulating film 7 is formed by the chemical vapor deposition method at high temperature, phosphorus or arsenic contained in the first capacitor electrode is diffused into the diffusion layer 4 by thermal diffusion. Through the silicon substrate 1, and a deep diffusion layer 12 is formed. Therefore, when the width S of the thick silicon oxide film 2 becomes narrow, the leak current flows through the deep diffusion layer 12 to the adjacent memory element. As a result, the memory element malfunctions, which deteriorates the reliability of the semiconductor memory device, and it is difficult to achieve higher integration.

An object of the present invention is to provide a semiconductor memory device which can increase the capacitance of a capacitor and can be further miniaturized.

Another object of the present invention is to provide a method of manufacturing a semiconductor memory device capable of improving the insulation reliability of adjacent memory elements.

[0016]

According to another aspect of the present invention, there is provided a semiconductor memory device comprising: a first conductivity type semiconductor substrate having a main surface;
Between the first impurity region and the second impurity region of the second conductivity type different from the first conductivity type and formed on the main surface with a space therebetween, and between the first impurity region and the second impurity region. A conductive layer formed on the main surface with an insulating film sandwiched between the conductive layer and a first impurity region or a second impurity region in contact therewith, and a first refractory metal having an uneven surface. It includes a capacitor electrode, an insulating layer formed on the surface of the first capacitor electrode, and a second capacitor electrode formed on the insulating layer.

A semiconductor memory device according to a second aspect is the first aspect.
And further includes a silicide layer between the first capacitor electrode and the first impurity region or the second impurity region.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device comprising: a first conductivity type semiconductor substrate; Two
A step of forming a conductive layer sandwiching an insulating film on the main surface between the first impurity region and the second impurity region, and a high melting point having an uneven surface. A step of forming a first capacitor electrode made of metal by connecting it to the first impurity region or the second impurity region; a step of forming an insulating layer on the surface of the first capacitor electrode; Forming a second capacitor electrode on the surface of the layer.

A method of manufacturing a semiconductor memory device according to a fourth aspect is dependent on the third aspect, and the refractory metal fluoride and SiO ₄ or H ₂ are used in the step of forming the first capacitor electrode.
And a step of forming the first capacitor electrode by a chemical vapor deposition method using a mixed gas of.

[0020]

In the semiconductor memory device according to claim 1,
Since the uneven shape is formed on the surface of the first capacitor electrode, it is possible to effectively increase the surface area that acts as the electrode of the capacitor and increase the capacitance of the capacitor.

In the semiconductor memory device according to the second aspect, since the silicide layer is provided between the first capacitor electrode and the first impurity region or the second impurity region, the first capacitor electrode is used. Reaction of a certain refractory metal with the first impurity region or the second impurity region is suppressed, and a stable capacitor electrode is formed.

In the method of manufacturing a semiconductor memory device according to the third aspect, since the first capacitor electrode made of a refractory metal containing no phosphorus or arsenic as an impurity is formed, a number of electrodes are formed on the first capacitor electrode. Even if the insulating layer is formed by chemical vapor deposition at a high temperature of 100 degrees Celsius, phosphorus or arsenic does not diffuse from the first capacitor electrode due to thermal diffusion, and the first capacitor under the first capacitor electrode does not diffuse. No deep diffusion layer is formed below the impurity region or the second impurity region.

In the method of manufacturing the semiconductor memory device according to the fourth aspect, the uneven shape can be formed on the surface of the first capacitor electrode at the same time as growing the first capacitor electrode by the chemical vapor deposition method.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a memory element of a DRAM according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional structural view of a memory element of a DRAM according to an embodiment of the present invention. Two diffusion layers 4 serving as a source or a drain of a MOS transistor are formed on the upper layer of the silicon substrate 1 which is a p-type conductive layer, and a region sandwiched between the two diffusion layers 4 becomes a channel part in which carriers flow. A thin silicon oxide film to serve as an insulating layer is formed on the surface of the channel portion, and a gate electrode 3 to serve as the gate of the MOS transistor is formed thereon, thereby forming one MOS transistor. The gate electrode 3 is a conductive layer containing a polycrystalline silicon film containing phosphorus or arsenic, and the diffusion layer 4 is an n-type conductive layer containing phosphorus or arsenic as an impurity.

Then, on one of the two diffusion layers 4,
A refractory metal film 6 made of a tungsten film is formed as an electrode of the capacitor and electrically connected. The upper surface of the refractory metal film 6 has an uneven shape of several hundred liters, and has a surface area several times that of an ordinary smooth surface. A capacitor insulating film 7 is formed on the high melting point metal film 6, and the surface thereof has a shape that follows the uneven shape of the high melting point metal film 6. The second capacitor electrode 8 is formed on the upper surface of the capacitor insulating film 7, and the shape of the lower surface is formed so as to follow the uneven shape of the capacitor insulating film 7. The capacitor insulating film 7 is made of a silicon oxide film or a composite film of a silicon nitride film and a silicon oxide film, and the second capacitor electrode 8 is made of a polycrystalline silicon film containing phosphorus or arsenic. One capacitor is formed from the two capacitor electrodes 8 and the capacitor insulating film 7 and functions as a DRAM having one transistor-1 capacitor as a storage element.

Since the surface area of the electrode portion of this capacitor is the same and has a surface area several times as large as that of the electrode surface having a smooth surface, the electric charge to be stored is increased and the capacitor capacity can be several times as large. Therefore, even if the size of the capacitor having a smooth surface electrode is reduced to a fraction of that of the capacitor, the same capacitor capacity can be secured, the operation of the memory element is stabilized, and the reliability of the DRAM can be improved.

Although the tungsten film is used as the refractory metal film 6 in the above embodiment, the same effect can be obtained by using another refractory metal film such as molybdenum.

Next, the manufacturing process of the memory element of the DRAM shown in FIG. 1 will be described with reference to FIGS.

First, as shown in FIG. 2, a thick silicon oxide film 2 is locally formed on a silicon substrate 1 having p-type conductivity, and adjacent memory elements are electrically isolated. Next, after forming the gate electrode 3 of the MOS transistor and the diffusion layer 4 serving as the source or the drain, the silicon oxide film 5 is formed on the entire surface of the substrate and patterned so as to expose a part of the upper surface of the diffusion layer 4. . After that, the refractory metal film 6 is formed by a chemical vapor deposition method, and is patterned into a desired shape by a photolithography process to form a first capacitor electrode joined to the MOS transistor.

Here, when the refractory metal film 6 is a tungsten film, it is 5 to 100 tons at a temperature of 400 to 500 ° C.
The pressure is reduced to rr and the flow rate of the mixed gas is set to WF ₆ (tungsten hexafluoride): H ₂ = 1: 10 or WH ₆ :
A tungsten film is formed under the growth conditions of SiH ₄ (silane) = 3: 2. Under this growth condition, the tungsten film is formed, and at the same time, an uneven shape is formed on the surface of the tungsten film, so that the surface area of the capacitor electrode can be increased.

Next, as shown in FIG. 3, a capacitor insulating film 7 composed of a silicon oxide film or a composite film of a silicon nitride film and a silicon oxide film is formed on the entire surface of the substrate by chemical vapor deposition at a high temperature of several hundreds of degrees. It is formed by the phase growth method. At this time, since the lower portion of the capacitor insulating film 7 is the refractory metal film 6 containing no phosphorus or arsenic, a deep diffusion layer is not formed below the diffusion layer 4 by thermal diffusion. Next, the second capacitor electrode 8 made of a polycrystalline silicon film containing phosphorus or arsenic is formed on the entire surface of the substrate.

Through the above steps, the DRAM having the 1-transistor-1 capacitor shown in FIG. 1 as a memory element is completed.

As a result, a new deep diffusion layer is not formed under the diffusion layer 4, and even if the space between the adjacent memory elements is narrowed, the leakage current can be suppressed from flowing and the reliability of the DRAM can be improved. it can. Further, by the chemical vapor deposition method, the step of forming the refractory metal film 6 and the step of forming the uneven shape on the surface can be performed in one step, and the manufacturing step can be simplified. ing.

In the above embodiment, the refractory metal film 6 is formed by the chemical vapor deposition method, but in the other steps as long as it is the step of forming the refractory metal film 6 containing no phosphorus or arsenic as an impurity. The same effect can be obtained.
Further, after forming the refractory metal film 6 by the chemical vapor deposition method, desired patterning was performed by the photolithography process. However, the growth conditions of the chemical vapor deposition method were changed to change the source or drain of the MOS transistor. By selectively growing the refractory metal film 6 only on the exposed portion of the diffusion layer 4 to be formed, the manufacturing process can be further simplified, and a margin for patterning in the photolithography process can be set. It is not necessary and can be further miniaturized.

The DRA according to the second embodiment of the present invention will be described below.
The structure of the M storage element will be described with reference to FIG.

In FIG. 4, the same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. A silicide layer 10 made of a titanium silicide layer is formed between the refractory metal film 6 and the diffusion layer 4. Therefore, the reaction between the refractory metal film and the diffusion layer 4 is suppressed, and the refractory metal film 6 is introduced into the diffusion layer 4.
Can be prevented and a stable capacitor electrode can be formed.

Although titanium is used as the silicide film in the above embodiment, similar effects can be obtained by using other materials such as cobalt and nickel.

Next, the manufacturing process of the memory element of the DRAM shown in FIG. 4 will be described with reference to FIGS. Further, in FIG. 5, the same parts as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted.

First, as shown in FIG. 5, a titanium film 9 is formed on the entire surface of the substrate. Then, as shown in FIG.
By performing heat treatment for several tens of seconds in the temperature range of up to 800 ° C., the silicide layer 10 made of the TiSi ₂ film (titanium silicide layer) is formed by reacting only the silicon portion of the base with the upper titanium film 9. On the oxide film remains unreacted with silicon. Then, the titanium film 9 is removed to form a TiSi ₂ film in a self-aligning manner only on the portion where the silicon is exposed. This method is usually called silicide technology, and not only titanium but also cobalt, nickel, etc. are used.

Thereafter, as shown in FIG. 7, a thin silicon oxide film 5 is formed on the entire surface and patterned to form a MOS.
Exposing part of the source or drain of the transistor.

Next, as shown in FIG. 8, a refractory metal film 6 is formed only on the portion where the underlying layer is the silicide layer 10 by chemical vapor deposition using a mixed gas of WF ₆ and H ₂ or WF ₆ and SiO _4. Are selectively grown and electrically connected to the diffusion layer 4 through the silicide layer 10. Here, the refractory metal film 6
Is a tungsten film, WF ₆ : H ₂ = 1: 50
Alternatively, under the growth condition such as a flow rate ratio of about WF ₆ : SiO ₄ = 1: 0.6, the tungsten film is formed, and at the same time, the uneven shape is formed on the surface of the tungsten film.

Thereafter, as shown in FIG. 9, a capacitor insulating film 7 formed of a silicon oxide film or a composite film of a silicon nitride film and a silicon oxide film is formed on the entire surface of the substrate.

Finally, the second capacitor electrode 8 made of a polycrystalline silicon film containing phosphorus or arsenic is formed on the entire surface of the substrate.
Are formed to complete the DRAM having the 1-transistor-1 capacitor shown in FIG. 4 as a memory element.

In the above embodiment, since the refractory metal film 6 is selectively grown only on the exposed portion of the silicide layer 10, the manufacturing process can be simplified and the refractory metal film formed by the photolithography process can be simplified. It is not necessary to set the patterning margin 6 and further miniaturization is possible.

[0046]

In the semiconductor memory device according to the present invention, by forming the uneven shape on the surface of the first capacitor electrode, the surface area acting as the capacitor electrode can be effectively expanded and the capacitance of the capacitor can be increased. Therefore, it is possible to realize a finer capacitor portion by satisfying a predetermined capacitor capacitance.

In the method of manufacturing a semiconductor memory device according to the present invention, the first capacitor electrode made of a refractory metal containing no phosphorus or arsenic is provided on the first impurity region or the second impurity region. Since it is formed, phosphorus or arsenic does not diffuse due to thermal diffusion even if an insulating film is formed thereon by a chemical vapor deposition method at a high temperature, and the first impurity region or the second impurity region is not diffused. No deep diffusion layer is formed below. Therefore, the leakage current does not flow between the adjacent memory elements, and the insulation reliability can be improved.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view illustrating the first manufacturing process of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a partial cross sectional view illustrating a second manufacturing step of the semiconductor memory device in the first embodiment of the present invention.

FIG. 4 is a partial cross-sectional view of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 5 is a partial cross-sectional view illustrating the first manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 6 is a partial cross-sectional view illustrating the second manufacturing process of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 7 is a partial cross sectional view illustrating a third manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 8 is a partial cross sectional view illustrating a fourth manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 9 is a partial cross sectional view illustrating a fifth manufacturing step of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 10 is a partial cross-sectional view of a conventional semiconductor memory device.

FIG. 11 is a partial cross-sectional view illustrating the first manufacturing process of the conventional semiconductor memory device.

FIG. 12 is a partial cross-sectional view illustrating the second manufacturing process of the conventional semiconductor memory device.

FIG. 13 is a partial cross-sectional view illustrating the third manufacturing process of the conventional semiconductor memory device.

FIG. 14 is a partial cross-sectional view illustrating the fourth manufacturing process of the conventional semiconductor memory device.

FIG. 15 is a partial cross-sectional view illustrating the fifth manufacturing step of the conventional semiconductor memory device.

[Explanation of symbols]

 1 Silicon Substrate 2 Thick Silicon Oxide Film 3 Gate Electrode 4 Diffusion Layer 5 Silicon Oxide Film 6 Refractory Metal Film 7 Capacitor Insulation Film 8 Second Capacitor Electrode

Claims (4)

[Claims] 1. A semiconductor memory device for storing information in the form of charge storage, comprising: a semiconductor substrate of a first conductivity type having a main surface; and a semiconductor substrate formed on the main surface with a space therebetween. A first impurity region and a second impurity region of a second conductivity type different from the first conductivity type, and a conductive layer formed on the main surface between the first impurity region and the second impurity region. A first capacitor electrode made of a refractory metal that is provided in contact with and is on the first impurity region or the second impurity region and has an uneven shape on the surface; A semiconductor memory device comprising: an insulating layer formed on the surface; and a second capacitor electrode formed on the surface of the insulating layer. 2. The semiconductor memory device according to claim 1, further comprising a silicide layer between the first capacitor electrode and the first impurity region or the second impurity region. 3. A first impurity region of a second conductivity type and a second impurity region of a second conductivity type different from the first conductivity type are formed on a main surface of a semiconductor substrate of the first conductivity type with a space therebetween. Forming a conductive layer on the main surface between the first impurity region and the second impurity region with an insulating film sandwiched between the first impurity region and the second impurity region; and a first capacitor made of a refractory metal having unevenness on the main surface. The electrode is connected to the first impurity region or the second impurity region.
Forming the insulating layer on the surface of the first capacitor electrode; forming a second capacitor electrode on the surface of the insulating layer; And a method of manufacturing a semiconductor memory device including. 4. The step of forming the first capacitor electrode includes the step of forming by chemical vapor deposition using a mixed gas of refractory metal fluoride and SiO ₄ or H _2. A method for manufacturing the semiconductor memory device described.