JPH06133008A - Fault collection system in duplex device - Google Patents

Abstract

PURPOSE:To record more correct fault information and to facilitate the retrieval of a fault by reading a collected serious fault cause from the device of a facing other system through an inter-system bus. CONSTITUTION:Devices are mutually connected through the inter-system bus 15, and the serious fault cause collection means 1 of the respective devices collect the serious fault causes of the self devices. The collected fault causes are read from the device of the facing other system through the bus 15 or the fault cause collection circuits of the respective devices collect fault causes including the serious fault cause of the self device. The collected fault cause is read from the device of the self system and from the device of the facing other system through the inter-system bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault collection system in a duplexer in which devices are connected to each other via an intersystem bus.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional duplexer. In FIG. 6, devices of system I and system II have the same configuration and are connected via an intersystem bus 15. Has been done. Each of these devices is provided with a main processor (CPU) 3, and this main processor 3 is provided with a ROM 7 for storing programs via a bus 13,
Program operation memory (MM) 5, IO register 6,
It is connected to the inter-system communication device 4.

Further, the main processor 3 is connected to the fault factor collecting circuit 2 via a bus 16 connected to the bus 13, and the fault factor collecting circuit 2 is connected to the switching control circuit 11 by a normal signal path. Is also connected. Here, the main processor 3 executes a required program in the processor storing ROM 7, and the program storing ROM 7 is a read-only memory for storing the program. The program operation memory 5 is a main memory used when a program operates, and is an IO memory.
The register 6 stores data for input / output.

The intersystem communication device 4 communicates between itself and another system, and includes intersystem bus connection drivers / receivers 8a and 8b and intersystem communication interface control register (I).
NFIO) 9, inter-system communication buffer memory (BM) 10
It is composed by. The inter-system bus connection driver / receiver 8a is for access from another system, and the inter-system bus connection driver / receiver 8b is for access to another system.

Intersystem communication interface control register 9
For example, when a command is input from the main processor 3, the corresponding interrupt signal is output and
It is for notifying a command. The inter-system communication buffer memory 10 is a storage circuit placed in the middle for correctly performing the interface between circuits having different operation levels.

The fault factor collection circuit 2 is a circuit for collecting fault information of fault factors (including severe fault factors) of the own device, activating the fault, and requesting system switching. The switching control circuit 11 is a circuit that performs system switching control between other systems. The intersystem bus 15 is a transmission line for intersystem communication, and the bus 13 is a transmission line for information between the main processor 3, the intersystem communication device 4, and the program operation memory 5. The bus 16 is used by the device of its own system to read the failure factors collected by the failure factor collection device 2.

Considering the case where the system I is operating as the active system and the system II is operating as the standby system by such a configuration, in this case, the active system I is regularly or irregularly operated by the standby system II. To the inter-system communication. That is, system I
When a command for intersystem communication is issued from the main processor 3 of 1, the command is sent to the intersystem communication interface control register 9.

Upon receiving this command, the inter-system communication interface control register 9 outputs an interrupt signal corresponding to this command, and this interrupt signal is transmitted through the inter-system bus connection driver / receiver 8a to another system which is a standby system. It is sent to II. At the same time, the information stored in the inter-system communication buffer memory 10 from the main processor 3 side is also sent to the other system II via the inter-system bus connection driver / receiver 8a.

Then, these interrupt signals and the information corresponding thereto are sent to the main processor 3 side of the other system II through the intersystem bus connection driver / receiver 8b of the other system II. Then, the main processor 3 of the other system II outputs the response command and the information corresponding thereto.
After that, the device on the other system side also transmits to the other side in the same manner as in the case of the own system. In this way, inter-system communication is performed between the redundantly configured devices.

By the way, when a failure occurs in the operation system device, this failure information is sent to the failure factor collecting circuit 2. The fault factor collection circuit 2 that receives this uses the route on the bus line, that is, the bus 16 and the bus 13.
The contents are notified to the main processor 3 of the own device via the, and a system switching signal is output to the switching control circuit 11 of the own device.

Then, the active system I and the standby system II are switched, and the specific contents of the failure are switched from the main processor 3 of the failed system to the active system by intersystem communication. It is sent to the main processor 3 of the system device. Then, the device of the system newly used as the active system performs a failure search based on the accurate failure information obtained from the failed system, and executes appropriate processing according to this failure.

[0012]

However, in the conventional fault collection system in the duplexer, a serious fault such as a memory fault, a watchdog timer detection fault due to a bus stack, a power stage fault, a clock interruption fault, etc. Would lead to a software runaway, and the inter-system communication itself would not be satisfactory.

In this case, of course, the system is switched between the active system and the standby system, but the switched active system cannot correctly recognize the failure cause of the other system. In other words, the operating system can only recognize that some serious failure has occurred in the failure system only due to the abnormal communication between the failure system and the failure system, and the contents of the serious failure cannot be understood at all. There is a problem that it cannot be applied.

Further, each of these fault factors is individually extended as one signal line to the other system to transmit fault information, and the operating system fetches it in the register of its own system and reads the register to cause the fault system. One of the methods is to detect the failure factor of 1. However, in that case, there is a problem that the number of signal lines increases by the number of failure factors. The present invention has been devised in view of such a problem, and in an apparatus configured to be duplicated, when a system switching is performed due to a serious failure such that intersystem communication cannot be satisfactorily performed, an operating system is a failed system. It is an object of the present invention to provide a failure collection method in a duplication device, in which the failure cause can be recognized, and more accurate failure information can be recorded to facilitate failure search.

[0015]

FIG. 1 is a block diagram of the principle of the first invention. In FIG. 1, devices of a system I and a system II are connected to each other via an intersystem bus 15. It is a duplicated device. Each device comprises a main processor 3, which is a bus 1
3 is connected to the inter-system communication device 4 and the memory 5. Further, the severe failure factor collection means 1 is connected to a device of another system which directly opposes via the bus 14 and the intersystem bus 15.

Here, the main processor 3 controls each circuit, and the intersystem communication device 4 performs intersystem communication of each device of the duplex system. The memory 5 is
The main memory for program operation, and the severe failure factor collecting means 1 collects the serious failure factors of its own device. The intersystem bus 15 is an information transmission path between systems, and the bus 13 is an information transmission path between the main processor 3, the intersystem communication device 4, and the memory 5. The bus 14 is for reading out the serious failure factor collected by the serious failure factor collecting means 1 from the device of the opposite system via the intersystem bus 15 (claim 1).

FIG. 2 is a block diagram of the principle of the second invention. Also in FIG. 2, the devices of the system I and the system II are connected to each other via an intersystem bus 15 and are duplicated. It is a device. Each device includes a main processor 3, and this main processor 3 is connected to an intersystem communication device 4 and a memory 5 via a bus 13. Further, the failure factor collecting means 2 is connected to the device of its own system via the buses 16 and 13, and is also connected to the device of another system directly opposite to it via the bus 14 and the intersystem bus 15. There is.

Here, the main processor 3, intersystem communication device 4, memory 5, bus 13, and intersystem bus 15 are the first
Is the same as in the invention. The failure factor collection means 2 collects failure factors including a serious failure factor of the device itself. The bus 14 is also the same as that of the first aspect of the invention, and is for reading out the fault factors collected by the fault factor collecting means 2 from the device of the opposite system via the intersystem bus 15. is there. The bus 16 is used by the device of its own system to read out the failure factors collected by the failure factor collecting means 2 (claim 2).

[0019]

In the fault collecting system in the duplexer of the first aspect of the invention described above, as shown in FIG.
In the redundant devices connected to each other via the device, the serious failure factor collection means 1 of each device collects the serious failure factor of its own device. Then, the serious failure factor collected by each of the serious failure factor collecting means 1 is read out from the device of the other system which is opposed via the intersystem bus 15 (claim 1).

In the fault collecting method in the duplexing device of the second invention, as shown in FIG. 2, in the duplexing device in which the devices are connected to each other through the intersystem bus 15, the fault factor collecting circuit of each device is connected. By 2, the failure factors including the serious failure factors of the own device are collected. Then, the fault factors collected by the respective fault factor collecting means 2 are read from the device of its own system and also from the device of the opposite system via the intersystem bus 15 (claim 2).

[0021]

Embodiments of the present invention will be described below with reference to the drawings. (A) Description of First Embodiment FIG. 3 is a block diagram showing a first embodiment of the present invention. In FIG. 3, the devices of system I and system II are connected to each other via an intersystem bus 15. It is a duplexer connected to each other.

Each device is provided with a main processor 3, and this main processor (CPU) 3 is via a bus 13 an intersystem communication device 4, a program operation memory (MM) 5, an IO register 6, R for program storage
It is connected to OM7. In addition, each of the above-described circuits includes a failure factor latch register 12 and a failure factor collection circuit (via a bus 16 connected to the bus 13, an intersystem bus 15, and a bus 14 connected to the intersystem bus 15). Failure factor collecting means) 2.

That is, the fault factor collection circuit 2 is connected to the device of the own system via the fault factor latch register 12, the buses 16 and 13, and the fault factor latch register 1
2, the bus 14, and the inter-system bus 15 are directly connected to the devices of other systems that face each other. The fault factor collection circuit 2 is also connected to the switching control circuit 11.

Here, the main processor 3, program operation memory 5, IO register 6, program storage R
The OM7, the failure factor collection circuit 2, and the switching control circuit 11 are
This is the same as the conventional one. The intersystem communication device 4 is also the same as the one in the prior art, that is, the intersystem bus connection driver / receiver 8
a, 8b, inter-system communication interface control register (IN
FIO) 9 and a buffer memory (BM) 10 for inter-system communication.

The fault factor latch register 12 is a circuit for controlling the direction so that the fault information can be read from the self system and the other system. Therefore, as shown in FIG. 4, the fault factor latch register 12 has two buffers 12.1a and 12.1.
b and two decoders 12 · 2a and 12 · 2b. This buffer 12.1a, 12.1b
When receiving a predetermined signal from the corresponding decoder 12.2a, 12.2b side, outputs the sent data to the opposite system side. Decoder 12 ・ 2a, 12
2b outputs a signal indicating that the stored information is output to the buffer 12.1 in accordance with the information sent from each system.

Bus 13, inter-system bus 15, bus 16
Is the same as the conventional one, and the bus 14 transfers the fault factors (including the severe fault factor) collected by the fault factor collecting circuit 2 from a device directly opposite to another system to another system. It is for reading via the bus 15. With the above configuration, as shown in FIG. 3, in a duplexer in which two devices are mutually connected via an intersystem bus 15,
Intersystem communication is carried out in the same manner as the above-mentioned conventional example.

By the way, when the system I is the active system,
When the fault factor collecting circuit 2 of the system I device collects the fault factor of its own device, the fault factor collecting circuit 2 of this system I
Outputs this failure information to the failure factor latch register 12. In addition, the failure factor collection circuit 2 includes the switching control circuit 1
The switching control circuit 11 of the system I, which outputs the switching request to 1 and receives the switching request, switches the operating system and the standby system together with the switching control circuit 11 of the system II. That is, the system I is the standby system and the system II is the active system.

Then, the fault factor latch register 12 of the system I which has received the fault information controls the direction so that it can be read from the self system and the other system. That is, when the failure information latch register 12 of the system I receives the failure information, the failure information shown in FIG.
This is received by the buffers 12.1a and 12.1b as shown in FIG. Then, the fact that the fault information is requested is transmitted to the decoder 12.2a of the fault factor latch register 12 of this system I. Upon receiving this request, the decoder 12.2a outputs a signal to the buffer 12.1a to output the failure information to the system I side, and the buffer 12.1a receiving this request outputs the failure information to the system I side. That is, it outputs to the bus 16.

If the fault information received via the buses 16 and 13 of the own system is mild fault information, the main processor 3 of the system I sends this content to the main processor 3 of the system II by intersystem communication. . That is, the main processor 3
Is an intersystem communication interface control register 9 of an intersystem communication device 4 of its own system (system I), an intersystem communication buffer memory 1
0, via the inter-system bus connection driver / receiver 8a and the inter-system bus connection driver / receiver 8b of the other system (system II), the minor fault information is sent to the main processor 3 of the system II.

Alternatively, when it is notified to the decoder 12 · 2b of the system I that the minor fault information is requested, the system I
Is the buffer 12.1b of the above description.
It is also possible to output the mild failure information to the system II side, that is, to the bus 14 side of the own system in the same manner as a. If this is done, this mild failure information will be transmitted to the bus 1 of system I.
4, intersystem bus connection driver / receiver 8a, intersystem bus 15, system II intersystem bus connection driver / receiver 8
b, the data is received by the main processor 3 of the system II via the bus 13. In other words, the minor fault factors collected by the fault factor collecting circuit 2 of the system I can be read directly from the opposing system II device.

Further, the buses 16 and 13 of the own system (system I)
If the fault information received via the system is severe fault information, the main processor 3 of the system I cannot send the contents to the main processor 3 of the system II by intersystem communication. For this reason, the fact that the severe failure information is requested is transmitted to the decoder 12 / 2b of the system I, and the buffer 12.1b of the system I is the buffer 12.1.
In the same way as a, the serious failure information is sent to the system II side, that is,
Output to the bus 14 side.

As a result, the serious fault information collected by the fault factor collecting circuit 2 of the system I is the same as the previous minor fault information. It is read directly without going through the main processor 3 of I). In this way, the failure information is of course read from the own system, but read access is also made from the other system. Then, when the system switching is performed due to the serious failure, the newly switched operating system (in this case, the system I
I) recognizes the failure factor of the failure system (system I) by reading the failure factor latch register 12 of the failure system.

The same processing as above is performed when a minor or severe failure occurs in the system II. In this way, according to the first embodiment, in the duplexer, each device is provided with the failure factor collection circuit 2, and the serious failure factors collected by each failure factor collection circuit 2 are opposed to the devices of other systems. Since it is configured so that it can be read out via the intersystem bus from each other, it is possible to add a signal line like the method that extends the fault factor to each other individually as one signal line and transmits the fault information. And when a system switchover occurs due to a serious failure that makes intersystem communication unsatisfactory,
Since the active system can recognize the cause of the fault in the fault system, the fault information can be recorded in the active system, which can switch the more accurate fault information with a simple circuit configuration, and the fault search can be facilitated.

Further, even in the case of a slight failure, the failure information can be sent to the main processor 3 of the operating system via the main processor 3 of the operating system, and the main processor 3 of the operating system can be directly operated without passing through the main processor 3 of the operating system. Fault information can be notified to the main processor 3. (B) Description of Second Embodiment FIG. 5 is a block diagram showing a second embodiment of the present invention.
In FIG. 5, each device of the system I and the system II is a redundant device in which the devices are mutually connected via an intersystem bus 15.

The duplexer is the same as the fault factor collecting circuit 2 and the bus 14 of the duplexer of the first embodiment.
Instead of the above, a mild failure factor collection circuit 1'and a bus 14 'are used. In addition, this duplexer is a bus 1
At the end of 4 ', a switching control circuit 11 of its own system is provided with a severe fault factor collecting circuit (severe fault factor collecting means) 1 connected by a normal signal path, and the other parts are the same. .

With such a configuration, as shown in FIG. 5, in a duplexer in which two devices are connected to each other via an intersystem bus 15, an intersystem is operated in the same manner as in the conventional example. Communication is carried out. By the way, when the system I is an active system and a fault other than a serious fault occurs in the device of the system I, that is, a minor fault occurs, the minor fault factor collecting circuit 1'of the system I causes the minor fault factor of its own device. Will be collected. This system I
Mild factor collection circuit 1'of system I which collects the factor of failure
Outputs the minor failure information of this failure factor to the failure factor latch register 12.

At the same time, the mild failure factor collection circuit 1 '
Outputs a switching request to the switching control circuit 11, and the switching control circuit 11 of the system I which receives the switching request switches the operating system and the standby system together with the switching control circuit 11 of the system II. That is, the system I is the standby system and the system II is the active system. Then, the device of the system I sends the mild failure information via the main processor 3 of its own system or the failure factor without going through the main processor 3 of its own system in the same manner as in the first embodiment. The minor fault information is directly sent from the latch register 12 to the main processor 3 of the other system. However,
In this case, the bus 14 'is used instead of the bus 14.

Further, when the system I is the active system and a serious failure occurs in the device of the system I, the serious failure factor collection circuit 1 of the system I collects the serious failure factor of its own device. Then,
The severe failure factor collection circuit 1 outputs a switching request to the switching control circuit 11, and the switching control circuit 11 of the system I which has received the switching request sets the system I to the standby system in the same manner as in the case of the previous mild failure information. , Switch system II to active system.

The severe fault factor collecting circuit 1 of the system I, which collects the serious fault factors of the system I, outputs the serious fault information of the fault factors from the bus 14 'of its own system to the inter-system bus connection of its own system. Via the driver / receiver 8a and the inter-system bus 15,
Output to system II of other system. Then, the severe fault information sent from the system I device to the system II device is received by the intersystem bus connection driver / receiver 8b of the system II device. After that, this serious fault information is received by the main processor 3 of the system II via the bus 13 of the system II.

In this way, the minor fault information is of course read from its own system, but read access is also made from other systems. If the system was switched due to a serious failure, the newly switched operating system (in this case,
The system II) recognizes the failure factor of the failure system (system I) by reading the severe failure factor collection circuit 1 of the failure system. It should be noted that the same processing as above is performed when a minor or severe failure occurs in the system II.

In this way, also in the case of the second embodiment, almost the same effects and advantages as in the case of the above-mentioned first embodiment can be obtained.

[0042]

As described above in detail, according to the failure collecting method in the duplexing device of the first invention, in the duplexing device in which the devices are connected to each other through the intersystem bus, each device is connected to the corresponding device. Severe failure factor collecting means for collecting the serious failure factor of the above, and configured so that the serious failure factors collected by each severe failure factor collecting means can be read from the device of the opposite system via the intersystem bus. This allows the operating system that has been switched to directly recognize the cause of the failure of the failed system when the system is switched due to a severe failure such that intersystem communication cannot be performed satisfactorily even though the circuit configuration is simple. There is an advantage (claim 1).

Further, according to the failure collecting method in the duplication device of the second invention, in the duplication device in which the devices are connected to each other via the intersystem bus, each device has a fault including a serious failure factor of the device. A failure factor collecting means for collecting factors is provided, and the failure factors collected by each failure factor collecting means are
In addition to reading from the device of its own system, the device is configured to read from the device of the opposite system via the intersystem bus. When a system switch is performed due to a serious failure such that communication cannot be performed satisfactorily, the switched operating system can directly recognize the failure cause of the failed system. Furthermore, there is an advantage that both the active system and the faulty system can recognize the mild or severe fault together (claim 2).

[Brief description of drawings]

FIG. 1 is a principle block diagram of a first invention.

FIG. 2 is a principle block diagram of a second invention.

FIG. 3 is a block diagram showing a first embodiment of the present invention.

FIG. 4 is a block diagram showing a failure factor latch register according to first and second embodiments of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of Codes] 1 Severe failure factor collection circuit (severe failure factor collection means) 1 ′ Mild failure factor collection circuit 2 Failure factor collection circuit (failure factor collection means) 3 Main processor 4 Inter-system communication device 5 Program operation memory ( 6) IO register 7 ROM for storing programs 8a, 8b Driver / receiver for intersystem bus connection 9 Intersystem communication interface control register 10 Intersystem communication buffer memory 11 Switching control circuit 12 Fault factor latch register 1.2.1a, 12 ... 1b Buffer 12.2a, 12.2b Decoder 13, 14, 14 ', 16 Bus 15 Inter-system bus I, II system

Claims (2)

[Claims] 1. A redundant device in which devices are connected to each other via an intersystem bus, each device is provided with a severe failure factor collection means (1) for collecting a serious failure factor of the device, and each serious failure factor is included. A fault collecting method in a duplexing device, characterized in that the serious fault factor collected by the collecting means (1) can be read from a device of another system facing the other via an intersystem bus. 2. A redundant device in which devices are connected to each other via an intersystem bus, each device being provided with a failure factor collecting means (2) for collecting a failure factor including a serious failure factor of the device, It is characterized in that the failure factors collected by the failure factor collecting means (2) can be read from a device of its own system and also read from a device of the opposite system via the intersystem bus. Failure collection method in redundant equipment.