JPH0612501A - Si type cpu module - Google Patents

Abstract

PURPOSE:To directly position even an external device excepting for a sub board on the bus of a processor provided with a serial communication function as well concerning the SI type CPU module mounting such a processor. CONSTITUTION:This SI type CPU module is provided with a memory 3 and a processor 2, which is equipped with functions for performing access through a multiplex bus 30 to this memory and serially communicating with the external device excepting for the sub board, on a sub board 1 linked to a mother board with a single in-line type connector 5. Then, the entire bus 30 is also opened to the external device 20 excepting for the sub board.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SI type CPU module equipped with a processor having a serial communication function, and more particularly to an SI type CPU module in which all of a multiplexed type bus is opened outside the module.

[0002]

2. Description of the Related Art An SI type module using an SI (single / inline) type connector can be mounted vertically on a mother board, so that a horizontal mounting type DI type using a DI (dual inline) type connector is used. Higher density mounting is possible compared to modules. SIMM (single in-line memory module) in which a memory is mounted on an SI type module is used as an expansion memory board. On the other hand, the SI type CPU module in which the processor is also mounted on the SI type module can be expected to have more functions.

When a transputer (trade name: manufactured by SGS Thomson) having a serial communication function is used as a processor mounted on the SI type CPU module, the memory in the module is accessed by using a bus, It becomes possible to communicate with external devices using a serial link.

FIG. 3 is a block diagram showing an example of a CPU module in which a single transputer 2 and an 8-chip memory 3 are mounted on a sub board 1. The transputer 2 accesses the memory 3 on the sub board 1 by using a multiplexed bus 30 in which an address bus and a data bus are multiplexed. The multiplex type bus 30 has a width of 32 bits, and includes 30-bit address data shared buses AD02 to AD31, 1-bit memory write data MWD0, and 1-bit memory refresh data MRD1.

As a data bus, AD02-31, MW
A total of 32 bits of D0 and MRD1 are divided into 8 bits and used. That is, MWD0, MRD1, AD02 to 0
8 bits of 7 are assigned to the memory of the first group and AD0
Eight bits from 8 to 15 are assigned to the second group of memories. Similarly, 8 bits of AD16 to 23 are allocated to the memory of the third group, and further 8 bits of AD24 to 31 are allocated to the memory of the fourth group.

On the other hand, the address bus AD0
Insufficient address A0 using 30 bits from 2 to 31
The portion corresponding to 0 and A01 is a 4-bit memory write bit MW obtained by decoding this in the transputer 2.
Use B0-3. In the example of FIG. 3, MWB0 to 3 are used for selecting a memory group, and all or part of AD02 to 31 is used for access in each memory chip. Here, since a 256K DRAM is used as the memory 3, AD02 to 19 are used as addresses. Of these, AD11 to 19 are input to the column address latch 31, and AD02 to 10 are input to the row / column address multiplexer 32. Since the output of the latch 31 is input to this multiplexer 32, it is eventually AD02.
The memory access is performed at -19. MWB0 to 3 also serve as strobe signals at the time of writing. MR is a strobe signal at the time of reading, and output enable O
Become E. On the other hand, MS0 to 3 are strobe signals of a specific pattern, MS0 is input to the latch 31, and MS1
Becomes the row address strobe RAS. Further, MS2 is input to the multiplexer 32, and MS3 becomes the column address strobe CAS. The above is the configuration of the memory selection unit on the sub board 1.

On the other hand, serial communication is performed to an external device by using the serial link Link. In this example, the case where there are four sets of serial links Link0 to Link3 is shown. Various communication signals are required for communication with the outside. Standard control signals include Reset Reset, Analyze Analyze, and
There are an error Error, a clock Clock, and a link speed Link Speed (in the figure, simply described as Speed). Vcc and GND are power supply systems.

FIG. 4 is a plan view of an SI type CPU module in which such a CPU module is mounted on a mother board with a 72-pin SI type connector 5. This SI
Since the type CPU module can be mounted vertically to the motherboard, it is suitable for high-density mounting. 22 is a column address latch, and 23 is a row / column address multiplexer. The memory 3 is assumed to be DRAM.

FIG. 5 is a block diagram of a system in which a plurality of transputer modules 7 are mounted on one motherboard 6. Each of the transputer modules 7A, 7B, 7C is configured as shown in FIGS. 3 and 4, and each has four serial link links.
To serially communicate with external devices via. 8 is the root transputer that hosts this system,
9 is a link switching device for connecting the serial links to each other, 1
Reference numerals 0A and 10B are link adapters that perform serial / parallel conversion to connect the external bus 11 and the serial link, and 12 is a reset signal Res that receives an error signal Error from the hung-up transputer.
system control logic to generate et, 1
Reference numeral 3 is an off-board expansion connector.

[0010]

In the general usage of the transputer described above, the construction is closed, so that
For example, external peripheral devices (timer, interface controller, DMA controller, etc.) cannot be directly positioned on the bus of the transputer. If a link adapter having a serial / parallel conversion function is used to do this, the transfer rate deteriorates, and one or more links, which are communication means between processors, are occupied. There is a drawback that all cannot be mounted on the sub board 1 having a limited area.

According to the present invention, an SI having a processor having a serial communication function such as the transputer described above is mounted.
It is an object of the type CPU module to allow external devices outside the sub-board to be directly positioned on the bus of the processor.

[0012]

In order to achieve the above object, according to the present invention, a memory and a multiplexed bus for this memory are provided on a sub board coupled to a mother board by a single in-line type connector. In a SI type CPU module equipped with a processor having a function of accessing and externally communicating with an external device outside the sub-board, the multiplexed bus also with respect to the external device outside the sub-board. It is characterized by opening all of.

Specifically, the entire multiplexed bus of the processor and necessary control signal lines are connected to empty terminals of the connector and opened to the outside. In this case, an external device selection unit for selecting one of a plurality of external devices sharing the multiplex type bus is provided outside the sub board to use the bus opened to the outside. The external device selection unit can have the same configuration as the memory selection unit on the sub board.

[0014]

In the SI type CPU module of the present invention, the entire multiplexed type bus is open to the outside, so that an external device is placed on the bus of the processor having the serial communication function on this module. Can be positioned directly. Therefore, in general, only the serial communication function is used to communicate with the outside. Therefore, even an SI type CPU module equipped with a processor such as a transputer, which was considered to be closed, can be connected to an expansion device that exceeds the limitation on the number of serial links. In addition, since it can be placed on the bus, the closure of the system can be eased. In particular, by putting out all of the bus to the outside, a transputer which normally becomes only a slave can be used as a master. Moreover, since the connector used is SI type, by mounting it vertically (or diagonally) on the motherboard,
The degree of integration of the parallel processing units can be dramatically improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of essential parts showing an embodiment of the present invention. In this figure, 1 is a sub board, 2 is a transputer, 3A, 3B ...
M or DRAM), 5 is an SI type connector, 30 is a multiplex type bus, and these are the SI type CP of the present invention.
It is the main component of the U module. SI type CP of this example
U module is a 32-bit multiplexed bus 3
By outputting all 0s to the outside, a large number of peripheral devices 20A, 20B, 20C ...
It can be directly positioned on the bus 30 of the above. The number of buses opened to the outside is limited by the number of pins of the SI type connector 5. When the T805 type transputer is used, if the 72-pin SI type connector 5 is used, all the 32-bit buses 30 can be output to the outside.

Examples of the external device 20 sharing the bus 10 include peripherals such as a timer, an interface controller and a DMA controller. However, if the bus width is 32 bits, a memory can be connected. An external address decoder 21 sends a selection signal to the external device 20.

FIG. 2 is a block diagram showing the SI type CPU module of the present invention in more detail. The SI type CPU module shown in this figure has all the configurations shown in FIG. 3 and, in order to open all the buses 30 to the outside, exchanges necessary control signals with the outside. That is, as described above, as the standard control signal, reset Reset and analyze Ana
There are lyse, error Error, clock Clock, and link speed Speed (Vcc and GND are power supply systems). The memory write bits MWB0 to MWB3 and the memory strobe MS are used as extension control signals.
Send 0-3 etc. to the outside.

External device selectors 21, 22, and 23 are provided outside the CPU module. Of these, the external address decoder 21 is used for the external devices 20A, 20
Chip select CS that activates only one B ...
0 to CS3 are generated. In addition, column address latch 2
2 and the row / column address multiplexer 23 are CP
This is the same as the internal configuration of the U module (31 and 32 in FIG. 3).

[0019]

As described above, according to the present invention, an SI type CP equipped with a processor having a serial communication function is installed.
In the U module, all buses are opened to the outside of the module, so that external devices outside the sub board can be directly positioned on the bus of the processor. Therefore, there is an advantage that a CPU module equipped with a processor such as a transputer having a limited serial link has expandability and can function as a master. Further, even if all the buses are output, since the buses are of the multiplexer type, SI type connectors can be sufficiently used, and there is an advantage that they can be applied to the construction of a highly integrated and highly functional system.

[Brief description of drawings]

FIG. 1 is a block diagram of an essential part showing an embodiment of the present invention.

FIG. 2 is a block diagram showing the SI type CPU module of the present invention in more detail.

FIG. 3 is a block diagram showing an example of a CPU module.

FIG. 4 is a plan view of an SI type CPU module.

FIG. 5 is a block diagram of a system in which a plurality of CPU modules are mounted.

[Explanation of symbols]

1 ... Sub board, 2 ... Processor having serial communication function, 3 ... Memory, 4 ... Address decoder, 5 ... SI type connector, 20 ... External device, 21 ... External address decoder, 22 ... Column address latch, 23 ... Row / Column address multiplexer, 30 ... Multiplex type bus.

Claims (4)

[Claims] 1. A memory, a memory, and a multiplexed bus for accessing the memory on a sub-board connected to a mother board by a single in-line type connector, and for an external device outside the sub-board. Is an SI-type CPU module equipped with a processor having a function of serial communication, wherein the SI-type bus module is open to all external devices outside the sub-board. CPU module. 2. The SI according to claim 1, wherein all of the multiplex type buses of the processor and necessary control signal lines are connected to an empty terminal of the connector and opened to the outside. Type CPU module. 3. The SI type according to claim 2, wherein an external device selection section for selecting one of a plurality of external devices sharing the multiplex type bus is provided outside the sub board and used. CPU module. 4. The SI type CPU module according to claim 3, wherein the external device selection unit has the same configuration as the memory selection unit on the sub-board.