JPH06102311A - Test method and apparatus for semiconductor package - Google Patents

Abstract

PURPOSE:To provide method and apparatus which do not damage the flatness of a lead pin and not cause jamming at the time of testing a thin semiconductor package. CONSTITUTION:A semiconductor package test apparatus comprises a loader 1 for carrying in a tray 7 where plural semiconductor packages 5 are stored, an X-Y stage 2 for sequentially receiving the tray 7 in a test site and positioning the same, a test device 4 which is disposed above the X-Y stage 2 and includes probe pins 8a, 8b which can come into contact with lead pins 5a, 5b of the semiconductor package 5, and an unloader 3 for carrying out the tray 7 where the semiconductor packages 5 are stored after the end of measurement. By this arrangement, the semiconductor package 5 can be tested correctly.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package testing method and apparatus.

[0002]

2. Description of the Related Art Conventionally, when testing a semiconductor package (hereinafter simply referred to as a package), the package is handled by using a belt type or natural drop type test handler device, and then the lead pins of the package are connected to a test site unit. It is common to insert various types of data by inserting them into a socket provided in the socket, mechanically fixing them, and applying a test signal to a test terminal in the socket.

[0003]

However, using the above-mentioned conventional test apparatus, for example, TSOP (Thin S
When testing a thin package such as a mall out-line package, the lead pin flatness (Coplanarit
It is difficult to deal with lead deformation such as damage to y). Further, the method of transporting the package in the test handler device has a problem such as jamming.

An object of the present invention is to provide a semiconductor package test method and apparatus for solving the above problems of the prior art.

[0005]

The first aspect of the present invention is as follows.
A step of carrying in a tray containing a plurality of semiconductor packages, a step of moving the tray to a test site and positioning it at a predetermined position, a step of measuring the semiconductor package, and a step of carrying out the semiconductor package after the measurement. And a semiconductor package testing method.

A second aspect of the present invention is a loader for loading a tray containing a plurality of semiconductor packages, an XY stage for sequentially receiving and positioning the trays at a test site, and the XY stage. A test of a semiconductor package, which comprises: a test device, which is provided above the probe, and which has a probe pin capable of contacting a lead pin of the semiconductor package; and an unloader which carries out a tray containing the semiconductor package after the measurement is completed. It is a device.

[0007]

[Operation] According to the present invention, a tray containing a plurality of semiconductor packages is continuously carried into a test site of an XY stage, and a probe pin of a measuring instrument is brought into contact with a lead pin of the semiconductor package from above. Since the test is performed, even when testing a thin package, various data can be accurately measured without deforming the lead pins and without fear of jamming.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings. 1 is a side view showing an embodiment of a test handler device of the present invention, FIG. 2 is a sectional view of a measuring device used in the present invention, and FIG. 3 is a plan view of a tray used in the present invention.

In FIG. 1, 1 is a loader, 2 is an XY stage, and 3 is an unloader. Reference numeral 4 is a measuring device for testing the semiconductor package 5, 6 is a testing device, and 7 is a tray on which a plurality of semiconductor packages 5 to be measured are placed. Here, as shown in FIG. 2, the measuring device 4 is provided with a plurality of pairs of probe pins 8a and 8b capable of contacting the opposing lead pins 5a and 5b of the semiconductor package 5. The number of the probe pins 8a and 8b is such that 32 semiconductor packages 5 can be simultaneously measured.

The tray 7 has a rectangular shape as shown in FIG. 3, and a plurality of semiconductor packages 5 are arranged in the tray 7 at intervals a in the X-axis direction and at intervals b in the Y-axis direction. Placed in precision. The size of these intervals a and b is an integral multiple of the pitch p of the leads 5a of the semiconductor package 5. The operation of the test handler device configured as above will be described. A tray 7 having a plurality of semiconductor packages 5 arranged at predetermined intervals is set on the entry side of the plurality of loaders 1. Then, by the loader 1, the first one tray 7
Is carried into the test site of the XY stage 2 and positioned at a predetermined position. The measuring device 4 standing by above the XY stage 2 is lowered, and its probe pins 8a, 8b are brought into contact with the lead pins 5a, 5b of the semiconductor package 5 to be tested for measurement. The semiconductor packages 5 in the tray 7 are sequentially measured, and when the measurement of all of the semiconductor packages 5 is completed, the measuring device 4 is lifted to stand by at a predetermined position, and the semiconductor packages 5 are unloaded to the next step by the unloader 3.

[0011]

As described above, the present invention has the following great effects. Since there is no jamming as in the conventional example, mechanical bending and package defects are reduced. Since the probe pin is moved to make contact with the lead pin, there are few contact mistakes. Since a socket or the like is not used at the time of measurement unlike the conventional example, lead deformation does not occur, and the influence of contact capacitance and impedance is small. Since the simultaneous measurement can be performed, the test site area can be reduced.

[Brief description of drawings]

FIG. 1 is a side view showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a test apparatus used in the present invention.

FIG. 3 is a plan view of a tray used in the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Loader 2 XY stage 3 Unloader 4 Measuring instrument 5 Semiconductor package 5a, 5b Lead pin 6 Testing device 7 Tray 8a, 8b Probe pin

Claims (2)

[Claims] 1. A step of carrying in a tray containing a plurality of semiconductor packages, a step of moving the tray to a test site and positioning it at a predetermined position, a step of measuring the semiconductor package, and a semiconductor for which measurement has been completed. A method for testing a semiconductor package, which comprises the step of unloading the package. 2. A loader for loading a tray containing a plurality of semiconductor packages, an XY stage for sequentially receiving and positioning the tray at a test site, and the XY stage.
A test device provided with a probe pin arranged above the Y stage and capable of contacting a lead pin of a semiconductor package;
A semiconductor package test apparatus, comprising: an unloader that carries out a tray containing a semiconductor package after measurement.