JPH06101787B2 - Image data scaling processor - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scaling device for image data used in digital copiers, facsimiles, other image processing devices, and the like.

2. Related Art FIG. 8 shows an external view of a conventional image reading apparatus. This image reading device has a shape like a top of a copying machine. A document is placed on the contact glass 2 and pressed by the document pressure plate 3. The operation unit 4 includes
It is equipped with several kinds of keys such as a reading start button and a density selection key, and several kinds of displays for displaying the setting status and the operating status, so that various functions can be set.

Start scanning by pressing the start button,
An image signal can be obtained.

9 and 10 show a typical configuration of the image reading apparatus shown in FIG. 8, particularly a reading optical system. FIG. 9 shows an optical system when a contact image sensor is used.
Figure 10 shows the optical system when a reduced image sensor is used. Other than this, there is a document whose document is moved and the optical system is fixed.

When the contact image sensor as shown in FIG. 9 is used, the optical system is a 1 × optical system. The original surface on the contact glass 2 is illuminated by the fluorescent lamp 5 and its reflected light 8
Enters the image sensor 7 through the self-hook lens 6. The image sensor 7 has a width equal to or larger than the document width (the depth direction in FIG. 9, that is, the main scanning direction X), and the image data of one line in the width direction is read at one time.

Number of lines sampled and sampling pitch Px
Depends on the number of pixels of the image sensor. After reading one line of data, the carriage 9 that integrates the fluorescent lamp 5, the self-hoc lens 6, and the image sensor 7 is driven in the direction of the arrow (sub-scanning direction Y), and the next line is read. There is also a mode in which the carriage 9 is continuously driven in the sub-scanning direction Y. The pitch Py between the lines is determined by the speed of the carriage 9, the charge storage time of the sensor 7, etc., but is normally set to the same sampling pitch Py as described above.

When a reduction type image sensor is used as shown in FIG. 10, the lens 14 reduces the document width of the optical image so as to match the size of the image sensor. In FIG. 10, three mirrors are used, but two or five mirrors are also conceivable. Reading in the main scanning direction X is the same as when using a contact sensor. In the sub-scanning direction Y, the first carriage in which the fluorescent lamp 10 and the first mirror 11 are integrated and the second carriage in which the mirrors 12 and 13 are integrated are independently provided on the contact glass plate 2 from the original. It is driven so that the optical path length to the lens 14 is constant.

Here, in the conventional variable magnification method, with respect to the main scanning direction X,
This is performed by changing the optical path length of the optical system to change the reduction ratio, and in the sub-scanning direction Y, the speed of the moving body is changed. However, this method
It cannot be used when the contact type sensor as shown in the figure is used.

Even in the case of the compact sensor shown in FIG. 10, the lens
The range of the magnification change is structurally limited, such as the amount of movement that changes the positions of the 14 and the sensor 7 is large, but the magnification ratio does not change so much. However, a precise mechanism has to be used, and a coarse mechanism has a big problem that the read image is deformed.

In consideration of these conventional problems, recently, instead of optical scaling, image processing to obtain scaled image data by predictively calculating the scaled data from the same-magnification read data, so-called electrical scaling is used. I'm starting to be seen.

However, the electrical scaling currently proposed has a problem in the precision of the scaling, and if the scaling is performed accurately, the hardware becomes complicated and so-called zoom scaling such as 1% step,
There was a problem that it was difficult to deal with a wide range of magnifications.

Further, when the image is read by scanning, the spatial frequency characteristic of the image represented by the read data changes, and the image deteriorates. Therefore, in the past, the read image data was MTF (Modul
ation Transfer Function) correction (repair of blurred image). This is, for example, by defining a coefficient pattern (filter) as shown in FIG. 13a, and, for example, the target pixel data Oik shown in FIG. 13b (here, the data showing the density).
Mik = Y · Oi ₋₁ k + V · Oik ₋₁ + W · Oik ₊₁ + Z · Oi ₊₁
Correct the data Mik to be k + X · oik. Correction coefficient V to Z
The (filter coefficient) is set to a value as shown in FIG. 14b, for example. Since these correction coefficients have appropriate values corresponding to the spatial frequency characteristics (supplementing density) of the original image data, they are usually set to values corresponding to the original image sampling density of scanner.

Therefore, the appropriate MTF correction characteristics differ with respect to the new sampling frequency at the time of scaling (the sampling density of the scaled image data corresponding to the original image), and it is necessary to change the correction coefficient. In particular, it is difficult to apply the correction coefficient (FIG. 14b) at the same magnification as it is to a wide range of magnification change of 50 to 400% as in the embodiment of the present invention described later.

If this is ignored and MTF correction is performed with the same correction factor (Fig. 14b) at a reduction ratio or enlargement ratio, the image vibration phenomenon (striped pattern) may occur due to over-emphasizing the image edge due to MTF correction during enlargement. Occur.

An object of the present invention is to scale image data with relatively high precision, relatively fine scaling and relatively wide scaling.
In addition, it is intended to prevent incompatibility of MTF correction due to scaling in performing this scaling processing in real time.

First, the basic idea of variable magnification executed in the later-described embodiment of the present invention will be described.

For example, in the image data obtained by the image reading apparatus shown in FIG. 9 or FIG. 10 (hereinafter referred to as original image data), the number of pixels in the main scanning direction X is N, and the number of pixels in the sub scanning direction Y is M.
Then, the distribution of the image data corresponding to the original image can be considered as shown in FIG. R% in the main scanning direction in Fig. 11
[N × R / 100] new data (hereinafter referred to as scaled image data) can be generated by scaling at a magnification of.

Here, three typical scaling algorithms will be described. Here, since the electrical scaling is performed only in the main scanning direction, the following description also applies.

First, in any method, it is necessary to recognize the position of the new sampling point 0 after scaling and obtain the original image data of the old sampling points of several pixels around the new sampling point 0 and their distances.

As shown in FIG. 12, the new sampling point 0 is between Sij and Sij ₊₁ of the original image data, and the distance between them is 0 .
Let r ₁ and r ₂ , and let P be the sampling pitch of the original image data.

As the scaling image data of nearest pixel substitution method 0 point, a method of setting the original image data closest to the 0, if r ₁ ≦ r ₂ If Oik = Sij r _1> r ₂ in FIG. 12 For example, Oik = Sij _{+ 1} . That is, the image data of the sampling points closest the original image to the sampling point 0 of the scaled image, the scaled image data Oik of the point 0.

A method for distributing the density level according to the distance between adjacent pixels adjacent interpixel distance linear Allocation 0 and the original image data. Scaled image data Oik in Fig. 12
It _{is, Oik = (1-r 1} / P) Sij + (1-r 2 / P) Sij +1 ...... (1) obtained from.

Cubic function convolution method Interpolation calculation is performed using an interpolation function h (γ) as shown in FIG.

h (γ) is approximated by the following equation to γ that has been qualified with the sampling pitch P.

Scaled image data Oij using this h (gamma) is, Oik = _{[h (1 + r 1 / P} ) Sij -1 + h (r 1 / P) Sij + h (r 2 / P) Sij +1 + h (1 + r 2 / P) Sij ₊₂ ] /
_{[H (1 + r 1 / P} ) + h (r 1 / P) + h (r 2 / P) + h (1 + r 2 / P) ]
(3) In addition to the above, there are methods such as the proximity pixel distance inverse proportional method and the proximity pixel area allocation method, but since they are relatively similar, the above is considered as a representative example.

All of these methods have been known for a relatively long time, and have been put to practical use mainly in the field of computer image processing.

For computer image processing, etc., when image data is stored in a high-capacity memory such as a page memory and then scaling processing is performed, these methods can be easily used, but there is no page memory and dedicated hardware is used. To do these things,
There are various restrictions.

When performing scaling with a digital copier, facsimile, etc. during scanning, it is necessary to perform raster scanning (line units) on the data input in raster scanning (line units) even after scaling processing, and also use the data clock ( Pixel sync pulse) needs to be constant at any magnification.

In other words, the data after the scaling process must be in the same format and at the same speed as the optical scaling. That is, real-time processing is required.

This means that if the digital copier system or the entire facsimile system can be scaled,
Different.

For example, if the printing speed of the printer can be changed at the time of scaling, the data clock of the scaling factor can also be changed. Further, in a system that performs transmission, it does not need to be raster scan data after scaling.

However, when the magnification is considered as a reading device or when the magnification processing is independently performed, the raster scanning processing is limited as described above.

The embodiment of the present invention described below is a variable power device applicable to a reading device subject to these restrictions.

FIG. 6 and FIG. 7 are examples of time charts of pre-scaling data and post-scaling data that satisfy this restriction. In these, LSYNC is a horizontal cycle signal (line synchronization pulse: sub-scanning synchronization pulse) and reads image data of one line in the main scanning direction during one cycle of this signal. DCLK is a data clock (pixel synchronization pulse). At the timing shown in FIG. 6, it is assumed that pre-scaling data (pixel unit) Y is input to the scaling processing section from Si ₀ to Si _N in synchronization with DCLK within the period of LSYNC.

As a result, the scaled data Z is output. The output may be delayed from the data Y, but it must be synchronized with DCLK. The delay time (t ₂ −t ₁ ) is not particularly limited, but it should not change between lines, and t ₂ and t ₁ should always be constant.

In addition, when inputting / outputting data in line units,
As shown in the figure, the read data (input) of the line buffer memories RAM1 and RAM2 may be later than the write data (output).

Anyway, the most important and most difficult thing is to synchronize the scaled image data to DCLK at any magnification.

This requirement is relatively easy to achieve if the magnification is changed with several fixed magnifications, but especially in recent copying systems, a wide range of magnification and a small magnification of about 1%, which is called zoom magnification, are used. It is required to change the magnification all the time, and it has become necessary for digital copiers and facsimiles to meet these demands. Therefore, it is difficult to satisfy the demands of the preceding requirements in actually applying the above-described scaling method.

Configuration The variable power processing apparatus of the present invention, first, a calculation means for calculating the original image data sampling position information corresponding to the designated magnification R for creating the variable size image data; the original image based on the original image data sampling position information Sampling position designating means for designating the sampling designated position x of data; Sampling means for extracting the original image data at the designated position x; Scaled image data setting means for computing scaled image data corresponding to the extracted original image data; And designated magnification R
MTF correction calculation data associated with the MTF correction calculation data, and based on the MTF correction calculation data, MTF correction means for MTF-correcting image data after scaling or before scaling.

[Action]

According to this, the MTF correction calculation according to the designated magnification R is performed, and the image deterioration due to the scaling processing is reduced.

In the embodiment of the present invention, in order to execute the real-time processing as described above, the calculation means 100i / [specified magnification R
(%)] = Ji + Ri, i is an integer, 0 ≦ Ri <1, Ji is an integer, and an integer Ji and a decimal fraction Ri are calculated; the sampling position designating means synchronizes with a data clock that determines a pixel unit of the original image data. And i is changed one by one, and when R <100, Ji-Ji _-1 = 2 and the sampling designated position x of the original image data x
Is set to be 2 larger, Ji-Ji _-1 = 1 to specify the specified position x to be 1 larger, and when R ≧ 100, Ji-Ji _-1 = 1 is set to be 1 to increase the position x to 1 larger. -When Ji _-1 = 0, the position x is designated as it is; the sampling means counts the data clock to extract the original image data at the designated position x and one or more image data adjacent thereto. The scaled image data setting means synchronizes the scaled image data at position i with Ri, the original image data at the designated position x, and one or more original image data adjacent thereto, in correlation with each other. Establish.

According to this, the sampling position x of the original image data is designated by the calculation means and the sampling position designating means at a pitch corresponding to the scaling ratio R, and the sampling means designates the original image at the position x and a position adjacent to it. The data is extracted and the scaled image data setting means uses a predetermined logic,
For example, the variable-magnification image data is set by the processing such as the above. Since the sampling position designating means, the sampling means and the scaled image data setting means all operate in synchronization with the data clock DCLK of the original image data, the scaled image data is synchronized with the data clock DCLK. That is, variable-magnification image data can be obtained by real-time processing. Therefore, it is possible to process the scaled image data in a raster scan type.

The calculating means may calculate Ji and Ri by increasing i by 1 each time one pulse of the data clock DCLK appears, or i = 0 to R-1 before the actual image reading.
Ji and Ri of each of the above are calculated in advance, these data are stored in a memory such as RAM3, and i is sequentially changed to a number larger by 1 in synchronization with the data clock DCLK. You may make it read Ji and Ri matched with the number. Either way, Ji and Ri
Are sequentially specified in synchronization with the data clock DCLK.

As described above, the calculation means uses 100i / [specified magnification R
(%)] = Ji + Ri, i is an integer, 0 ≦ Ri <1, Ji is an integer, an integer Ji and a decimal number Ri, the maximum integer Ji is calculated, and this Ji and the integer Ji calculated previously are calculated. Since the sampling position x (that is, Ji) of the original image data is specified by the sampling position specifying means based on Ji _-1 , the scaling factor R (%) is set to an arbitrary number and range with 1 as the minimum unit. Can be set. That is, zoom magnification in units of 1% is realized, and the zoomable range can be set extremely wide. In the embodiment of the present invention described later, the scaling factor is 1%.
As a unit, R = 50% to 400% is settable range.

In one embodiment of the present invention, memory means for storing original image data for one line; means for alternately setting the memory means for writing / reading; address counting means for giving write / read position x to the memory means; Prepare That is, a line buffer memory is provided.

The sampling position designating means, when writing to the memory means, provides the address counting means with a data clock DCLK that defines the pixel unit of the original image data as a count pulse, and when reading from the memory means, the data clock DCLK. I is increased by 1 for each pulse of, and when R <100, when Ji-Ji _-1 = 2, the count pulse 2DCLK having twice the frequency of the data clock DCLK is
When Ji _-1 = 1 is given, the data clock DCLK is given as a count pulse to the address counting means, and when R ≧ 100, Ji-
When Ji _-1 = 1 the data clock DCLK is given to the address counting means, and when Ji-Ji _-1 = 0 the count pulse to the address counting means is cut off to read out the original image data at the read position x.
Shall be specified. Prior to reading the original image, the calculation means 100i / [designated copy magnification R (%)] = Ji + Ri, i =
0-R-1,0 ≤ Ri <1, Ji is an integer, and integer Ji and decimal R
It is assumed that data (Ai) for specifying x corresponding to i and data (Bi) for calculating the scaled image data are calculated and stored in the RAM3. When image reading is started, RAM3
The data is read out and given to the sampling position designating means and the scaled image data setting means. As described above, the variable-magnification image data setting means synchronizes the Ri (data Bi), the original image data at the designated position x read from the memory means, and one or more original image data adjacent thereto in synchronization with the data clock DCLK. The scaled image data setting means determines the scaled image data at the position i based on the correlation of the three parties.

That is, in this embodiment, one line of original image data is stored in the buffer memory, and its read address is controlled to perform read sampling of the original image data,
Obtain the scaled image data. The change amount of the read address of the image data at the time of reduction, that is, the read pitch of the original image data corresponding to the scaling factor is the count clock to be given to the read address counter of the buffer memory.
It is performed by switching between DCLK and a clock 2DCLK having a frequency twice that of DCLK.

In another embodiment of the present invention, a line buffer memory is provided at the same time as the above-mentioned embodiment, but the read address is the address counting means; the up / down counting means; and the count data of the address counting means and the up / down counting means. The sum of the count data of is added to the line buffer memory as address data.

Then, the sampling position designating means gives a data clock DCLK for defining a pixel unit of the original image data as a count pulse to the address counting means when writing to the memory means, and R when reading from the memory means.
In the case of <100, the up / down counting means is instructed to up, and the data clock DCLK is given to the address counting means as a count pulse, and when Ji-Ji _-1 = 2, the data clock DCLK is also given to the up / down counting means. J
When i ₋₁ = 1, no count pulse is given to the up / down counting means, and when R ≧ 100, the up / down counting means is instructed to down, and the data clock DCLK is given to the address counting means, and Ji-Ji _{− When 1} = 1, the data clock DCLK is not given to the up / down count means, and Ji-J
When i ₋₁ = 0, the data clock DCLK is also applied to the up / down count means to specify the read position x of the original image data.

That is, the read number x of the line buffer memory is determined by increasing or decreasing the count number of the data clock DCLK according to the scaling factor.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the drawings.

FIG. 1a shows a first embodiment of the present invention, FIG. 2a shows a second embodiment, FIG. 3a shows a third embodiment, and FIG. 4 shows a fourth embodiment. First, the outline of these embodiments will be described.

Referring to FIG. 1a, the device shown in FIG. 1a (excluding the printer PRT) is a reading device that can be used for both digital copiers and facsimiles, and is incorporated in the exterior shown in FIG. It is what The SKYANA SCR scans A3 originals at a density of 400 dpi (pixels / inch) at 6 bits / pixel (64 gradations), performs shading correction, MTF correction, etc., and uses this 6-bit original image data for the printer. Alternatively, it is a device for converting into a binary signal / pixel of “1” or “0” for transmission and outputting. In addition,
These reading densities and gradations are examples, and 400dp
The gradation does not have to be i or 64.

The document surface DOC is illuminated by the light from the light source 5, and the reflected light is read at 400 dpi in the A3 document lateral direction (297 mm).
The pixel image sensor 7 receives it.

The image sensor 7 converts the optical signal of the document DOC into an electric signal, and the amplifier 22 widens the signal to a signal of a predetermined level. Next, the analog signal having a different voltage level depending on the density is converted by the A / D converter 23 into a 6-bit digital signal, that is, image data.

Next, the circuit 24 performs shading correction for correcting variations in sensitivity of each element of the 5000-pixel sensor 7 and unevenness of illuminance of the light source 5 in the A3 original lateral direction.

The scaling process is performed after this shading correction in the embodiment shown in FIG. 1a. That is, the main-scanning-direction scaling calculator 28 performs scaling processing in the main-scanning direction X, and immediately after this scaling processing, MTF correction in the main-scanning direction X is executed. The scaling process in the sub-scanning direction Y is performed, and subsequently the MTF correction in the sub-scanning direction Y is performed. These scaling processes are performed before the shading correction circuit 24 and MTF correction (2
It can also be done after 9).

After the scaling processing in the main scanning direction X and the MTF correction by the calculator 28, the scaling processing in the sub scanning direction Y and the MTF correction are performed in the circuit 29, and then the scaled image data is converted into the binarization circuit 30.
It is binarized to "1" or "0" according to the threshold level, and is output to the printer PRT (or the transmission processing unit). Alternatively, the gradation processor 31 converts the halftone expression to "1" or "0", and the printer PRT (or transmission processing unit)
Output to. Note that FIG. 1a shows a mode of outputting to the printer PRT.

In such a flow of image data, the scaling process in the main scanning direction X and the MTF correction are roughly shown in FIG. 1a by the parallel 6-bit latch 25 to the arithmetic unit 28, the microprocessor 35, the RAM 3 and the sampling circuit. It is executed by a scaling processing device composed of 64 and 65.

This scaling apparatus extracts the position of the new sampling point i after scaling, the function of extracting the original image data at the original image data position x around the new sampling point i, and the new sampling point i. It has a function of calculating the scaled image data from the distance from the original image data position x (Ji) and the extracted data, and a function of performing MTF correction of the scaled image data. The configuration of the main-scanning direction scaling calculator 28 is shown in FIG. 1d.

The scaling processing in the sub-scanning direction Y and the MTF correction are performed by the sub-scanning scaling calculator 29. The configuration of the sub-scanning scaling calculator 29 is shown in FIG. 1e.

In FIG. 1a, first, the latch 25, the data distributor 26, the RAM1 and RAM2 as the line buffer memory, and the data selector 27 determine the sampling point x in the future to extract the image data and extract the scaled image data. When performing the calculation, in order to take out a plurality of original image data to be referred to in the scaled image data calculation at a time, an interpolation method using two peripheral pixels by the correction method (implementation shown in FIGS. 1a, 2a and 4 is performed. In the example), every two pixels are grouped together, and in the interpolation method using four peripheral pixels (the example in FIG. 3a), every four pixels are grouped together.

For example, when the new sampling point 0 is between Sij and Sij _{+1 in} FIG. 12, the data selector 27 selects Sij and Sij ₊₁ (see
Examples shown in FIGS. 1a, 2a and 4) or Sij
_This means that _-1 , Sij, Sij ₊₁ and Sij ₊₂ are taken out at once (the embodiment of FIG. 3a).

Here, the method and the method described above are the interpolation method using the two peripheral pixels (the embodiment shown in FIGS. 1a, 2a and 4), and the method is the interpolation method using the four peripheral pixels (the embodiment shown in FIG. 3a). .

As a concrete method, the original image data Y (Fig. 6) sequentially input in synchronization with the data clock DCLK is latched by the DCLK 25.
Can be implemented by using a memory (a delay memory with a DCLK1 pulse period). If there are two pixels, one stage of latch 25 (Figure 1a,
The embodiment shown in FIGS. 2a and 4) can be realized by four stages of latches 25 _{1 to} 25 ₃ (embodiment of FIG. 3a) with 4 pixels.

Next, RAM1 and RAM2 for line memory are used. Here, a group of 2 pixels (the embodiment shown in FIGS. 1a, 2a and 4) or 4 pixels (the embodiment shown in FIG. 3a) is used.
The memory for storing 00 pieces has a two-stage configuration of input and output. When one (RAM1) is input, the other (RAM2) is output, 1
When one line ends, the input and output are reversed. This is because the output a of the T flip-flop 36 which performs the inversion operation by the line synchronization pulse LSYNC is given to the data distributor 26, and when the a is H, the data distributor 26 is used as the A output of the RAM1.
Is designated for writing (W), another output b is given to the data serrata 27, and when b is L, the data selector 27 is used as B output and the RAM 2 is read (R).

Regarding the addresses of the line memories RAM1 and RAM2, at the time of input (write), the address obtained by counting up the counters 38 and 43 in the DCLK cycle is used as is, but at the time of output (read), this address is used. Change. The output address is the original image data sampling position x = Ji immediately before the sampling point i of the scaled image data.

When the sampling point i of the scaled image data is Sij and S
ij ₊₁ and the next sampling point is
When it is between Sij and Sij ₊₁ the read address counter is stopped. When it is moved between Sij ₊₂ and Sij ₊₃ , the read address counter is incremented by ₂ and between Sij ₊₁ and Sij ₊₂ . When it moves to, the read address counter is incremented by 1 as usual.

At the time of enlargement (R ≧ 100), the position of the new sampling point is determined by the operation of advancing the counter by one and the operation of stopping the counter. At the time of reduction (R <100), the position is determined by a combination of an operation of advancing the counter by 1 and an operation of advancing the counter by 2. Since the reduction is considered up to 50% in this apparatus, the counter may be incremented by one or two, but when the reduction is less than 50%, it may be incremented by three or more.

The information on where and how many read address counters to advance is calculated in advance by the microprocessor 35 by the magnification R%. Sampling point i of scaled image data
In the original image data position x immediately before, the starting position is 0, the sampling pitch P of the original image is 1, and the magnification is R.
(%), 100i / R = Ji + Ri (4) i = 0,1,2,3, ... Ji: integer, Ri: decimal integer Ji.

That is, if the sampling point i is between Sij and Sij _{+ 1} , the sampling position x of the original image data will be Ji. Therefore, as i increases, the integer part Ji of 100i / R becomes 1
When the number increases, the read address counter is also incremented by 1,
When the integer part Ji of 100i / R is increased by 2 by the increase of i, the counter is also advanced by 2, and when the integer part Ji of 10i / R is not advanced by 1, the counter may not be advanced. . Further, the fractional part Ri of 100i / R is the distance γ ₁ between Sij and the i corresponding position 0 . This distance data γ ₁ will be used in the subsequent variable-magnification image data calculation.

The microprocessor 35 uses i = 0 to R- in the above equation (4).
Calculate up to 1. That is, the integer J ₀ by the calculation of the equation (4) when i = ₀ and the decimal R ₀ , the integer J ₁ by the calculation of the equation (4) when the i = 1 and the integer J ₁ by the calculation of the decimal R ₁ , i = 2 (4) (4) in the integer J ₂ and the decimal R ₂ , ..., i = R−1 calculated by the formula
Calculates the integer J _R-1 and the decimal R _R-1 by the operation of the expression. Thus, the integer Ji and the decimal fraction Ri only for i = 0 to R-1
By computing only, this can be applied to the entire line length of the original image data. That is, in all cases, the sampling points of the scaled image data have a cycle of every R, so that i =
The value of i = 0 for R, the value of i = 1 for i = R + 1, and the value of i = 1
In the case of = R + 2, the value of i = 2 may be assigned ...

In all the embodiments of the present invention described later, the calculation of Ji and Ri for i = 0 to R-1 is performed before the start of the reading operation by the magnification R.
(%) Is specified, Ji and Ri are converted into data Ai and Bi in a form matching the hardware and written to RAM3 (FIG. 1a) and RAM4 (FIG. 1e). When image reading is started, that is, during zoom processing,
I is incremented by 1 in synchronization with the data clock DCLK, i-compatible data (Ai, Bi) is read from RAM3, and the address is incremented by 1 in synchronization with the line synchronization pulse LSYNC. Then, the data (Ai, B
i) is read from RAM4.

As another embodiment, a dedicated microprocessor for performing the above calculation or an arithmetic means is provided to calculate the equation (4) in synchronization with the data clock DCLK in parallel with the scaling processing, and also the line synchronization clock LSYNC. In sync with (4)
The equation is calculated, and the integer part Ji of 100i / R, that is, the original image data sampling position x and the line sampling position y is directly used as an address, and the decimal part Ri is used as the distance data r ₁ which is a variable image data calculation parameter. It may be used as.

Next, the relationship between the reading of the original image data from the line buffer RAM1 and RAM2 and the calculation of the scaled image data will be described.

The embodiment shown in FIG. 1a, FIG. 2a and FIG. 4 calculates (or) the scaled image data based on the original image data Sij, Sij ₊₁ and Ri of 2 pixels. Line memory RAM1
The original image data of 6 bits are alternately input line by line to RAM2 and RAM2 in synchronization with DCLK as they are, and at this input, Sij is obtained by the latch 25 and Sij ₊₁ is obtained without passing through the latch 25. Then, 6-bit Sij and Sij ₊₁ are arranged side by side to write 12-bit data as 12-bit data in units of lines alternately to RAM1 and RAM2. When one is being written, one word (12 Since the data is read in bit units, the arithmetic unit 28
(6 bits) and Sij ₊₁ (6 bits) are given.

In the embodiment shown in FIG. 3a, latches 25 _{1 to} 25 ₃ in three stages are provided, and the latched data Sij ₋₁ , Sij and Sij ₊₁ and the data Sij ₊₂ not passing through the latches are parallel in 6 bits each. It is combined into a 24-bit word, written to RAM1 and RAM2, and read from them in parallel 24 bits simultaneously. Therefore, the arithmetic unit 28 is provided with Sij _-1 (6 bits), Sij
(6 bits), Sij ₊₁ (6 bits) and Sij ₊₂ (6 bits) are given.

The latches 25, 25 _{1 to} 25 ₃ are connected to the data selector 27 and the arithmetic unit 2
It is also possible to interpose between 8 and read / write only one line of 6-bit data from / to RAMs 1 and 2. By doing this, the transmission of the scaled image data for one line is equivalent to one pixel (in the case of FIG. 1a) or three pixels (in the case of FIG. 3a).
Although delayed, the memory capacity of RAM1 and RAM2 is 6 bits × 1 line pixel number in each case. Therefore, it is effective in reducing the line buffer memory capacity in a usage mode in which a delay deviation of several pixels does not pose a problem.

Here, when the RAM1 is in the write state (a = H, b = L), the address counter 38 advances in a cycle of DCLK in the normal operation, but the RAM1 is in the output state (a = L, A method of setting a read address for reading the image data at the sampling position x (Ji) of the original image data when b = H) will be described.

First, the first method is to change the frequency of the count lock to the address counter. If the frequency of the data clock DCLK is f ₀ , the frequency f at R% scaling is f
_R becomes f _R = f ₀ · 100 / R (Hz) (5).

In this method, the deviation of f _R with respect to f ₀ is also the deviation of the sampling points of the original image and the scaled image, so that it is accurate and reliable. When reading RAM1 and 2, the address counter
The desired combined data can be obtained by operating at f _R and sampling (latching) the outputs of RAM1 and 2 with DCLK again. With this method, the information about the integer Ji in the calculation result of the above-mentioned formula (4) is unnecessary. Then,
In this embodiment, the scaling factor R% is, for example, 50 to 400%, and R
Assuming that the minimum unit of is 1%, 350 pairs of pulses f _R = f ₀ · 100
/ R is required. This is created by a dedicated microprocessor.

The second method is that the calculation result of equation (4) above is an integer.
Focusing on Ji, the previous scaling image data sampling position Xi _-1
And the sampling position Xi this time, (1) When reduced The integer part is increased by one (Ji-Ji _-1 = 1) Ai
= H When the integer part is increased by one (Ji-Ji _-1 = 2), Ai
= L (2) At expansion When the integer part is increased by one (Ji-Ji _-1 = 1) Ai
= H When the integer part is not increased by 2 (Ji-Ji _-1 = 0), Ai
= L, define the sequence [Ai] from i = 0 to R-1,
Write (Fig. 1a) and RAM4 (Fig. 1e) (before reading). This is shown in Figures 1a, 2a, 3a and 4
This is common to all the illustrated embodiments.

Then, in the embodiment of FIG. 4, as the count pulse,
Data clock DCLK and pulse 2D with twice the frequency of DCLK
Prepare CLK. Ai is RAM3 when calculating scaled image data
From i, read is repeated from i = 0 to R-1. In the embodiment shown in FIG. 4, the reduction time (R <10
0), the count pulse of the address counter (38 or 43) for reading the line memory (RAM1 or RAM2) is switched so as to be DCLK when Ai = H and 2DCLK when Ai = L. When enlarged (R ≧ 100), the count pulse of the address counter 38 or 43 is Ai and DCLK.
By using AND (logical product), the count-up is performed when Ai = H and the count is not performed when Ai = L.

All embodiments of the present invention have RAM3 and RAM4, which store the aforementioned Ai based on the result of equation (4) calculated by the microprocessor 35. These RAM3 and
The RAM 4 also stores data Bi that is different in each embodiment. The contents of Bi will be described later.

In this way, Ai is stored in RAM3 and RAM4 before image reading, and during image reading, Ai and Bi are read in synchronization with data clock DCLK from RAM3 and line clock LSYNC from RAM4. , Ai, the read address in the main scanning direction X is set, and the adjacent data Sij and Sij ₊₁ are simultaneously read from the RAM1 and RAM2 (the embodiment of FIGS. 1a, 2a and 4) or simultaneously. Data Sij _-1 ,, Si
Along with the fact that j, Sij ₊₁ and Sij ₊₂ are read out (the embodiment of FIG. 3a), the configuration of the computing unit 28 for computing the scaled image data becomes simple, as will be described later. The data Ai read from the RAM 4 defines the extraction position of the line data in the sub-scanning direction Y.

In the count pulse switching method of the embodiment shown in FIG. 4, when the enlargement (R ≧ 100) and Ai = L, the ENABLE of the counters 38 and 43 is enabled.
The terminal may be set to L to stop counting.

The third method is carried out in the embodiment shown in FIG. 1a. The address counters 38 and 43 themselves use the data clock DCL.
Continue counting up by K. In addition to the address counters 38 and 43, another up / down counter 39 and 44 is provided to specify down when expanding (R ≧ 100) and specify up when reducing (R <100). Then, the up / down counters 39 and 44 input the AND (logical product) of DCLK and Ai so as to count only when Ai = L.

As a result, for example, at the time of reduction, first, the up / down counters 39 and 44 are set to 1 when Ai = L, the adders 37 and 42 add 1 to the values of the address counters 38 and 43, and the RAM1 and RAM2 are read. Address. Further, at the next Ai = L, the up / down counters 39 and 44 are set to 2, and the count values of the address counters 38 and 43 are added to determine the position x (Ji) of the sampling point.

In the case of enlargement, it is necessary to read the read address without shifting it. At this time, the address counters 38 and 43 count up. To compensate for this, conversely, 1 is set at Ai = L.
Up / down counter 39,44
Is subtracted.

Next, the calculation method of the scaled image data (scaled image data calculation in the main scanning direction X) will be described. The embodiment shown in Figure 1a is for carrying out the method described above, the embodiment shown in Figure 2a is for carrying out the method described above, and the embodiment shown in Figure 3a is described above. That is what you do. A method of executing these methods will be described.

 Closest pixel setting method (embodiment of FIG. 1a) The calculation method of this method is relatively simple.

In FIG. 5, one of Sij and Sij ₊₁ that is closer to the scaled image data sampling position i ( 0 in FIG. 12) may be selected.

When the integer Ji and the decimal fraction Ri are calculated by the microprocessor 35 based on the equation (4), the decimal fraction Ri is 0 and Sij.
If r ₁ / P (P is the sampling pitch of the original image data, P = 1 in the embodiment) is 0.5 or less, Sij is selected, and if larger than 0.5, Sij ₊₁ is selected. Good. In the embodiment shown in FIG. 1a, the microprocessor 35
When calculating Ji and Ri and calculating Ai described above, if r ₁ / P is 0.5 or less, Bi = H is set, and if it is larger than 0.5, Bi = L is also calculated. RA with Ai
Write to the same address on M3. This is a process before image reading. When image reading starts, data clock DCLK
In synchronization with, Ai and Bi are read from RAM3, Bi is used as a select signal, Sij is selected when Bi = H, and Sij is selected when Bi = L.
₊₁ is selected as the data selector of the arithmetic unit 28 in this embodiment.
Feed to 80XA (Fig. 1d).

Proximity pixel distance linear allocation method (Fig. 2a) This method becomes more complicated. This is because the formula (1) must be calculated. In this case, the problem is the accuracy of the distance r ₁ / P or r ₂ / P. It is up to the first decimal place, that is, it should be considered in steps of 0.1, or it is necessary to look at it in more detail, or whether P is divided into four, that is, in steps of 0.25. This problem is how much accuracy is required as a digital copier system or a facsimile system, and corresponds to the required image quality in the digital copier or facsimile system. From the viewpoint of arithmetic processing, r ₁ / P and r ₂ / P are preferable because they are reciprocals of powers of 2. This is because operations such as 1/2, 1/4, 1/8, etc. can be performed only by bit shifting the target data. Therefore, firstly, divide Ri = r ₁ / P into 0.25 (1/4) steps based on the calculation result of equation (4). That is, the minimum unit of Ri is 1/8, and Ri
The area division of is set to 1/4. As an example, try dividing as follows.

When 0 ≦ r ₁ / P <1/8, Ri = r ₁ / P = 0, Bi = 0 1/8 ≦ r ₁ / P <3/8, Ri = r ₁ / P = 1/4 , Bi = 1 3/8 ≦ r ₁ / P <5/8, Ri = r ₁ / P = 1/2, Bi = 2 5/8 ≦ r ₁ / P <7/8, Ri = r ₁ / P = 3/4, Bi = 3 Here, when 7/8 ≦ r ₁ / P <1, it means that 0 and Sij ₊₁ are at the same position. = 4
However, in this case, since 3 bits are required for Bi, in this case, from the hardware configuration, x is incremented by 1, the integer Ji is increased by 1 and the decimal fraction Ri is set to 0.
Then, it is preferable that 0 is between Sij ₊₁ and Sij ₊₂ and Bi = 0, since Bi can be a 2-bit signal. Similar to the above, this Bi is written together with Ai at the same address in RAM3 and RAM4.

In Fig. 2a which implements this method, by the distance (Bi = 0 to 4) divided into four, A · Sij + B · Sij ₊₁ = Oik (6), where A corresponds to r ₁ / P Coefficient, B is a coefficient corresponding to r ₂ / P, Sij, Sij ₊₁ is the content of 6-bit data, and Oik is the content of scaled image data (6 bits).

Since A and B are determined, the X direction variable-magnification image data calculator 80XB in FIG. 2a calculates four types of A.Sij and B.Sij ₊₁ and selects one of them for Bi data selector. 28b, 28
It is selected by c and added by the adder 28d to obtain the scaled image data Oik.

In the embodiment shown in FIG. 2a, the coefficients A and B corresponding to Bi are
Are set as shown in Table 1 below.

Since the reciprocal of a power of 2 such as 1/2, 1/4 can be obtained only by bit shifting the signal line, the hardware configuration becomes very easy.

A modified example of the X-direction scaled image data calculator 80XB shown in FIG. 2a is shown in FIG. 2c. The X-direction scaled image data calculator 80XB shown in FIG. 2c is composed of the ROM 28g. The scaled image data Oik determined by Sij (minimum value of 6 bits to maximum value), Sij ₊₁ (minimum value of 6 bits to maximum value) and Bi is calculated in advance and written in the ROM 28g. At the time of image reading-magnification processing, the magnified image data Oik is read using Sij and Sij _{+ 1} as addresses of the ROM 28g.

Sij is 6 bits, Sij ₊₁ is 5 bits (since coefficient B is 1 or less, only the upper 5 bits are required), and Bi is 2 bits.
The ROM 28g can be an 8k × 8 bit ROM with an address of 13 bits, so the calculations to be performed in advance can be performed without much difficulty. The hardware configuration for calculating the scaled image data becomes very simple.

Cubic function convolution This method requires extremely complicated calculation as shown in the above equation (3) and is not suitable for hardware implementation. You can make a good scaling.

Similar to the case of this method, there is a problem of distance accuracy, but here also the case where γ ₁ / p is divided into four is considered.

The division method is exactly the same.

If the above formula (3) is simply rewritten, A · Sij ₋₁ + B · Sij + C · Sij ₊₁ + D · Sij ₊₂ = Oik ……
(7) Note that the denominator of equation (3) is a normalization coefficient and can be excluded from the parameters.

From the above equation (2), A, B, C and D are calculated in the four cases of γ ₁ / P = 0, 1/4, 1/2, 3/4 as follows.

Based on this coefficient, four cases of A · Sij ₋₁ and B are obtained in the same manner as in the case of X-direction scaled image data calculator 80XB in FIG.
There is a method in which Sij, C, Sij ₊₁ and D, Sij ₊₂ (Sij etc. are 0 to 63) are prepared and selected one by one by Bi to add four. However, in this case, unlike in the case of, each calculation is slightly troublesome, and the hardware becomes a little complicated.

Therefore, in order to reduce the burden on the hardware as much as possible,
Coefficients A, B, C and D are approximated as in Table 2 below and rewritten. However, at this time, it is necessary that A + B + C + D = 1.

In this case, the denominator of the coefficient is 8 or less, and the coefficient by hardware becomes much easier. The X-direction variable-magnification image data calculator 80XC shown in FIG. 3a is adapted to perform the variable-magnification image data calculation using the coefficients shown in Table 2.

In this example also, the X-direction scaled image data calculator 80XC
It is possible to use a ROM as shown in Figure 2c. When doing so, ROM 63 is used as shown in FIG. 3c.

The address of ROM63 is 3 bits for Sij _-1 , 6 bits for Sij,
5 bits for Sij ₊₁ , 3 bits for Sij ₊₂ , 2 bits for Bi,
The total is 17 bits. Since the amount of memory becomes 128 kbytes, it is a little difficult to calculate the data to be stored in the ROM 63 in advance. However, this method also simplifies the hardware for calculating the scaled image data.

Next, the NTF correction will be described.

In the first method, the correction coefficient is set in advance corresponding to the magnification. That is, the MTF correction calculation formulas in which the correction coefficients (filter coefficients) shown in FIGS.
Then, specify one of them and correct the MTF. Immediately after calculating the scaled image data in the main scanning direction (data selector 80 in FIG. 1d).
The output of XA, the output of the X-direction scaled image data calculator 80XB in FIGS. 2a and 2c, and the output of the X-direction scaled image data calculator 80XC in FIGS. 3a and 3c) Since no scaling processing is performed, only MTF correction in the X direction is performed.

The correction coefficients (filter coefficients) V to Z shown in FIG.
From the image data distribution shown in Fig. 3b, M of the image data of interest Oik
TF corrected value Mik _{is, Mik = Y · Oi -1 k} + V · Oik -1 + W · Oik +1 + Z · Oi -1 k +
X ・ Oik …… (8) Since this is at _{Mik = V · Oi -1 k +} W · Oik +1 + X / 2 · Oik + Y · Oik -1 + Z · Oi -1 k + X / 2 · Oik, the MFT correction in the X direction only, Mik = V・ Oik _-1 + W ・ Oik _-1 + X / 2 ・ Oik ・ ・ ・ (9) should be MTF corrected value. In the MFT correction only in the Y direction, Mik = Y · Oi ₋₁ k + Z · Oi ₋₁ k + X / 2 · Oik (10) may be set as the MFT-corrected value.

Therefore, the X-direction MFT correction calculator 1 of the first embodiment shown in FIG. 1d
In 10XA, four sets of MTF correction calculation formulas in which the correction coefficients shown in FIGS. 14a, 14b, 14c and 14d are substituted into the formula (9) are executed to obtain the specified magnification R. The value calculated by the corresponding calculation formula is extracted by the data selector 98. The second embodiment shown in FIG. 2a and the third embodiment shown in FIG. 3a are also arranged to perform MTF correction in this way.

In addition to the above-described method of changing the correction coefficient, the second method is to perform an operation that also takes MTF correction into account when calculating the scaling.
H (r) in FIG. 6 is an interpolation function used in the variable-magnification image data calculation (described above) when the MTF correction of the input system is 100%. However, the actual scan rate is about 10-40%, though it varies depending on the reading speed and density. Approximately 15 for Sukiana SCR, which is the target of the examples described
%, And the frequency response H (ω) is approximately the curve shown in FIG. This curve is The interpolation coefficient h (r) obtained by this Fourier transform is shown in FIG. By using this h (r) to obtain Oik by the equation (3), the scaling process is performed in the form of MTF correction. Here, as in the case of the method, the coefficients A to D of the equation (7) are obtained by dividing into four of r ₁ / P = 0, 1/4, 1/2, 3/4. In this case, it approximates to a count that is simple in hardware and easy to calculate. At this time, with Sij
If the positions of 0 match, Sij _-1
The term is also required, and in the end, E · Sij ₋₂ + A · Sij ₋₁ + B · Sij + C · Sij ₊₁ + D · Sij ₊₂ ＝ Oik …… (11). This Oik is the X-direction MTF-corrected scaled image data Mik because it has been subjected to the scaled image data calculation in the X direction and the MFT correction.

The coefficients A to E are as shown in Table 3 below.

This is done by using one more coefficient than in the case of the X-direction scaled image data calculation using the coefficients in Table 2 (the embodiment of FIG. 3a) and the X-direction scaled image data calculation and X-direction calculation.
It shows that the direction MTF correction calculation can be performed at the same time. The X-direction variable-magnification image data calculation that has been subjected to MTF correction based on the coefficients shown in Table 3 is performed in the embodiment shown in FIG. 3d.

The variable-magnification image data calculation and the MTF correction calculation in the main scanning direction X have been described above. The scaling image data calculation in the sub-scanning direction Y and the MTF correction calculation are similarly performed. The difference between the two is whether the original image data is calculated by focusing on the arrangement in the main scanning direction X or by calculating the arrangement by focusing on the arrangement in the sub-scanning direction Y.

Next, the hardware configuration and operation of the embodiment of the present invention will be described.

First Embodiment (FIGS. 1a to 1e) In the first embodiment shown in FIG. 1a, the original image data read by the scan scanner SCR is sent line by line to the shading correction circuit 24 in one line of data. Is given serially in units of parallel 6 bits (6 bits are 1 word indicating the density of 1 pixel), and the circuit 24 has a similar data structure and a similar transfer format, and the line sync pulse LSTN
One line is supplied to the latch 25 and the data distributor 26 in synchronization with the data clock DCLK for one line during one cycle of C. The output of the circuit 24 is the data of a pixel
When Sij _{+ 1} , the output of the latch 25 is the data Sij one pixel before, and these data Sij and Sij _{+ 1} are given to the data distributor 26 in parallel 12 bits.

On the other hand, the T flip-flop 36 outputs the line synchronization pulse LSYN.
Since the signal level of its output Q, Q is inverted every time one pulse of C arrives, for example, when the data of the first line is given, the data distributor 26 gives the input 12 bits to RAM1 and RAM1. Is designated for writing. At this time, the data selector 27 gives the 12-bit data of the input terminal B to the arithmetic unit 28, and the RAM 2 is designated for reading. When the data of the second line is supplied to the data distributor 26, the data distributor 26 supplies the input 12 bits to the RAM2, and the RAM2 is designated for writing. At this time, the data selector 27
12-bit data is given to the arithmetic unit 28, and RAM1 is designated for reading.

In this way, the data of two adjacent pixels on the n-th line are written in parallel in RAM1. During that time, the data of the adjacent two pixels of the (n-1) th line are read out in parallel from the RAM2.
The data of the adjacent two pixels of the (n + 1) th line is RAM2 in parallel.
The data of two adjacent pixels on the n-th line are read from the RAM 1 in parallel during the writing. Similarly, RAM1 and
The RAM2 is switched by the line synchronization pulse LSYNC and alternately designated for writing and reading. In this way
Data of adjacent two pixels on the n-th line are combined in parallel
When writing 12-bit data to RAM1 or RAM2,
12-bit data obtained by combining the data of adjacent two pixels of the (n−1) th line in parallel is read from RAM2 or RAM1 and given to the arithmetic unit 28. That is, the arithmetic unit 28 has a circuit
One line later than the data output by 24,
The original image data is given in a form of arranging the data of two adjacent pixels. In this way, the data buffer memory RAM1, RAM2
The reading of data from that input is delayed by one line.

The read / write address of RAM1 is determined by the sampling circuit 64, and the read / write address of RAM2 is determined by the sampling circuit 65.

First, the sampling circuit 64 will be described. When the RAM 1 is designated for writing, the signals a = H, b = L, the AND gate 40 is off (gate closed), and the up / down counter 39 receives a count pulse. If not given, its output remains at 0. Since the data clock DCLK is given to the address counter 38 as a count pulse, it is incremented by 1 each time one pulse of the data clock DCLK arrives. The adder 37 adds the count data of the counters 39 and 38 and gives the sum data to the RAM 1 as address data. As a result, the 12-bit data obtained by parallelizing the data of two adjacent pixels becomes the data clock.
Data is sequentially written to RAM1 in synchronization with DCLK. Ie 1
All data for the line is written to RAM1.

When RAM1 is designated for reading, a = L, b =
Since it is H, the AND gate 40 is turned on (gate is opened) when the signal c is L, and the up / down counter 39 is supplied with the data clock DCLK as a count pulse. Signal d
= H (reduction), up-counting, and d = L (enlargement), down-counting. The signal c is the data Ai described above and controls the stop / progress of counting. At the time of reading, the sum of the count values of the counters 39 and 38 becomes the read address of the RAM1. c =
In the case of L, the counter 39 counts up by 1 every time DCLK appears 1 pulse when d = H, and the read address of the RAM 1 advances by 2. When d = L, the counter 39 appears each time DCLK appears 1 pulse. 1 countdown, RA
Note that the read address of M1 stalls.

c = Ai.

The sampling circuit 65 has exactly the same configuration as 64, except that the a signal is applied to the AND gate 45 instead of the b signal. This is because when RAM1 is read (b = H, a = L), RAM2 is write and RAM1 is written (b = L, a).
This is because the RAM 2 is read out when H = H) and the read address is the sum of the count values of the counters 44 and 43.

Here, Ai will be described. The microprocessor 35
In response to the image reading start instruction (ST changes from L to H), the specified scaling ratio R% is read, and based on this, i
For each of = 0 to R−1, Ji and Ri are calculated. When R <100 (reduction), Ji-Ji ₋₁ ≧ 2 and Ai and L, and Ji-Ji ₋₁ ≦ 1 If Ai is H and R ≧ 100 (enlargement), Ji-Ji ₋₁ ≧ 1 and Ai is H, and if Ji-Ji ₋₁ ≦ 0, Ai is L, and if Ri ≦ 0.5, Bi is H, and when Ri> 0.5, Bi
Is L, Ai and Bi are RAM3 (FIG. 1a) and RAM4
The data is stored in the address R-i (Fig. 1e). In this memory operation, the microprocessor 35, i = 0 data A ₀ and B ₀ corresponding giving one pulse to the OR gate 49 before writing, loading data representing the R in the address counter 48. When A ₀ and B ₀ are given to the RAM 3, one pulse is given to the OR gate 51, the address counter 48 is incremented by _1, and the data A ₁ and B ₁ corresponding to i = 1 are given to the RAM 3 and then the OR gate 51. Give 1 pulse to. Such an operation is performed until i = R-1. Accordingly, the data A ₀ and B ₀ of the address 0 to i = 0 corresponding RAM 3, i = 1 corresponding data A ₁ and B ₁ in the address 1, ... Address R-1 to i = R-1 Corresponding data A _R-1 and B _R-1 are written.

Then, when the image reading is instructed to the scanning SCR and the image reading is actually started, the data indicating the designated magnification R% is set in the address counter 48 by the line synchronization pulse LSYNC, and every time the data clock DCLK appears one pulse. The counter 48 increments by 1 and the read address is incremented by 1 each time DCLK appears, i =
0 corresponding data A ₀ and B ₀ to i = R-1 corresponding data
A _R-1 and B _R-1 are sequentially read, the data Ai is given to the sampling circuits 64 and 65 as the signal c, and the data Bi is given to the data selector 80XA of the arithmetic unit 28.

The data selector 80XA selects Sij when Bi = H and S when Bi = L.
ij ₊₁ is output as the scaled image data Oik. This output operation is synchronized with the data clock DCLK.

The scaled image data Oik obtained by scaling in the X direction is supplied to the X direction MTF correction calculator 100XA, and the scaled image data Mik corrected in the X direction MTF is supplied to the sub-scanning scale calculator 29. Circuit 2
In 9, the scaling processing in the sub-scanning direction Y and MTF correction are applied,
It is given to the binarization circuit 30 and the gradation processor 31. In this embodiment, the gradation processor 31 includes 64 kinds of ROMs having gradation distribution data distribution patterns corresponding to density, a cyclic line counter initialized by 64 counts, and cyclic data initialized by 64 counts. It has a clock counter, and the read address of the ROM is set by Oik, line count data, and data clock count data. That is, one pattern of ROM is specified by Oik,
The main scanning address of the pattern is specified by the data clock counter and the sub-scanning address is specified by the line counter, and the 1-bit image data in the pattern is read. When the microprocessor 35 gives an instruction to output binarized data (i = H), the gate circuits 32 to 34 cause the binarization circuit 30 to operate.
When the gradation data output is instructed (i = L), the output of the gradation processor 31 is output to the printer PRT.

In the X-direction MTF correction calculator 100XA, the latch 81 delays the scaled image data (Oij) by one cycle of the data clock DCLK,
Further, the latch 82 delays by one cycle. As a result, the scaled image data Oik _-1 and O for executing the equation (9) are obtained.
ik is obtained from latches 82 and 81 and is
You get Oik ₊₁ . These data are given to the XMTF calculator 100XA.

In the adder 83 of the XMTF calculator 100XA, there are data (2.Oik) obtained by shifting all 6 bits of Oik to the upper bits by 1 bit (2.Oik) and data obtained by extracting only the upper 5 bits of all 6 bits (1 / 2.Oik). Given, the adder 83 adds the data indicating 5/2 · Oik to the adder 94
Give to. The adder 84 gives the data showing the sum of Oik ₋₁ and Oik ₊₁ to the complementer 90. The complementer supplies the adder 94 with data indicating − (Oik ₋₁ + Oik ₊₁ ). As a result, the adder 94
Gives the MTF correction calculation value obtained by substituting the coefficient shown in FIG. 14a into the equation (9) to the input terminal A of the data selector 98.

The adders 85, 86, the complementer 91 and the adder 95 give the MTF correction operation value obtained by substituting the coefficient shown in FIG. 14b into the equation (9) to the input terminal B of the data selector 98.

The adder 87, the complementer 92, and the adder 96 give the MTF correction calculation value obtained by substituting the coefficient shown in FIG. 14c into the equation (9) to the input terminal C of the data selector 98. Also, adder 88, 89, complementer
The 93 and the adder 97 give the MTF correction calculation value obtained by substituting the coefficient shown in FIG. 14d into the equation (9) to the input terminal D of the data selector 98.

On the other hand, the microprocessor 35 checks the designated magnification R immediately before image reading, and when R <100, outputs the selection instruction data RR for setting the A input to the output to the data selector 98, and 100 ≦ R <200. In the case of, the selection instruction data RR for setting the B input to the output is output to the data selector 98, and 20
When 0 ≦ R <300, the selection instruction data RR that sets the C input to the output is output to the data selector 98, and when 300 ≦ R, the selection instruction data RR that sets the D input to the output is output to the data selector 98. To do.

As a result, the scaled image data Mik calculated by the MTF correction coefficient according to the designated magnification R is obtained, and the sub-scanning scaling calculator 29
Given to.

Next, the configuration of the sub-scanning scaling calculator 29 will be described with reference to FIG. 1e.

The scaled image data Mik subjected to the scaling operation and the MTF operation in the main scanning direction X is supplied to the gate 103 of the sampling circuit 65Y in synchronization with the data clock DCLK.

RAM4 is written simultaneously with writing Ai and Bi to RAM3. When reading an image, the address counter 48Y counts the line clock LSYNC to determine the read address of the RAM 4. So here Ai and Bi are line clocks instead of data clock DCLK.
I is set to 1 for each LSYNC pulse (as the sub-scan progresses)
The larger value (Ai, Bi) is read from RAM4. Address counter 43Y of sampling circuit 65Y, up-down count 44Y, AND gate 45Y and adder 42Y
Is a sampling circuit 65 in the main scanning direction (1a
The configuration is similar to that of the figure), but the line clock LSYNC is counted instead of the data clock DCLK. That is, the sampling position Y in the sub-scanning direction is determined. The count data of the address counter 43Y indicates the sub-scanning position starting from the start of image reading of one page, and the output data of the adder 42Y indicates the sampling position y in the sub-scanning direction. When the two data match, that is, when the sub-scanning position for image reading matches the sampling position y, the comparator 102 gives an H output to the latch 129 and the OR gate 130. Since the output of the latch 129 is also given to this OR gate 130, the OR gate 130
When the image scanning line No. is Ji (y) and Ji ₊₁ (y +
In the case of 1), the gate-on signal (H) is sent to the data gate 103,
And give to AND gates 108,109. It should be noted that the OR gate 130 generates the gate open signal (H) during the arrival of data on the line at the sampling position Ji (y) and the next line.

On the other hand, the data Bi read from the RAM 4 is set in the latch 131, and the OR gate 132 outputs the same data Bi over the section of two lines.

Scale calculator 80Y corresponding to the data selector 80XA in Fig. 1d
The RS flip-flop 104 outputs a signal s that becomes H when the image sub-scanning position reaches the sampling position Ji (y).
Is set at the rising edge of and is reset by the signal t which becomes H at the next LSYNC. That is, the flip-flop 104
Is set when the sub-scanning position reaches the sampling position (y), and is reset when the sub-scanning advances next. OR gate 132 over 2 lines (adjacent 2 lines) when this set is set and when it is subsequently reset
Since the same data Bi is output, the AND gate 105 that receives the output Q of the flip-flop 104 is set by the signal s, and the data Bi is high.
At the time of (instruction to select the preceding line of the two adjacent lines), the output of H is output to the data gate 103 through the OR gate 107.
And give to AND gates 108,109. The AND gate 106 receiving the Q output of the flip-flop 104 is reset by the signal t in the flip-flop 104, and the data Bi is L.
When it is (instruction to select a subsequent line of two adjacent lines), H is output, and the data gate 1 is output through the OR gate 107.
Give to 03 and AND gate 108,109. The gate 103 and the AND gates 108 and 109 are
When the image sub-scanning is the sampling line No.y (Ji), the gate is opened only for one line section, and when the data Bi is L, the image sub-scanning is the sampling line No.y (Ji).
When the next line y + 1 (ji + 1) is reached, the gate is opened only for one line section. In this way, the data Bi
When H is H, the data of the line No. y indicated by Ji calculated by the equation (4) is stored in the memory 29 for one line. When the data Bi is L, the data of the line No. y + 1 next to Ji is stored in the memory 29 for one line.

The above is the calculation of the scaled image data in the sub-scanning direction (in the first embodiment, selection of one line of the sampling line and the next adjacent one line).

Next, the MTF correction in the sub-scanning direction will be described.
(0), the scaled image data subjected to MTF correction in the sub-scanning direction (that is, the scaled image data setting in the main scanning direction and the sub-scanning direction is completed here, and the MTF in the main scanning direction is
Since the correction has been completed, obtain the final data which has completed all the scaling processing and MTF correction). The line buffers 81Y and 82Y each store one line of the scaled image data that has undergone the scaling processing in the main scanning direction and the sub-scanning direction and the MTF correction in the main scanning direction. Buffer 82
If the output image data of Y is Mi ₋₁ k, the output image data of the buffer 82Y is Mik one line after that, and the image data that arrives at the input end of the buffer 82Y is one line after Mik. Mi ₊₁ k. These are the X's shown in Figure 1d.
It is given to the YMTF calculator 100Y, which has the same configuration as the MTF calculator 100XA, and the YMTF calculator 100Y converts Oik _-1 to Mi _-1 k and Oi shown in Fig. 1d.
Substitutions of k for Mik and Oik ₊₁ for Mi ₊₁ k (Equation 10 substituting the coefficients of FIGS. 14a, 14b, 14c, and 14d) ) Is calculated and the data showing the one solution is output. This output is the scaled image data for which the scaling processing in the main scanning direction and the sub-scanning direction has been completed, and the scaling processing in the main scanning direction and the sub-scanning direction has been completed.

Looking at the correspondence between the elements of FIG. 1e and the elements of FIGS. 1a and 1d, the latches 129, 131 and the OR gate 13 of FIG.
0, 132, 133, scaling calculator 80Y and data gate 65Y
This is a sub-scanning direction scaling operation means corresponding to the main scanning direction scaling operation means comprising a combination of the sampling circuit 65 of FIG. 1a and the data selector 110XA of FIG. 1d. The buffer memories 81Y and 82Y in FIG. 1e correspond to the latches 81 and 82 in FIG. 1d for obtaining a data delay of one pixel in the main scanning direction,
A line buffer memory that obtains a data delay of one pixel in the sub-scanning direction. The YMTF computing unit 100Y of FIG. 1e executes the computation (4 sets) of the equation (10) shown in FIGS. 14a to 14d, which has the same configuration as the XMTF computing unit 100XA shown in FIG. 1d. It is an arithmetic unit that outputs data indicating a set of arithmetic solutions.

Next, the scaling control operation of the microprocessor 35 will be described with reference to FIGS. 1b and 1c. First, refer to FIG. 1b.

Microprocessor when power is turned on (step 1)
Reference numeral 35 sets the input / output port to the standby state level and clears the internal registers, counters, timers, flags, etc. (step 2: hereinafter, the word step is omitted in parentheses).

Next, the data R designating the designated scaling ratio R% is read and stored in the register Rs (3), and L is set to the output port g (4). That is, the AND gate 50 is turned off (gate closed), and the address counter 48 is set so that the count pulse is not given from the outside. Next, output port n
Then, the data indicating the designated scaling ratio Rs% stored in the register Rs is set (5) and added to the preset data input terminal P of the address counter 48. Then, one pulse is output to the output port f (6) and the address counter 48 is loaded with Rs. As a result, the address counter 48 is initialized (initial address setting).

Next, the microprocessor 35 sets the RAM 3 for writing (7) and sets the contents of the internal address register i to indicate 0 (register clear) (8). As a result, the above i = 0 is set. Next, the register j is cleared and H is set in the registers Bi and Ai (9). Then, the contents Bi and Ai of the registers Bi and Ai are stored in the RAM 3 (10). At this stage, since i = 0, B ₀ = H and A ₀ = H are written in the address R of RAM3. Then, the contents of register i are incremented by 1 (1
1). This means that the value of i has been changed to a value one greater than the previous value. Next, i is 2 or more (2 at this stage)
Therefore, 100i / Rs = Ji + Ri integer Ji and fractional Ri
Is calculated (13), the contents of the current calculation value register ji are transferred to the previous calculation value register ji _-1 (14a), and the current calculation register j
The integer Ji is stored in i (14b), and then steps 15 to 17 are performed.
To set Bi, and in steps 18 to 25 set Ai. Then, one pulse is output to the output port h (22), the write address of RAM3 is incremented by one, the write address is advanced, and in step 10, RAM3 is set to the previously set Bi and Ai.
Write in. Similarly, change i to a value 1 larger (1
1) Calculate Ji and Ri (13), set Bi and Ai based on them and Rs (15 to 25), update RAM3 write address (22), and write Bi and Ai to RAM3. (1
0). In this way, when i = Rs + 1, i = 0 to Rs
Since all of Bi and Ai corresponding to -1 have been written in the RAM 3, the process proceeds from step 12 to the scaling processing control at the time of image reading in FIG. 1c. It should be noted that when the process proceeds from step 8 to step 9, A ₀ = H is written in the address 0 of the RAM 3, but this does not correspond exactly to Ji-Ji _-1 . Because
This is because Ji _-1 is unknown at this stage. But i
Is set to Rs−1, the next (i = Rs)
Since the counter 48 is initialized by a carrier indicating Rs count over and i is returned to 0, i = 0 and i = Rs are the same. Therefore, the operation of A _{0 at} i = 0 can be replaced with that of i = Rs. And may be used J _R-1 in the case of i = Rs-1 as Ji _-1. Therefore, in step 12, until i = Rs, Ai
And seeing how Bi has completed and memory to RAM3 has completed. That is, it is sufficient to store Ai, Bi from i = 0 to Rs−1, but even if i = Rs (this is synonymous with i = 0), Ai, Bi
Is calculated and stored in memory. In this i = Rs,
Since the counter 48 counts over Rs and sets the write address of RAM 3 to 0, B ₀₁ and A ₀ written in step 9 are rewritten to B _R s and A _R s. As a result, A ₀ written in steps 9 and 10 is updated to an accurate value.

When the process proceeds from step 12 to the variable-magnification processing control at the time of image reading in FIG. 1c, it waits until the image reading start instruction signal ST becomes H for instructing the reading start (26), and until the reading start instruction arrives. , Reads the input magnification instruction data R and checks whether it is the same as the value stored in the register Rs (27). If they are not the same, the designated magnification R has been changed, so return to step 3 in FIG. 1b, and similarly, calculate the data Bi and Ai corresponding to the new designated magnification R and write them to the RAM3. To do.

When the image reading start instruction signal ST goes high, the scan SC
Check if R is ready (28), check if printer PRT is ready (29), and wait for both to become ready if either is not ready.

If both SKYANA SCR and printer PRT are ready, 2
If value image processing (document: text image processing) is instructed, set H to the output port i (31) 2
The gate circuits 32 to 34 are set so as to give the output of the binarization circuit 30 to the printer PRT, and when gradation image processing (photographic image processing) is instructed, L is set to the output port i (32 The gate circuits 32 to 34 are set so that the output of the gradation processor 31 is given to the printer PRT. Next, the microprocessor 35 refers to the content of the designated scaling register Rs to check whether reduction is designated or enlargement is designated (33), and when reduction is designated, the output port d
Is set to H (34), and the up-down counters 39 and 44 are set to up-count. When enlargement is designated, L is set to the output port d (35) and the up / down counters 39 and 44 are set to down count.

Then, the designated magnification R is R <100,100 ≦ R <200,200 ≦ R
Check whether the range is <300 or 300 ≦ R (51, 53, 55, 57), and when R <100, XMTF calculator 10
0XA (data selector 98) and selection instruction signal RR to YMTF calculator 100Y that sets A input to output (14th
XMTF calculator 10 is set (52) for instructing the output of the calculated value based on the coefficient in Fig. a (52), and when 100 ≤ R <200.
0B (data selector 98) and YMTF computing unit 100Y select instruction signal RR that sets B input to output (14th)
(54) to output the calculated value based on the coefficient (54), and when 200 ≦ R <300, XMTF calculator 100X
A selection instruction signal RR to A (data selector 98) and YMTF calculator 100Y is set to output C input (14c)
(56), and when 300≤R, the selection instruction signal RR to (the data elector 98 of XMTF calculator 100XA) and YMTF calculator 100Y is set. , D input is set to output (instruction to output the calculated value based on the coefficient of FIG. 14d) (57).

Next, the RAM 3 is set to read (36), H is set to the output port g (37), and the AND gate 50 is turned on (gate open). Next, an H-level start signal ATS is given to the scan SCR and printer PRT (38).

Scanner SCR starts image reading in response to ATS going high, and outputs line sync pulse LSYNC, data clock DCLK, and original image data serially line by line. For example, odd line data Is written to RAM1,
When the even line data is written to RAM2 and the odd line data is written to RAM1, the even line data is read from RAM2 and the even line data is
When written to RAM2, the odd line data is RA
Read from M1. That is, the original image data is written in the line buffer memories RAM1 and RAM2 in the form shown in FIG.
Also read from it.

During this image reading, the address count 48 is initialized by the line synchronization pulse LSYNC and the count-over signal generated by itself (generated every time when counting the specified magnification Rs%), and then the data clock DCLK.
To count up. This allows the address counter 48
The address given to RAM3 becomes 0 when the line synchronization pulse LSYNC arrives for one pulse, and sequentially increases by 1 each time one pulse of DCLK appears. The address counter 48 is next to the maximum number Rs-1. Next to the count-over of, the address counter 48 is initialized by the count-over and becomes 0 again, and becomes 1 every time DCLK arrives. This is repeated during one cycle of the line sync pulse LSYNC. RAM3 is set to read, so Ai and B
i, i = 0 to R−1, are sequentially read from RAM3 from i = 0, and when i = R−1, they are read again from i = 0, and so on, sequentially in synchronization with DCLK. After being read, Ai is given to the inverters 41 and 46 as a signal c, and Bi is given to the data selector 28a.

c = Ai = H (Ji-Ji _-1 ≤ 1 when reduced, Ji-Ji _-1 ≥ when enlarged
In the case of 1), since the AND gates 40 and 45 are turned off (gate closed), the count values of the counters 39 and 44 do not move,
The scaled image data is sampled at the same sampling pitch as the sampling pitch (P = 1) of the original image data. In this period, the image magnification is 1. That is, the scaled image data becomes the original image data (not thinned or written twice).

c = Ai = L (Ji-Ji _-1 ≧ 2 when reduced, Ji-Ji _-1 <when expanded
In the case of 1), since the counters 39 and 44 are up-counting at the time of reduction, since the counters 39 and 44 are counting up in the same way as the address counters 38 and 43 are counting up, one pulse of DCLK Upon arrival, the read addresses of RAM1 and RAM2 are increased by 2, and the original image data is sampled in every one pixel. Counter when expanding
Address counter 3 because 39 and 33 are down-counting
Since counters 39 and 44 count down in contrast to 8 and 43 count up, the read address of RAM1 and RAM2 does not move even when DCLK arrives, and the data of the same pixel of the original image data should be repeatedly sampled. become.

By the above sampling operation, the original image data is sampled at the pitch corresponding to the designated magnification R, and Bi = H (Ri
When ≦ 0.5), the data selector 28 sets Sij of the sampled original image data to OiK, and Bi = L (Ri> 0.
In the case of 5), the data selector 28 outputs Sij _{+ 1} of the sampled original image data as Oik. The original image data sampled in this way is the XMTF calculator 110X.
At A, the MTF in the main scanning direction is corrected.

In the sub-scanning scaling calculator 29 shown in FIG. 1e, the RA
RAM4 is read in the form of line clock LSYNC count instead of data clock DCLK count.
Thus, the data Ai and Bi are read and Ai and Bi are given to the sampling circuit 65Y. As a result, in the sub-scanning direction as well, the image data (in this case, the intermediate data subjected to the scaling processing in the main scanning direction) is sampled in the same manner as the sampling in the main scanning direction. Then, the sampled image data is subjected to MTF correction in the sub-scanning direction by the YMTF calculator 110Y.

As described above, in the first embodiment shown in FIG. 1e, the scaled image data is set by the above-described method.

Second Embodiment (FIGS. 2a and 2b) The main part of the second embodiment, which is different from the first embodiment, is mainly shown in FIG. 2a, and the processing control operation of the first embodiment is also shown. Only the different parts are shown in FIG. 2b. In the second embodiment, the main scanning scaling calculator 28 is a main scanning direction scaling image data calculator 80.
It is composed of an XB and a main scanning direction MTF correction calculator 110XB (not shown) having the same structure as the main scanning direction MTF correction calculator 110XA shown in FIG. 1d. The sub-scanning scaling calculator (not shown) of the second embodiment has two line buffers (not shown) each storing image data for one line, and a calculator having the same configuration as 80XB ( (Not shown) sub-scanning direction scaling calculator; and sub-scanning direction MT having the same configuration as the combination of the line buffers 81Y, 82Y and YMFT calculator 100Y shown in FIG. 1e.
It is composed of an F correction calculator (not shown). In summary, the second embodiment is different from the first embodiment only in the scaling processor. Therefore, the scaling processing calculator of the second embodiment will be described in detail here.

In Fig. 2a, the main scanning direction scaled image data calculator 80XB
Calculates the scaled image data Oik as described above.

That is, the four types of coefficients A and the image data Sij (0
˜63) is applied to the input ports a to d of the data selector 28b. Note that a to d correspond to a to d in the right column of Table 1, where a is all bits of Sij, that is, Sij, and b is the sum of upper 5 bits and upper 4 bits of Sij. The data shown is the top 5 of Sij in c.
Bits, that is, 1/2 Sij, are given to d, and the upper 4 bits of Sij, that is, 1/4 Sij.

Further, the data obtained by multiplying the four types of coefficients B in Table 1 by the image data Sij ₊₁ is the input ports a to d of the data selector 28c.
Applied to. Note that these a to d are also a to d in the right column of Table 1.
Data corresponding to 0, a indicating 0, and b indicating
The upper 4 bits of Sij _{+ 1} , that is, 1 / 4Sij _{+ 1,} is assigned to c as Sij _{+ 1}
Of the upper 5 bits of Sij ₊₁ , ie, 1 / 2Sij ₊₁ is given, and d is given data indicating the sum of the upper 5 bits of Sij ₊₁ and the upper 4 bits of data, namely 3 / 4Sij ₊₁ .

The outputs A and B of the data selectors 28b and 28c are set to any one of the inputs a to d by the signal Bi applied to them, and when the data Bi is 0, the input a is set to the outputs A and B, When the data Bi is 1, the input b is the outputs A and B, and when the data Bi is 2, the input b is
When the input c is the output A, B and the data Bi is 3, the input d is the output A, B. The values of Bi are shown in Table 1.

The adder 28d converts the data indicating the sum of the output A of the data selector 28b and the output B of the data selector 28c to the scaled image data Oik.
Output as.

The selection data Bi of the data selectors 28b and 28c is stored in RAM3,
It is pre-read before the image is read.

The sub-scanning direction scaled image data calculator (not shown) has a structure in which two sets of line buffers are serially connected to the input end of the calculator 80XB and the outputs of those buffers are input in parallel to the 80XB. .

The scaling control operation of the microprocessor 35 of the second embodiment (FIG. 2a) is substantially the same as that of the first embodiment shown in FIGS. 1b and 1c, but step 15 of FIG. 1b is performed. ~ 17
In place of the data Bi setting for the scaled image data calculation by, the data Bi (from Table 1) setting for the scaled image data calculation by steps 41 to 50 shown in FIG. 2b is set. I am trying to do it. That is, the decimal number Ri calculated with each value of i is 0 ≦ Ri <1/8, 1/8 ≦ Ri <3 /
Check if any of 8,3 / 8 ≦ Ri <5/8, 5/8 ≦ Ri <7/8, and 7/8 ≦ Ri <1, in steps 41 to 47, and set 0 ≦
When Ri <1/8, set data indicating 0 in register Bi (42), and when 1/8 ≦ Ri <3/8, set data indicating 1 in register Bi (44), 3 / When 8 ≦ Ri <5/8, set the data indicating 2 to register Bi (46), and 5/8 ≦ Ri <7/8
In case of, the data indicating 3 is set in the register Bi (4
8). When 7/8 ≦ Ri <1, Ri is rounded up to 1, the content of the register j is updated by a number larger by 1 (49), and 0 is set in the register Bi. The Bi thus set is written in the RAM 3 together with Ai as in the first embodiment.

The other scaling processing control operation is similar to that of the first embodiment, and during the image reading, the data Bi set in this way is Ai.
Together with data selectors 28b and 2
Given to 8c. As a result, the scaled image data Oik which is the output of the adder 28d is the one calculated by the above equation (6).

FIG. 2c shows a modified example of the main scanning direction scaled image data calculator 80XB shown in FIG. 2a. In this example, the ROM 28g has the above-mentioned (6) with 0 to 63 of Sij, 0 to 63 of Sij ₊₁ and 4 types of coefficient A shown in Table 1 and 4 types of coefficient B shown in Table 1 as parameters. The scaled image data Oik calculated by the equation is stored with those parameters as addresses. The read address of the ROM 28g is the Si output from the data selector 27.
The coefficients A and B (Table 1) defined by j, Sij ₊₁ and Bi and specified by Bi, and the scaled image data Oik calculated by equation (6) by Sij, Sij ₊₁ are read from the ROM 28g. Be done.

Third Embodiment (FIGS. 3a and 3b) FIG. 3a shows the main part of the third embodiment, which is mainly different from the first embodiment, and the processing control operation of the first embodiment Only the different parts are shown in Figure 3b. In the third embodiment, the main-scanning scaling calculator 28 is a main-scanning-direction scaling image data calculator 80XC.
And a main scanning direction MTF correction calculator 110XC (not shown) having the same configuration as the main scanning direction MTF correction calculator 110XA shown in FIG. 1d. The sub-scanning scaling calculator (not shown) of the third embodiment has two line buffers (not shown) each storing image data for one line, and a calculator having the same configuration as the 80XB ( (Not shown) sub-scanning direction scaling calculator; and sub-scanning direction MT having the same configuration as the combination of the line buffers 81Y, 82Y and YMFT calculator 100Y shown in FIG. 1e.
It is composed of an F correction calculator (not shown). In summary, the third embodiment is different from the first embodiment only in the scaling processor. Therefore, the scaling processing calculator of the third embodiment will be described in detail here.

In Fig. 3a, the main scanning direction scaled image data calculator 80XC
Calculates the modified image data Oik as described above.

That is, the data obtained by multiplying each of the four types of coefficients A in Table 2 by the original image data Sij ₋₁ is supplied to the data selector 52.
The data obtained by multiplying each of the four types of coefficient B in Table 2 by the original image data Sij is the data obtained by multiplying the data selector 53 by each of the four types of coefficient C in Table 2 by the original image data Sij _+1. Is given to the data selector 54, and the data obtained by multiplying each of the four types of coefficients D in Table 2 by the original image data Sij ₊₂ is given to the data selector 55.
Each of the 55 is identified in the data Bi (Table 2). Data indicating values calculated by one of the coefficients A to D (each of four types: Table 2) is output, and the sum obtained by adding them is output by the adder 56 as the scaled image data Oik.

The complementer 57 is for converting the subtraction data (-1/8) into addition data (converting subtraction into addition).

The outputs A to D of the data selectors 52 to 55 are set to any one of the inputs a to d depending on the signal Bi given to them, and when the data Bi is 0, the input a is output A to D.
When the data is D and Bi is 1, the input b is the outputs A to D, when the data Bi is 2, the input c is the outputs A to D, and when the data Bi is 3, the input c is the outputs A to D. , Input d is output A to D. The values of Bi are shown in Table 2.

The adder 56 outputs the data indicating the sum of the outputs A to D of the data selectors 52 to 55 as the scaled image data Oik.

The selection data Bi of the data selectors 52 to 55 is previously read in the RAM 3 before the image is read.

The scaling control operation of the microprocessor 35 of the third embodiment (FIG. 3a) is substantially the same as that of the first embodiment shown in FIGS. 1b and 1c, but step 15 of FIG. 1b is performed. ~ 17
Instead of setting the data Bi for calculating the scaled image data according to, the data Bi (from Table 2) for calculating the scaled image data according to steps 41 to 50 shown in FIG. 3b is set. I am trying to do it. That is, the fractional Ri calculated with each value of i is 0 ≦ Ri <1/4, 1/4 ≦ Ri <1 /
Check if any of 2, 1/2 ≤ Ri <3/4, 3/4 ≤ Ri <7/8, and 7/8 ≤ Ri <1, in steps 41 to 47, and set 0 ≤
When Ri <1/4, the data indicating 0 is set in the register Bi (42), and when 1/4 ≦ Ri <1/2, the data indicating 1 is set in the register Bi (44), 1 / When 2 ≦ Ri <3/4, set the data indicating 2 to register Bi (46), and 3/4 ≦ Ri <7/8
In case of, the data indicating 3 is set in the register Bi (4
8). When 7/8 ≦ Ri <1, Ri is rounded up to 1, the content of the register j is updated by a number larger by 1 (49), and 0 is set in the register Bi. The Bi thus set is written in the RAM 3 together with Ai as in the first embodiment.

The other scaling processing control operation is similar to that of the first embodiment, and during the image reading, the data Bi set in this way is Ai.
At the same time, it is read from the RAM 3 and given to the data selectors 52 to 55. As a result, the scaled image data Oik which is the output of the adder 56 is roughly calculated by the equation (7).

FIG. 3c shows a modification of the computing unit 80XC shown in FIG. 3a. In this example, the ROM 63 has 0 to 63 of Sij _-1 , 0 to 63 of Sij, and Sij _+1.
0 to 63, Sij ₊₂ 0 to 63, and four types of coefficient A shown in Table 2,
Scaled image data calculated by the above-mentioned equation (7) using four types of coefficient B, four types of coefficient C and four types of coefficient D as parameters.
Oik stores those parameters as addresses. The read address of ROM63 is the data selector 2
Sij ₋₁ , Sij, Sij ₊₁ , Sij ₊₂ and Bi output from 7 and the coefficients A to D (Table 1) specified by Bi and Sij
₋₁ , Sij, Sij ₊₁ and Sij ₊₂ , the scaled image data Oik calculated by the equation (7) is read from the ROM 63.

Fourth Embodiment (FIG. 4) FIG. 4 shows only the components of the fourth embodiment that differ from the first embodiment. In the fourth embodiment, the sampling circuit 64 and
65 is characteristic, other parts are the same as those in the first embodiment, and parts other than the sampling circuits 64, 65 may be the same as those in the second and third embodiments.

The sampling circuit 64 shown in FIG. 4 has an AND gate 68 when the RAM 1 is designated for writing (a = H, b = L).
Since and 69 are off and the AND gate 67 is on, the address counter 38 is counted up by DCLK. That is, the original image data is read into the RAM1 every time one pulse of DCLK arrives. When the RAM1 is designated for reading (a = L, b = H), the AND gate 67 is off, and when the RAM1 is reduced (d = H), the AND gate 68 is also off, and the data Ai is stored. Correspondingly, when it is H, DCLK
2DCLK when Ai is L, AND gate 71 or 72
And to the counter through OR gate 70 and AND gate 69 and OR gate 66. When enlarged (d = L), AND gate 69 is off, and when Ai is H, DC
LK is supplied to the counter 38 through the AND gate 68 and the OR gate 66, and when Ai is L, the clock is not supplied to the counter 38.

The sampling circuit 65 also has the same configuration as 64, but the signals a and b are exchanged and supplied to the AND gates 74, 75 and 76. This is because RAM2 is read when RAM1 is written and RAM2 is written when RAM1 is read.

With the configuration and operation of the sampling circuits 64 and 65 described above, also in the fourth embodiment, in the same manner as in the first embodiment (FIG. 1a), writing to the RAMs 1 and 2 and reading and sampling from the RAMs 1 and 2 are performed. . That is, in the first embodiment, the up-down counters 39 and 44 and the adders 37 and 42 count the sampling of the original image data, which is skipped one by one, by double counting DCLK to set the address to 1 of DCLK. The number of pulses is increased by 2 per pulse, but in the fourth embodiment, in this case, 2D
CLK is given to the address counter, and when the DCLK generates one pulse, the address counter is incremented by 2,
The address is advanced by 2 per 1 pulse of DCLK.

Fifth Embodiment (FIG. 3d) FIG. 3d shows the essential parts of the fifth embodiment of the present invention. Figure 3d shows
Only the parts that differ from FIG. 3a are shown. The fifth embodiment is also a modification of the third embodiment, and based on the above-mentioned equation (11),
Scaled image data calculation in the main scanning direction and MTF correction calculation are performed simultaneously, and scaled image data calculation and MTF correction calculation in the sub-scanning direction are performed simultaneously.

First, the arithmetic processing in the main scanning direction will be described. In the fifth embodiment, in order to reduce the required memory capacity of RAM1 and RAM2, the original image data for one line is read and written respectively. Depending on these, it is not possible to obtain adjacent image data in parallel at the same time.
28 is equipped with _four latches 25 _{1 to} 25 _4, which allow
Image data of adjacent 5 pixels is obtained, and the image data and the MTF-corrected data are obtained by using these image data and the coefficients shown in Table 3.

The data selector 111 outputs one of four values obtained by multiplying E · Sij ₋₂ in the equation (11) by the coefficient E in the table 3, and the data selector 112 outputs the data in the equation (11). , A · Sij ₋₁ , and outputs one of four values obtained by multiplying the coefficient A in Table 3 by the data selector 113. One of four values multiplied by B is output, and the data selector 114
Outputs one of four values obtained by multiplying C · Sij ₊₁ in the equation (11) by the coefficient C in Table 3, and the data selector 115
One of four values obtained by multiplying D · Sij ₊₂ in the equation (11) by the coefficient D in Table 3 is output. Which of the four types is output is determined by the data Bi given to the data selectors 111 to 115 by the RAM 4. The outputs of the data selectors 111 to 115 are adders
One of the calculated values (four types of cases a to d) obtained by substituting the coefficients of Table 3 into the equation (11), which is given to the adder 116, is designated by the data Bi. Is output.

This output Mik is subjected to the scaling processing in the main scanning direction as already described in relation to the equation (11) and the third table, and further, with R as a variable, optimum MTF correction is brought about at each value of R. It is a combination of calculations.

Sub-scanning scaling calculator 29 (not shown) of the fifth embodiment
Are latches 25 ₁ to 2 of the main scanning scaling calculator 28 shown in FIG. 3d.
Each of the 5 ₄ is replaced by a line buffer memory.

The other structure of the fifth embodiment is the same as that of the third embodiment. The scaling processing operation is similar to that of the third embodiment described above, except that steps 51 to 57 shown in FIG. 1c are omitted.

In the fifth embodiment, since the scaling processing and the MTF correction operation are aggregated by the same arithmetic expression, the hardware related to the arithmetic becomes simpler and the arithmetic steps are smaller than the case where the arithmetic operations are performed separately. Has become.

Effect As described above, according to the present invention, the scaling ratio R of the image data is designated.
Since the MTF correction calculation corresponding to is performed, the image deterioration due to the scaling processing is reduced.

[Brief description of drawings]

FIG. 1a is a block diagram showing the configuration of the first embodiment of the present invention. 1b and 1c are flow charts showing the scaling processing control operation of the microprocessor 35 shown in FIG. 1a. FIG. 1d is a block diagram showing the configuration of the main-scanning scaling calculator 28 shown in FIG. 1a. FIG. 1e is a block diagram showing the configuration of the sub-scanning scaling calculator 29 shown in FIG. 1a. FIG. 2a is a block diagram showing an essential part of the second embodiment of the present invention. FIG. 2b is a flow chart showing a part of the scaling processing control operation of the microprocessor 35 shown in FIG. 2a. FIG. 2c is a block diagram showing a modified example of the arithmetic unit 80XB shown in FIG. 2a. FIG. 3a is a block diagram showing an essential part of the third embodiment of the present invention. FIG. 3b is a flow chart showing a part of the scaling processing control operation of the microprocessor 35 shown in FIG. 3a. FIG. 3c is a block diagram showing a modification of the arithmetic unit 80XC shown in FIG. 3a. FIG. 3d is a block diagram showing the main part of the fifth embodiment of the present invention. FIG. 4 is a block diagram showing the main part of the fourth embodiment of the present invention. FIG. 5 is a graph showing the value of the interpolation function used in the cubic function convolution method for calculating the scaled image data, where the horizontal axis represents the sampling position assigned to the scaled image data with respect to the sampling position of the original image data. The amount of deviation is shown, and the vertical axis shows the value of the interpolation function. FIG. 6 shows the data Y which is the image reading output of the scan SCR shown in FIG. 1a, the synchronizing clocks LSYNC, DCLK and the latch 25.
3 is a time chart showing the relationship of the data Z which is the output of FIG. FIG. 7 shows the line buffer memory RAM1, RAM shown in FIG. 1a.
2 write data, read data and line sync pulse L
It is a time chart showing the relationship with SYNC. FIG. 8 is a perspective view showing the appearance of a conventional image reading apparatus. FIG. 9 is a side view showing main mechanical components of one conventional image reading apparatus. FIG. 10 is a side view showing main mechanical components of another conventional image reading apparatus. FIG. 11 is a plan view showing the image data distribution on the memory corresponding to images when original image data for one page is stored in the memory for image data scaling by the conventional electrical method. . FIG. 12 is a plan view showing the relationship between the sampling position of the original image data and the sampling position of the scaled image data when the scaled image data is calculated by the distance linear distribution method between adjacent pixels. FIG. 13a is a plan view showing a correction coefficient distribution for MTF correction. FIG. 13b is a plan view showing a distribution of correction pixels in MTF correction and pixels referred to in the correction. 14a, 14b, 14c and 14d are plan views showing the distribution of the MTF correction coefficient. FIG. 15 is a graph showing the frequency response of the scanana SCR shown in FIG. 1a. FIG. 16 is a graph showing the scaling calculation interpolation coefficient in which MTF correction is added. 1: Image reading device, 2: Contact glass plate 3: Original pressure plate, 4: Operation part 5: Fluorescent lamp, 6: Selfoc lens, 7: Image sensor, 8: Reflected light 9: Carridge, 11 to 13: Reflected light 14 : Lens, SCR: Scanner 28: Main scanning scaling calculator, 29: Sub scanning scaling calculator DOC: Document 35: Microprocessor (computing means, sampling position designating means) 64,65,65Y: Sampling circuit (sampling means) ) 80XA: Data selector (magnified image data setting means) 80Y: Magnification calculator (magnified image data setting means) 100XA: Main scanning direction MTF calculator (MTF correction means) 100Y: Sub scanning direction MTF calculator (MTF) Correction means) 80XB, 80XC: Magnification calculator (scaled image data setting means) 28 in FIG. 3d: Main scanning scale calculator (scaled image data setting means, MTF correction means)

Claims (8)

[Claims] 1. A calculation means for calculating original image data sampling position information corresponding to a designated magnification R for producing a scaled image data; a sampling designated position x of the original image data based on the original image data sampling position information. Sampling position specifying means for specifying; Sampling means for extracting original image data at the specified position x; Scaled image data setting means for calculating scaled image data corresponding to the extracted original image data; An image data scaling apparatus comprising: MTF correction means; which has attached MTF correction calculation data and performs MTF correction on image data after scaling or before scaling based on this. 2. The MTF correction means uses correction calculation data corresponding to a magnification region obtained by dividing a range of a designated magnification R into small divisions, and a number of correction calculation means corresponding to the number of small divisions, and one of the correction calculation means. According to the designated magnification R and selecting the output thereof as MTF correction data. The image data scaling processing apparatus according to claim (1). 3. The calculation means is 100i / [specified magnification R (%)]
= Ji + Ri, i is an integer, 0 ≦ Ri <1, Ji is an integer, and is an operation means for calculating an integer Ji and a decimal number Ri; the sampling position specifying means is synchronized with a data clock that determines a pixel unit of the original image data. I is changed one by one, and when R <100, Ji-Ji _-1 = 2 and the sampling designated position x of the original image data is increased by 2 to a number larger than Ji-Ji _-1 =
The designated position x is designated by 1 as a number larger by 1 and when R ≧ 100, the position x is designated by 1 as a number greater by Ji-Ji ₋₁ = 1 and Ji-Ji _−1.
= 0, the position x is designated as it is; the sampling means counts the data clock, and the original image data at the designated position x and the adjacent 1
The above-mentioned image data is extracted; and the variable-magnification image data setting means synchronizes the original image data of Ri, the specified position x and one or more original image data adjacent thereto in synchronization with the data clock. The scaled image data at the position i is determined by the correlation of the three parties; The image data scaling device according to claim (1). 4. The scaled image data setting means sets the scaled image data as original image data at a designated position x when Ri ≦ 0.5, and Ri> 0.
The image data scaling apparatus according to claim (3), wherein the scaled image data is used as the original image data at the position x + 1 in step 5. 5. The scaled image data setting means sets the sum of the original image data at the position x by the weight of Ri and the original image data at the position x + 1 by the weight of 1-Ri as the scaled image data. ,
The image data scaling apparatus according to claim (3). 6. The scaled image data setting means obtains the scaled image data by a cubic function convolution formula using as parameters the original image data at Ri, position x, and the three original image data before and after the original image data. The image data scaling apparatus according to claim (3). 7. A sampling means is a buffer memory means for storing original image data for one line; a means for alternately setting the buffer memory means for writing / reading; an address for giving a writing / reading position to the buffer memory means. Counting means: When writing to the buffer memory means, the data clock DCLK is given to the address counting means as a count pulse, and when reading from the memory means, i is changed by 1 in synchronization with the data clock DCLK, and In the case of R <100, one of the count pulse 2DCLK and the data clock DCLK having twice the frequency of the data clock DCLK corresponding to Ji-Ji _-1 is given to the address counting means as a count pulse, and R ≧ 100 Is Ji-Ji _-1
The sampling position designating means for designating the reading position x of the original image data by applying / blocking the data clock DCLK to / from the address counting means in correspondence with the above. The image data scaling device according to item (4), item (5) or item (6). 8. Sampling means: buffer memory means for storing original image data for one line; means for alternately setting the buffer memory means for writing / reading; address counting means; up / down counting means; address counting means Means for giving the sum of the count data of 1) and the count data of the up / down count means to the buffer memory means as address data; when writing to the buffer memory means, the data clock DCLK is given to the address count means as a count pulse, When reading from the buffer memory means, i is changed by 1 in synchronism with the data clock DCLK, and when R <100, the up / down count means is instructed to up and the data count DCLK is counted by the address count means. , And to Ji-Ji _-1 In response to this, DCLK is applied / blocked to the up / down counting means, and when R ≧ 100, the up / down counting means is instructed to down, and the data clock DCLK is given to the address counting means, and Ji
-Ji _-1 , Sampling position designating means for designating read-out position x of the original image data by applying / blocking the data clock DCLK to the up / down counting means; ), Item (4), Item (5)
An image data scaling device according to item (6).