JPH06101493B2 - Plastic chip carrier - Google Patents
Plastic chip carrierInfo
- Publication number
- JPH06101493B2 JPH06101493B2 JP61071543A JP7154386A JPH06101493B2 JP H06101493 B2 JPH06101493 B2 JP H06101493B2 JP 61071543 A JP61071543 A JP 61071543A JP 7154386 A JP7154386 A JP 7154386A JP H06101493 B2 JPH06101493 B2 JP H06101493B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- lead
- resin
- chip carrier
- film carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明は、IC,LSI等の接続に用いられるプラスチックチ
ップキャリアに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plastic chip carrier used for connecting ICs, LSIs and the like.
従来の技術 近年、IC,LSIの高密度化に伴い、パッケージもデュアル
インラインからフラットパッケージタイプへと変ってき
ている。2. Description of the Related Art In recent years, with the increasing density of ICs and LSIs, the package has changed from dual inline to flat package type.
そして、さらに小型，薄型高密度化の要望に対し、フィ
ルムキャリアタイプのものが用いられてきている。A film carrier type has been used to meet the demand for further reduction in size and thickness.
これは、従来のものがICチップのパッド上に全ワイヤー
を一本一本ボンディングしていたのに対し、フィルムキ
ャリアではフィルムのインナーリードをICチップのパッ
ドに一度に熱圧着するため、作業性が良く、パッケージ
をしないことと、ワイヤーをたるませることもないた
め、厚みが薄く，軽く小型化に出来るという利点を有し
ている。しかし、その反面，フィルム状であるため、フ
ィルムの熱伸縮，吸湿によるストレスをインナーリード
を受け、断線しやすいという問題も有していた。This is because the conventional one bonded all the wires on the pad of the IC chip one by one, but in the film carrier, the inner leads of the film are thermo-compressed to the pad of the IC chip at one time, so workability is improved. It has good advantages in that it is not packaged and the wire does not sag, so it has the advantages of being thin, light and compact. However, on the other hand, since it is in the form of a film, it has a problem that the film is easily broken due to the inner leads that are subjected to stress due to thermal expansion and contraction of the film and moisture absorption.
以下、図面を用いて従来のフィルムキャリアについて説
明する。Hereinafter, a conventional film carrier will be described with reference to the drawings.
第３図は、本発明の一実施例におけるフィルムキャリア
の外観図である。同図において、１はICチップ、２はIC
チップ１上に設けられたパッド、３はフィルムで、フィ
ルム３の表面に銅箔４が貼付けられている。５はパッド
２と接続されたインナーリードで、６はアウターリード
である。第４図は、フィルムキャリアが基板に装着され
た状態を示す断面図である。同図において、７はインナ
ーリード５と半導体チップ１上に設けられたパッド２を
接続するためのバンプ、８は基板である。FIG. 3 is an external view of a film carrier according to an embodiment of the present invention. In the figure, 1 is an IC chip, 2 is an IC
Pads 3 provided on the chip 1 are films, and a copper foil 4 is attached to the surface of the film 3. Reference numeral 5 is an inner lead connected to the pad 2, and 6 is an outer lead. FIG. 4 is a sectional view showing a state in which the film carrier is mounted on the substrate. In the figure, 7 is a bump for connecting the inner lead 5 and the pad 2 provided on the semiconductor chip 1, and 8 is a substrate.
発明が解決しようとする問題点 しかしながら、このようなフィルムキャリアは、フィル
ム状であるため外部からのストレスをインナーリード５
は受けやすく、切断されやすいという問題点を有してい
た。Problems to be Solved by the Invention However, since such a film carrier is in the form of a film, the inner leads 5 are protected from external stress.
Had a problem that it was easily received and easily cut.
そこで本発明は外部からのストレスに対してもインナー
リードが切断されにくい、高信頼性のフィルムキャリア
を提供するものである。Therefore, the present invention provides a highly reliable film carrier in which the inner leads are hard to be cut even when an external stress is applied.
問題点を解決するための手段 この目的を達成するため、フィルムに取り付けられたリ
ードと、前記リードの一方の端が接続される半導体チッ
プ部品と、前記リードの一方の端と前記半導体チップ部
品とをトランスファーモールドパッケージする樹脂とを
備え、前記リードの他方の端をフィルムとともに前記樹
脂の外周に沿設しかつ前記樹脂の底面に前記リードが位
置するように構成したものである。Means for Solving the Problems To achieve this object, a lead attached to a film, a semiconductor chip component to which one end of the lead is connected, one end of the lead and the semiconductor chip component And a resin for transfer-molding a package, the other end of the lead is provided along with the film along the outer periphery of the resin, and the lead is located on the bottom surface of the resin.
作用 この構成により、インナーリードが切断されにくくな
る。Action With this configuration, the inner leads are less likely to be cut.
実施例 以下、本発明の一実施例について、図面を参照して説明
する。Embodiment One embodiment of the present invention will be described below with reference to the drawings.
第１図は、本発明の一実施例におけるプラスチックチッ
プキャリアの断面図、第２図は同斜視図である。FIG. 1 is a sectional view of a plastic chip carrier according to an embodiment of the present invention, and FIG. 2 is a perspective view of the same.
第１図，第２図において、第３図，第４図と同一物には
同一番号を付し説明を省略する。第１図において、９は
パッケージである。同図においてフィルムキャリアの主
要部をエポキシ樹脂でトランスファモールドし、外部端
子はパッケージ９の側面よりフィルム３の外側に銅箔４
が出るようにしてフィルム３とともに下面に曲げられて
いる。また底面にはフィルム３の幅と厚みのくぼみを設
け、フィルム３の先端を位置させる。In FIGS. 1 and 2, the same components as those in FIGS. 3 and 4 are designated by the same reference numerals and the description thereof will be omitted. In FIG. 1, 9 is a package. In the figure, the main part of the film carrier is transfer-molded with epoxy resin, and external terminals are copper foil 4 on the outside of the film 3 from the side surface of the package 9.
Is bent to the lower surface together with the film 3. Further, a recess having the width and the thickness of the film 3 is provided on the bottom surface, and the tip of the film 3 is positioned.
このようにすることにより、インナーリード５の曲線が
少なくなるとともに、アウターリード６がパッケージ９
の下に位置しているため、プリント基板８の取付け面積
が小さくなることになるという効果も有する。By doing so, the curve of the inner lead 5 is reduced, and the outer lead 6 becomes
Since it is located below, there is also an effect that the mounting area of the printed circuit board 8 is reduced.
発明の効果 以上のように本発明は、ICチップとインナーリードで接
続されたフィルムキャリアと、前記フィルムキャリアと
ICチップとトランスファーモールドパッケージする樹脂
とで構成され、前記フィルムキャリアの銅箔面が樹脂の
外側に、フィルムキャリアのアウターリードが樹脂の底
面に位置するので、インナーリードをフィルム３ととも
に曲げるので断線しにくくなる。また、インナーリード
をフィルム３とともに樹脂で成形するのでインナーリー
ドが変形しにくくなる。さらに、アウターリードがパッ
ケージの下に位置するためプリント基板の取付け面積が
小さくなるという効果を有する。Effects of the Invention As described above, the present invention is a film carrier connected to an IC chip with inner leads, and the film carrier.
It is composed of an IC chip and resin for transfer mold packaging. The copper foil surface of the film carrier is located outside the resin and the outer leads of the film carrier are located on the bottom surface of the resin. It gets harder. Moreover, since the inner lead is molded with resin together with the film 3, the inner lead is less likely to be deformed. Further, since the outer leads are located under the package, there is an effect that the mounting area of the printed board is reduced.
第１図は本発明の一実施例におけるプラスチックチップ
キャリアの断面図、第２図は同斜視図、第３図は従来の
フィルムキャリアの斜視図、第４図はフィルムキャリア
が基板に装着された状態を示す断面図である。 １……半導体チップ、４……銅箔、５……インナーリー
ド、６……アウターリード。1 is a sectional view of a plastic chip carrier according to an embodiment of the present invention, FIG. 2 is a perspective view thereof, FIG. 3 is a perspective view of a conventional film carrier, and FIG. 4 is a film carrier mounted on a substrate. It is sectional drawing which shows a state. 1 ... semiconductor chip, 4 ... copper foil, 5 ... inner lead, 6 ... outer lead.
Claims (1)
リードの一方の端が接続される半導体チップ部品と、前
記リードの一方の端と前記半導体チップ部品とをトラン
スファーモールドパッケージする樹脂とを備え、前記リ
ードの他方の端をフィルムとともに前記樹脂の外周に沿
設しかつ前記樹脂の底面に前記リードが位置するように
構成したプラスチックチップキャリア。1. A lead attached to a film, a semiconductor chip component to which one end of the lead is connected, and a resin for transfer-mold packaging the one end of the lead and the semiconductor chip component. A plastic chip carrier in which the other end of the lead is provided along with the film along the outer periphery of the resin, and the lead is located on the bottom surface of the resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61071543A JPH06101493B2 (en) | 1986-03-28 | 1986-03-28 | Plastic chip carrier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61071543A JPH06101493B2 (en) | 1986-03-28 | 1986-03-28 | Plastic chip carrier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62226636A JPS62226636A (en) | 1987-10-05 |
| JPH06101493B2 true JPH06101493B2 (en) | 1994-12-12 |
Family
ID=13463759
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61071543A Expired - Lifetime JPH06101493B2 (en) | 1986-03-28 | 1986-03-28 | Plastic chip carrier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06101493B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0637241A (en) * | 1992-07-17 | 1994-02-10 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| FR2745954B1 (en) * | 1996-03-06 | 1999-10-22 | Itt Composants Instr | PRE-CUT METAL STRIP FOR THE MANUFACTURE OF ELECTRONIC COMPONENTS, METHOD FOR MANUFACTURING SUCH COMPONENTS THUS OBTAINED |
| US6972482B2 (en) * | 2003-09-22 | 2005-12-06 | Intel Corporation | Electronic package having a folded flexible substrate and method of manufacturing the same |
| DE102012106425A1 (en) | 2012-07-17 | 2014-01-23 | Epcos Ag | module |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| BE891283A (en) * | 1980-12-08 | 1982-03-16 | Gao Ges Automation Org | CARRIER ELEMENT FOR AN INTEGRATED CIRCUIT MODULE |
| JPS57104245A (en) * | 1980-12-19 | 1982-06-29 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| JPS59222947A (en) * | 1983-06-02 | 1984-12-14 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacture thereof |
-
1986
- 1986-03-28 JP JP61071543A patent/JPH06101493B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62226636A (en) | 1987-10-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5563443A (en) | Packaged semiconductor device utilizing leadframe attached on a semiconductor chip | |
| US5521429A (en) | Surface-mount flat package semiconductor device | |
| US5770888A (en) | Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package | |
| JP3332516B2 (en) | Thermally enhanced semiconductor device having exposed back surface and method of manufacturing the same | |
| JP4476482B2 (en) | Low profile ball grid array semiconductor package, integrated circuit, printed circuit board, processor system, method for manufacturing low profile ball grid array semiconductor package, and method for mounting semiconductor die | |
| KR970006533B1 (en) | Semiconductor device and manufacture thereof | |
| US6306686B1 (en) | Method of fabricating an electronic package with interconnected chips | |
| US6303997B1 (en) | Thin, stackable semiconductor packages | |
| US5598031A (en) | Electrically and thermally enhanced package using a separate silicon substrate | |
| US6982485B1 (en) | Stacking structure for semiconductor chips and a semiconductor package using it | |
| US20020047213A1 (en) | Multi-chip package type semiconductor device | |
| KR960705357A (en) | Semiconductor devices | |
| US7217991B1 (en) | Fan-in leadframe semiconductor package | |
| US6249433B1 (en) | Heat-dissipating device for integrated circuit package | |
| US6573608B2 (en) | Semiconductor device with layered semiconductor chips | |
| US20020140073A1 (en) | Multichip module | |
| JPH06101493B2 (en) | Plastic chip carrier | |
| US20030102545A1 (en) | Semiconductor device | |
| US20050017354A1 (en) | Arrangement for reducing stress in substrate-based chip packages | |
| US6181003B1 (en) | Semiconductor device packaged in plastic package | |
| US6101101A (en) | Universal leadframe for semiconductor devices | |
| JP2756791B2 (en) | Resin-sealed semiconductor device | |
| US20050179119A1 (en) | Miniaturized chip scale package structure | |
| KR100235108B1 (en) | Semiconductor package | |
| JPH0739244Y2 (en) | Hybrid integrated circuit device |