JPH06104295A - Soldering of hybrid ic - Google Patents
Soldering of hybrid icInfo
- Publication number
- JPH06104295A JPH06104295A JP9361492A JP9361492A JPH06104295A JP H06104295 A JPH06104295 A JP H06104295A JP 9361492 A JP9361492 A JP 9361492A JP 9361492 A JP9361492 A JP 9361492A JP H06104295 A JPH06104295 A JP H06104295A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- jig
- carbon
- bare chip
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、パワーFET,ダイ
オード,トランジスタ等のベアチップを基板に搭載して
なるハイブリッドICのはんだ付け方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for soldering a hybrid IC in which bare chips such as power FETs, diodes and transistors are mounted on a substrate.
【0002】[0002]
【従来の技術】従来、この種のハイブリッドICを製造
する場合において、パワーFET等のベアチップを基板
に搭載するには、図5に示すように、まず、ベアチップ
10をプリフォーム状のはんだ箔11を用いて加熱装置
12上に設けられた基板の如き接合物13に載せ、その
後、図6に示すように、ベアチップ10の上面より加圧
治具14を介して加圧しつつ矢印で示すように左右にス
クライブしながらヒートプレートの如き加熱装置12に
よって加熱し、はんだ箔11を溶融させて接合物13に
接合し、オーミックコンタクトをとっていた。2. Description of the Related Art Conventionally, in manufacturing a hybrid IC of this type, in order to mount a bare chip such as a power FET on a substrate, as shown in FIG. 5, the bare chip 10 is first formed into a preform-shaped solder foil 11. Is placed on a bonded article 13 such as a substrate provided on the heating device 12 by using, and then, as shown in FIG. 6, while pressing from the upper surface of the bare chip 10 via a pressing jig 14, as indicated by an arrow. While scribing to the left and right, it was heated by a heating device 12 such as a heat plate to melt the solder foil 11 and bond it to the bonded article 13 to form an ohmic contact.
【0003】しかしながら、ベアチップ10を複数搭載
するハイブリッドICのような場合、加圧治具14や、
そのスクライブ領域を考慮した作業スペースが必要とな
るため、小型化が難しいという問題があった。However, in the case of a hybrid IC having a plurality of bare chips 10 mounted therein, a pressing jig 14 or
There is a problem that downsizing is difficult because a work space considering the scribe area is required.
【0004】[0004]
【発明が解決しようとする課題】そこで、その改良とし
て、図7に示すように、1〜3個のベアチップ10を基
板13または放熱板15の如き接合物に搭載し、それぞ
れ予めオーミックコンタクトを取った後、その組立体を
ケース16内に搭載する方法があるが、この場合、作業
が煩雑である、といった課題があった。Therefore, as an improvement thereof, as shown in FIG. 7, one to three bare chips 10 are mounted on a bonded article such as a substrate 13 or a heat dissipation plate 15, and ohmic contacts are preliminarily provided. After that, there is a method of mounting the assembly in the case 16, but in this case, there is a problem that the work is complicated.
【0005】この発明は上記のことに鑑み提案されたも
ので、その目的とするところは、複数のベアチップを同
時に接合物に搭載でき、作業性が良く、かつ小型化も容
易なハイブリッドICのはんだ付け方法を提供すること
にある。The present invention has been proposed in view of the above circumstances, and an object thereof is to solder a plurality of bare chips on a bonded object at the same time, to improve workability and to reduce the size of the hybrid IC solder. It is to provide the attachment method.
【0006】[0006]
【課題を解決するための手段】本発明は、カーボンから
なる第1の治具1上に基板2を置き、その上に複数の貫
通孔5aを有するカーボンからなる第2の治具5を置
き、ベアチップ4、はんだ箔3を前記貫通孔5a内であ
って前記基板2上に位置させ、これらの貫通孔5a内に
対応した数の押圧部7aを有するカーボンからなる第3
の治具7の前記押圧部7aを入れ各ベアチップ4上に位
置させ、前記第3の治具7に垂直方向の荷重を加えつつ
水素還元ガス中にて加熱し、前記各ベアチップ4を同時
に前記基板2に接合させるようにして上記目的を達成し
ている。また、パッケージ6上にはんだ箔3aを介し基
板2を置き、かつ複数の貫通孔5aを有するカーボンか
らなる第2の治具5を置き、はんだ箔3、ベアチップ4
を前記貫通孔5a内であって前記基板2上に位置させ、
これらの貫通孔5a内に対応した数の押圧部7aを有す
るカーボンからなる第3の治具7の前記押圧部7aを入
れ各ベアチップ4上に位置させ、前記第3の治具7に垂
直方向の荷重を加えつつ水素還元ガス中にて加熱し、前
記各ベアチップ4を同時に前記基板2に接合させるとと
もに、前記基板2を前記パッケージ6に接合させる構成
として上記目的を達成している。According to the present invention, a substrate 2 is placed on a first jig 1 made of carbon, and a second jig 5 made of carbon having a plurality of through holes 5a is placed thereon. A bare chip 4 and a solder foil 3 are located in the through holes 5a and on the substrate 2 and made of carbon having a corresponding number of pressing portions 7a in the through holes 5a.
The pressing portion 7a of the jig 7 is placed on each bare chip 4 and is heated in a hydrogen reducing gas while applying a vertical load to the third jig 7 to simultaneously heat the bare chips 4 at the same time. The above-mentioned object is achieved by being bonded to the substrate 2. In addition, the substrate 2 is placed on the package 6 via the solder foil 3a, and the second jig 5 made of carbon having a plurality of through holes 5a is placed.
Is located on the substrate 2 within the through hole 5a,
The pressing portions 7a of a third jig 7 made of carbon having a corresponding number of pressing portions 7a are placed in the through holes 5a and are positioned on each bare chip 4 in a direction perpendicular to the third jig 7. The above object is achieved as a configuration in which each bare chip 4 is simultaneously bonded to the substrate 2 and the substrate 2 is bonded to the package 6 while being heated in a hydrogen reducing gas while applying the load.
【0007】[0007]
【作用】上記のように本発明では、複数のベアチップ4
をカーボン製の治具7によって一挙に垂直方向に押圧し
て基板2へ接合するようにし、従前のように加圧治具を
スクライブさせないため、スペースをとらず、装置や基
板2等を小型化でき、また、作業性も良くしている。ま
た、カーボン製の治具1,5,7等を用いてはんだ接合
しており、カーボンははんだが濡れにくく(付着しにく
く)、熱膨張係数が他の材料と近い。また、多数のベア
チップ4を一挙に基板2上に搭載でき、かつ基板2上の
回路で配線でき、ワイヤーボンディング工程を要するも
のにおいては配線用のワイヤーの本数を減らせることが
できる。さらに、基板2へのベアチップ接合、パッケー
ジ6への基板接合も同時に行うことができ、この場合、
はんだ付け工程を削減でき、より組立作業性を良くして
いる。As described above, according to the present invention, a plurality of bare chips 4 are used.
Is pressed all at once in the vertical direction by a carbon jig 7 to bond it to the substrate 2, and the pressure jig is not scribed as in the conventional case, so no space is taken and the device, the substrate 2, etc. are downsized. It can be done and the workability is also good. Further, soldering is performed by using jigs 1, 5, 7 made of carbon, etc. The solder of carbon is hard to be wet (hard to adhere), and the coefficient of thermal expansion is close to that of other materials. In addition, a large number of bare chips 4 can be mounted on the substrate 2 all at once, and wiring can be performed by a circuit on the substrate 2, and the number of wiring wires can be reduced in the case where a wire bonding process is required. Furthermore, bare chip bonding to the substrate 2 and substrate bonding to the package 6 can be performed at the same time. In this case,
The soldering process can be reduced, and the assembly workability is improved.
【0008】[0008]
【実施例】図1は本発明におけるはんだ付け方法に用い
られる装置の分解斜視図、図2は装置をセットした状態
における断面図である。これらの図中1はカーボンから
なる第1の治具で、この治具1は基板2のほぼ対応した
形状の基板載置面1aが底板1b上に形成され、かつ底
板1bの外周部には基板2の位置がズレたりするのを防
止するためのリブ状の支持部1cが形成されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an exploded perspective view of an apparatus used in a soldering method according to the present invention, and FIG. 2 is a sectional view showing a state in which the apparatus is set. In the drawings, reference numeral 1 is a first jig made of carbon. This jig 1 has a substrate mounting surface 1a having a substantially corresponding shape of a substrate 2 formed on a bottom plate 1b, and an outer peripheral portion of the bottom plate 1b. A rib-shaped support portion 1c is formed to prevent the position of the substrate 2 from being displaced.
【0009】基板2は図示例では横長の矩形をなし、上
面には所定の回路パターンをなす導体2aのブロックが
複数形成され、この各導体2a上に高融点のプリフォー
ム状のはんだ箔3を介しベアチップ4が載置される。The substrate 2 has a horizontally long rectangular shape in the illustrated example, and a plurality of blocks of conductors 2a having a predetermined circuit pattern are formed on the upper surface thereof, and a high melting point preform-shaped solder foil 3 is formed on each conductor 2a. The bare chip 4 is mounted via the.
【0010】5はカーボン製の第2の治具で、基板2の
周辺部を押さえるためのものである。この第2の治具5
には上面から下面にかけて基板2上に載置されるベアチ
ップ4の数と対応した数の貫通孔5aが治具5の長さ方
向に対し間隔をあけて形成されている。また、側部に
は、図3に示すように、溝5b,5cを形成し、この治
具5が収納される箱型のパッケージ6内の突部6aと位
置決めしつつ嵌合するようになっている。Reference numeral 5 denotes a second jig made of carbon for pressing the peripheral portion of the substrate 2. This second jig 5
Through holes 5a corresponding to the number of bare chips 4 mounted on the substrate 2 are formed from the upper surface to the lower surface at intervals in the length direction of the jig 5. As shown in FIG. 3, grooves 5b and 5c are formed on the side portions so that the jigs 5 can be fitted into the box-shaped package 6 in which the jig 5 is housed while being positioned. ing.
【0011】再び図1において、7はカーボン製の第3
の治具で、コーム状をなし、貫通孔5aに挿入され、ベ
アチップ4と当接され、かつベアチップ4を押圧する例
えば角棒状をなす押圧部7aが複数形成されている。そ
の他、8は第3の治具7の上部にセットされ、治具7等
の組立体を押圧するための所定の重さを有する銅板の如
き荷重体である。Referring again to FIG. 1, 7 is a carbon-made third
The jig is formed into a comb shape, is inserted into the through hole 5a, is in contact with the bare chip 4, and has a plurality of pressing portions 7a in the shape of, for example, a rectangular rod that press the bare chip 4. In addition, 8 is a loader such as a copper plate set on the third jig 7 and having a predetermined weight for pressing the assembly of the jig 7 and the like.
【0012】次に基板2上へのベアチップ4のはんだ付
け方法について説明する。まず、第1の治具1上に基板
2を置き、かつはんだ箔3、ベアチップ4等を導体2a
上に置く。ついで、第2の治具5をセットし、はんだ箔
3、ベアチップ4の位置決めを行う。これらはんだ箔
3、ベアチップ4の配置、位置決め等は第2の治具5を
セットした後、貫通孔5aを介して行っても良い。すな
わち、貫通孔5aにはベアチップ4の位置決め機能をも
たせている。しかる後、第3の治具7をセットし、押圧
部7aをベアチップ4上に置き、治具7の上部に荷重体
8を置き、その荷重で圧力を加える。この加圧状態で、
これらの組立体は水素還元ガス中に置かれ、かつ適宜構
成の加熱装置(図示せず)によって加熱し、高融点のは
んだ箔3を溶融させれば、はんだ接合を行うことができ
る。Next, a method of soldering the bare chip 4 on the substrate 2 will be described. First, the substrate 2 is placed on the first jig 1, and the solder foil 3, the bare chip 4 and the like are attached to the conductor 2a.
put on top. Then, the second jig 5 is set and the solder foil 3 and the bare chip 4 are positioned. The placement and positioning of the solder foil 3 and the bare chip 4 may be performed through the through hole 5a after the second jig 5 is set. That is, the through hole 5a has a positioning function for the bare chip 4. Then, the third jig 7 is set, the pressing portion 7a is placed on the bare chip 4, the load body 8 is placed on the jig 7, and pressure is applied by the load. In this pressurized state,
These assemblies are placed in a hydrogen reducing gas, and are heated by a heating device (not shown) having an appropriate configuration to melt the high melting point solder foil 3, whereby solder joining can be performed.
【0013】上記はんだ接合が終了した場合、組立体を
分解し、ベアチップ4が接合された基板2を取り出し、
必要性があればワイヤーボンディングにより必要な部分
の配線を行う。When the above solder joining is completed, the assembly is disassembled and the substrate 2 to which the bare chip 4 is joined is taken out,
If necessary, wire bonding is used to connect the necessary parts.
【0014】次に、図3に示したパッケージ6に基板2
をはんだ接合する。この場合のはんだとしては、ベアチ
ップ接合をしたはんだ箔3よりも融点の低いプリフォー
ム状のはんだ箔が用いられる。同じような融点であると
既になされたベアチップ接合に支障をきたすためであ
る。この基板接合は、パッケージ6内にはんだ箔を置
き、その上に基板2を置く。ついで、第2の治具5をそ
の溝5b,5cとパッケージ6側の突部6aとを合わせ
てパッケージ6内に置き、図1に示した荷重体8により
荷重を加える。この状態で水素還元ガス中で加熱すれば
基板接合を行うことができる。この場合、特に図示して
いないが治具5の下面は、上記したワイヤーボンディン
グによるワイヤーを切断しない形状となっていることは
勿論である。Next, the substrate 2 is placed in the package 6 shown in FIG.
Solder joint. As the solder in this case, a preform-shaped solder foil having a melting point lower than that of the solder foil 3 having the bare chip connection is used. This is because if the melting points are the same, the already existing bare chip bonding will be hindered. In this board bonding, the solder foil is placed in the package 6 and the board 2 is placed thereon. Then, the second jig 5 is placed in the package 6 with the grooves 5b and 5c and the projecting portion 6a on the package 6 side aligned, and a load is applied by the load body 8 shown in FIG. Substrate bonding can be performed by heating in a hydrogen reducing gas in this state. In this case, although not particularly shown, the lower surface of the jig 5 is of course shaped so as not to cut the wire by the above wire bonding.
【0015】なお、ベアチップ4と基板2との配線が導
体2aの回路パターンで行えるようなものではベアチッ
プ接合と基板接合とを同時に行うことができ、はんだ付
け工程を削減することができる。In the case where the wiring between the bare chip 4 and the substrate 2 can be performed by the circuit pattern of the conductor 2a, the bare chip bonding and the substrate bonding can be performed at the same time, and the soldering process can be reduced.
【0016】図4はその場合に用いられる装置例を示
す。すなわち、パッケージ6内にはんだ箔3aを置き、
その上に基板2、はんだ箔3を置き、かつ第2の治具
5、第3の治具7、荷重体8をセットし、水素還元ガス
中で加熱すればベアチップ接合、基板接合を同時に行う
ことができる。この場合、図1に示した第1の治具1は
省略することができる。また、はんだ箔3,3aとして
は同一のもの、またはほぼ同じ融点のものを用いれば良
い。FIG. 4 shows an example of an apparatus used in that case. That is, the solder foil 3a is placed in the package 6,
If the substrate 2 and the solder foil 3 are placed thereon and the second jig 5, the third jig 7 and the load body 8 are set and heated in a hydrogen reducing gas, bare chip bonding and substrate bonding are performed at the same time. be able to. In this case, the first jig 1 shown in FIG. 1 can be omitted. The solder foils 3 and 3a may have the same or substantially the same melting point.
【0017】[0017]
【発明の効果】以上のように本発明では、複数のベアチ
ップ4の上にカーボン製の治具7の押圧部7aをそれぞ
れ当て垂直方向に加圧して基板2上に置かれた上記ベア
チップ4をはんだ箔3を介し一挙に接合するようにし、
従来のように加圧治具をスクライブさせるといった工程
を伴わないないため、スペースをとることがなく、狭い
場所に複数のベアチップ4を同時に接合でき、作業性が
良いとともに、小型化を図ることができる。また、カー
ボン製の治具1,5,7を用いているため、この素材
は、はんだが濡れにくく、かつ熱膨張が他の材料(ベア
チップ4、基板2)と近いので、作業の際に基板などに
ストレスを加えることはない。As described above, according to the present invention, the bare chips 4 placed on the substrate 2 are pressed against the plurality of bare chips 4 by pressing the pressing portions 7a of the jigs 7 made of carbon respectively in the vertical direction. The solder foil 3 should be joined at once,
Since it does not involve a step of scribing a pressure jig as in the conventional case, a plurality of bare chips 4 can be simultaneously bonded to a narrow place without taking up a space, and the workability is good and the size can be reduced. it can. Further, since the jigs 1, 5, and 7 made of carbon are used, this material is hard to be wet with solder, and its thermal expansion is close to that of other materials (bare chip 4, substrate 2). There is no stress added to such.
【0018】また、請求項2のようにパッケージ6上に
はんだ箔3aを介し基板2を置き、かつ複数の貫通孔5
aを有するカーボンからなる第2の治具5を置き、はん
だ箔3、ベアチップ4を前記貫通孔5a内であって前記
基板2上に位置させ、これらの貫通孔5a内に対応した
数の押圧部7aを有するカーボンからなる第3の治具7
の前記押圧部7aを入れ各ベアチップ4上に位置させ、
前記第3の治具7に垂直方向の荷重を加えつつ水素還元
ガス中にて加熱し、前記各ベアチップ4を同時に前記基
板2に接合させるとともに、前記基板2を前記パッケー
ジ6に接合させるようにすれば、ベアチップ接合と基板
接合とを同時に行うことができ、はんだ付け工程が削減
する。Further, the substrate 2 is placed on the package 6 with the solder foil 3a interposed therebetween, and a plurality of through holes 5 are provided.
The second jig 5 made of carbon having a is placed, the solder foil 3 and the bare chip 4 are positioned in the through holes 5a and on the substrate 2, and a corresponding number of pressings are performed in the through holes 5a. Third jig 7 made of carbon and having a portion 7a
Put the pressing portion 7a of the above to position on each bare chip 4,
The third jig 7 is heated in a hydrogen reducing gas while applying a vertical load to bond the bare chips 4 to the substrate 2 at the same time, and bond the substrate 2 to the package 6. By doing so, bare chip bonding and substrate bonding can be performed at the same time, and the soldering process is reduced.
【図1】本発明に用いられる装置例の分解斜視図。FIG. 1 is an exploded perspective view of an example of a device used in the present invention.
【図2】同上の組立状態の断面図。FIG. 2 is a cross-sectional view of the above assembled state.
【図3】基板をパッケージに接合する場合の装置の分解
斜視図。FIG. 3 is an exploded perspective view of an apparatus when bonding a substrate to a package.
【図4】ベアチップ接合、基板接合を同時に行う装置の
組立状態の断面図。FIG. 4 is a cross-sectional view of an assembled state of a device that simultaneously performs bare chip bonding and substrate bonding.
【図5】従来例。FIG. 5 shows a conventional example.
【図6】従来例の動作説明図。FIG. 6 is an operation explanatory view of a conventional example.
【図7】他の従来例。FIG. 7 shows another conventional example.
1 第1の治具 1a 基板収納部 1b 底板 1c 支持部 2 基板 2a 導体 3,3a はんだ箔 4 ベアチップ 5 第2の治具 5a 貫通孔 5b,5c 溝 6 パッケージ 6a 突部 7 第3の治具 8 荷重体 1 1st jig 1a Substrate storage part 1b Bottom plate 1c Support part 2 Substrate 2a Conductor 3,3a Solder foil 4 Bare chip 5 Second jig 5a Through hole 5b, 5c Groove 6 Package 6a Projection 7 Third jig 8 load body
Claims (2)
基板(2)を置き、その上に複数の貫通孔(5a)を有
するカーボンからなる第2の治具(5)を置き、ベアチ
ップ(4)、はんだ箔(3)を前記貫通孔(5a)内で
あって前記基板(2)上に位置させ、これらの貫通孔
(5a)内に対応した数の押圧部(7a)を有するカー
ボンからなる第3の治具(7)の前記押圧部(7a)を
入れ各ベアチップ(4)上に位置させ、前記第3の治具
(7)に垂直方向の荷重を加えつつ水素還元ガス中にて
加熱し、前記各ベアチップ(4)を同時に前記基板
(2)に接合させることを特徴としたハイブリッドIC
のはんだ付け方法。1. A substrate (2) is placed on a first jig (1) made of carbon, and a second jig (5) made of carbon having a plurality of through holes (5a) is placed thereon. , The bare chip (4) and the solder foil (3) are located in the through hole (5a) and on the substrate (2), and the corresponding number of pressing portions (7a) are provided in these through holes (5a). The pressing portion (7a) of a third jig (7) made of carbon having carbon is placed on each bare chip (4) and hydrogen is applied to the third jig (7) while applying a vertical load. Hybrid IC characterized by heating in a reducing gas to simultaneously bond the bare chips (4) to the substrate (2)
Soldering method.
を介し基板(2)を置き、かつ複数の貫通孔(5a)を
有するカーボンからなる第2の治具(5)を置き、はん
だ箔(3)、ベアチップ(4)を前記貫通孔(5a)内
であって前記基板(2)上に位置させ、これらの貫通孔
(5a)内に対応した数の押圧部(7a)を有するカー
ボンからなる第3の治具(7)の前記押圧部(7a)を
入れ各ベアチップ(4)上に位置させ、前記第3の治具
(7)に垂直方向の荷重を加えつつ水素還元ガス中にて
加熱し、前記各ベアチップ(4)を同時に前記基板
(2)に接合させるとともに、前記基板(2)を前記パ
ッケージ(6)に接合させることを特徴としたハイブリ
ッドICのはんだ付け方法。2. A solder foil (3a) on the package (6).
The substrate (2) is placed over the second jig (5) made of carbon having a plurality of through holes (5a), and the solder foil (3) and the bare chip (4) are placed in the through holes (5a). Of the third jig (7), which is made of carbon and is located on the substrate (2) and has a corresponding number of pressing portions (7a) in the through holes (5a). 7a) is placed on each bare chip (4) and heated in a hydrogen reducing gas while applying a vertical load to the third jig (7), and each bare chip (4) is simultaneously placed on the substrate. A method for soldering a hybrid IC, characterized in that it is joined to (2) and the substrate (2) is joined to the package (6).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9361492A JPH06104295A (en) | 1992-03-19 | 1992-03-19 | Soldering of hybrid ic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9361492A JPH06104295A (en) | 1992-03-19 | 1992-03-19 | Soldering of hybrid ic |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06104295A true JPH06104295A (en) | 1994-04-15 |
Family
ID=14087210
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9361492A Pending JPH06104295A (en) | 1992-03-19 | 1992-03-19 | Soldering of hybrid ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06104295A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007083738A1 (en) * | 2006-01-20 | 2007-07-26 | Kabushiki Kaisha Toyota Jidoshokki | Aligning jig, aligning method, method for manufacturing semiconductor module and soldering apparatus |
JP2010109153A (en) * | 2008-10-30 | 2010-05-13 | Elpida Memory Inc | Method of manufacturing semiconductor device |
JP2012019028A (en) * | 2010-07-07 | 2012-01-26 | Toyota Motor Corp | Soldering method for element |
JP2012164841A (en) * | 2011-02-08 | 2012-08-30 | Fuji Electric Co Ltd | Assembly jig of semiconductor device and assembling method of semiconductor device |
JP2013021145A (en) * | 2011-07-12 | 2013-01-31 | Fuji Electric Co Ltd | Semiconductor device assembly jig and method of manufacturing semiconductor device using the same |
JP2017148258A (en) * | 2016-02-25 | 2017-08-31 | 株式会社日立製作所 | Ultrasonic probe and manufacturing method thereof, and ultrasonograph |
-
1992
- 1992-03-19 JP JP9361492A patent/JPH06104295A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2007083738A1 (en) * | 2006-01-20 | 2007-07-26 | Kabushiki Kaisha Toyota Jidoshokki | Aligning jig, aligning method, method for manufacturing semiconductor module and soldering apparatus |
JP2010109153A (en) * | 2008-10-30 | 2010-05-13 | Elpida Memory Inc | Method of manufacturing semiconductor device |
JP2012019028A (en) * | 2010-07-07 | 2012-01-26 | Toyota Motor Corp | Soldering method for element |
JP2012164841A (en) * | 2011-02-08 | 2012-08-30 | Fuji Electric Co Ltd | Assembly jig of semiconductor device and assembling method of semiconductor device |
JP2013021145A (en) * | 2011-07-12 | 2013-01-31 | Fuji Electric Co Ltd | Semiconductor device assembly jig and method of manufacturing semiconductor device using the same |
JP2017148258A (en) * | 2016-02-25 | 2017-08-31 | 株式会社日立製作所 | Ultrasonic probe and manufacturing method thereof, and ultrasonograph |
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