JPH0590117A - Single crystal thin film semiconductor device - Google Patents

Abstract

PURPOSE:To enable using crystal orientation and crystal axis suitable to an element to be formed on each layer, and using a substrate advantageous to chip working, by adhering two or more wafers having different crystal orientations, and forming elements on these wafers. CONSTITUTION:An N-channel MOS is formed on a silicon wafer having a (100) face, and element isolation and activation are performed. At the same time, a P-channel MOS is formed on a silicon wafer having a (110) face. Each of the oxidation periods is adjusted so as to be matched with each of the crystal faces. The respective wafers are dipped in pure water, stuck to each other in the water, taken out from the water, and bonded by heat treatment in an N atmosphere. The wafer on which the pMOS is formed is polished and grinded from the rear. Hence it is made possible to apply a suitable semiconductor substrate to each kind of element, and to combine the substrates on which elements are previously formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a single crystal thin film.

[0002]

2. Description of the Related Art At present, most LSIs merely have two-dimensionally arranged active elements and passive elements on the surface of a substrate, and only some of them are considered three-dimensionally as next-generation high-speed elements or multifunctional elements. Came into view. As an attempt to specifically realize this three-dimensional element, as a method of manufacturing the semiconductor device, for example, an amorphous silicon film formed on an insulating film is solid-phase grown by heat treatment to be single-crystallized, or melted using an energy beam. A method of recrystallizing or implanting oxygen ions to form an insulating film in a wafer has been used. On the other hand, there was a method of pasting. However, in the former method, since the silicon substrate is used as a seed crystal when proceeding with single crystallization, only the underlying silicon substrate and the silicon single crystal film on the top can obtain only the same crystal orientation. In addition, the method of stacking layers in order from the bottom layer is a problem in that the yield rate is poor because the total defect rate is a multiplication of the defect rates of each layer. There was a problem of thermal history of the lower layer, a problem of crystallinity and interface such as mixing of crystal defects and impurities, and a problem of working process such that it takes time to manufacture devices one by one. Regarding the latter bonding, unfortunately, no consideration was given to the device in spite of the possibility of greatly improving these problems. Moreover, the degree of freedom in the cutting process for forming chips has been poor.

[0003]

DISCLOSURE OF THE INVENTION The present invention provides a concrete method of a multifunctional high-speed three-dimensional device, which removes the restriction on the process and manufactures each layer independently and in parallel. The degree of integration, which is difficult with the current method of forming devices only on a silicon substrate, is increased by giving the degree of freedom to create devices in the crystal axis direction, and a method of stacking a system with new functions on one chip It is shown. In the conventional method of forming a laminated film by solid phase growth or crystal growth such as melt recrystallization, since the base is a seed crystal, only upper and lower crystals can be obtained with the same material, crystal plane, and crystal orientation. In addition, there was no choice but to sequentially fabricate from the lower layer. Therefore, the yield was poor even when laminated, and the elements in the lower layer deteriorated due to thermal history, and the working process took a long time. Regarding the multi-functionalization, there was no degree of freedom because the substrate for each layer was limited. Also, for example, CMO
Taking S as an example, the substrate cannot be optimized for each of P-ch and N-ch, and a sufficient stacking effect cannot be obtained. As an example, consider a structure in which a gate is formed between upper and lower MOSs and operated at the same time.
If the upper and lower elements are PMOS and NMOS, if they can be formed on different crystal planes, it is considered that mobility and the like can be balanced and multi-functionalization is facilitated. Further, the main point provided by the present invention is that the degree of freedom in manufacturing an element is not provided, and a suggestion is also given to a cleavage plane and a cleavage direction which are problems when finishing as a chip.
Further, when P-channel and N-channel MOS devices are formed on the (110) plane, the channel direction of P-channel is <11.
When the directions that are advantageous to the device are different, such that the direction of 0> and the direction of the N channel are the direction of <100>, which is advantageous in terms of mobility, the layout of the device is restricted, which is a major obstacle to increasing the integration degree. However, it is a problem to solve such a point.

[0004]

The present invention makes it possible to use crystal orientations and crystal axes that are suitable for the device to be formed in each layer by bonding single crystals having different crystal planes. Further, in order to achieve multi-functionality, elements having different functions were formed on substrates made of different materials, and the substrates were bonded together. In addition, by changing the orientation of the substrate on which the device is made and the substrate that supports it, it has become possible to use a substrate that is advantageous for chip processing. Furthermore, in order to shorten the construction period and improve the yield, each element can be formed before the substrates are bonded together.

[0005]

According to the present invention, each element is formed independently using a substrate suitable for each element, and the elements are attached to each other, whereby the element layout can be freely performed, and the semiconductors suitable for various elements can be appropriately selected. Enables the use of substrates, shortening the construction period, improving yield, integration, multifunctionality,
We were able to achieve improvements in operating speed and workability.

Further, by freely selecting upper and lower crystal planes and crystal orientations, for example, a P-channel semiconductor device is formed into a (110) plane thin film having a thickness of 0.1 μm or less, and N-ch is (100). It is possible to make full use of the merit of stacking in terms of the circuit configuration, such as making it on the surface and making the mobilities of the two uniform. Also, in the circuit configuration, a part that requires latch-up measures is made in the upper layer, and at that time, N
It was possible to select a crystal plane according to -ch and P-ch. Further, when P-channel and N-channel MOS devices are formed on the same (110) plane, the P-channel direction is <110> and the N-channel direction is <100.
The mobility becomes larger in the> direction. When such an element is formed on a substrate in which upper and lower substrates are bonded so that the <110> and <100> axes are overlapped, the channel directions are parallel to each other, and the dead space in the element layout can be reduced and the integration degree can be improved. I was able to give it. On the other hand, (11
When the (0) plane is used as the upper substrate, a cleavage plane that is crystallographically stable can be used in a so-called dicing process in which the semiconductor device is cut off by forming the (100) wafer or the (110) wafer below. It was possible to cut out a square chip.

[0007]

[Examples] With the miniaturization of integrated circuits, the size of semiconductor elements is approaching the limit, and not only LSIs are arranged two-dimensionally on the surface of a substrate but also three-dimensionally as next-generation high-speed elements or multifunctional elements. Considerations have become more realistic. Methods such as solid phase growth, melt recrystallization, and oxygen ion implantation insulating film formation have been used as attempts to specifically realize this three-dimensional element. In addition, there is also a method of attaching the other. However, in the former method, as shown in FIG. 1, since the silicon substrate is used as a seed crystal when proceeding with the single crystallization, only the underlying silicon substrate and the silicon single crystal film above have the same crystal orientation. There wasn't. Furthermore, because it is a method of stacking from the lower layer in order,
The overall defect rate is a product of the defect rates of each layer, resulting in poor yield, the problem of thermal history of the upper layer single crystal and the lower layer when making a device, and the inclusion of crystal defects and impurities. However, there are problems in the work process such as crystallinity and interface problems, and it takes time to fabricate devices one by one. In addition, even if the latter is bonded, there is a possibility that these problems can be greatly improved,
Unfortunately, no consideration was given to devices, processes, or processes.

As shown in FIG. 2, in the conventional example, the elements are laminated in order to exceed the limit of improvement in the degree of integration due to the miniaturization of the elements. However, since the crystal orientations of the lower and upper silicon substrates are the same, control of the characteristics of the P-ch and N-ch MOSs by the crystal structure is not utilized, and it is not possible to bring out the respective performances sufficiently or to make the characteristics uniform. Not doing it left a big problem in the circuit design.

According to the present invention, the crystal planes, crystal axes of the upper and lower substrates,
The above problem was solved by allowing the materials to be freely selected. FIG. 1 shows a bonded substrate of the first embodiment. First, an N-channel MOS was manufactured on a silicon wafer having a (100) plane. Device isolation is LOCOS, gate oxide film 250 Å, channel length 0.5μ
m, source, and drain are ion-implanted As,
Activation was performed by heat treatment at 850 ° C. for 30 minutes. On the other hand, (1
A P-channel MOS was similarly formed on a silicon wafer having a 10) surface. At this time, since the growth rate of the oxide film varies depending on the crystal plane as shown in FIG. 3, the oxidation time is adjusted according to the crystal plane. Next, as shown in FIG.
The substrates on which the OS and the NMOS were manufactured were attached. The respective wafers were first bonded by immersing them in pure water, bonding them in water, taking them out, and then heat-treating them at 850 ° C. in a N ₂ atmosphere for 30 minutes. Even if the inside of the furnace was evacuated to evaporate the water content before the heat treatment, the surface-adsorbed water remained and the adsorption effect was maintained. Almost the same adhesion was obtained even if the step of immersing in water was omitted, but it was advantageous to bond them once in water in terms of misalignment, entrapment of bubbles, and the like. Next, PM
The wafer on which the OS was formed was ground by mechanical polishing from the back side. At this time, mechanical polishing was performed until a thin film having a thickness of 0.05 μm was obtained by utilizing the fact that the grinding resistance was changed when the oxide film portion of LOCOS previously used for element isolation appeared on the surface. Thus, it was possible to make the mobilities of both devices uniform by utilizing the effect of improving the mobilities by thinning the active layer of the device and weakening the vertical electric field from the gate.
FIG. 4 shows the relationship between the crystal plane and the mobility for reference. As a result, the advantages of stacking can be fully utilized in terms of circuit configuration.

FIG. 5 shows that N gate is formed without forming the gate of the PMOS.
It is a second embodiment of the present invention in which a substrate on which a MOS is formed and a bonding gate are shared. The source / drain ion implantation for PMOS formation was performed using an oxide film mask, and was peeled off before bonding and the whole surface was oxidized again. FIG. 6 shows the Nss of such an oxide film, and although it differs depending on the crystal plane, the level of (111) plane was not a particularly serious problem. In such a circuit in which a gate is formed between the upper and lower MOSs to operate simultaneously, the characteristics can be balanced by forming the upper and lower elements on different crystal planes if they are PMOS and NMOS, respectively. Was able to stabilize. In a fine device, such control can no longer be performed by impurity ion implantation of the channel, and it has become possible to control only in relation to the crystal orientation of the substrate, the channel direction and the crystal axis.

FIG. 7 shows <110> and <10 when manufacturing P-channel and N-channel MOS devices on the (110) plane.
In the third embodiment of the present invention, the (110) plane substrates are attached to each other so that the 0> axis is overlapped, and the channel directions are made parallel to reduce the dead space in the layout of the device and to increase the integration degree. is there. As shown in FIG. 4, when P-channel and N-channel MOS devices are formed on the same (110) plane, the P-channel moves in the <110> direction and the N-channel moves in the <100> direction, respectively. The degree increases. However, when the elements are laid out in this way, the elements are arranged at an angle of 45 ° with respect to each other, so that a dead space in a triangular region is formed. Therefore, (11
A wafer with a (0) plane and an orientation flat of (110)
A MOS is formed and has a (110) plane.
An NMOS was formed on the wafer prepared as (00). These two wafers were laminated with an orientation flat and bonded by a heating process at 850 ° C. for 30 minutes. Then, the substrate on which the PMOS was formed was polished from the back side to form a thin film. Furthermore, the region where the PMOS is not formed is removed by reactive ion etching,
The wiring with the NMOS was formed. A1-Cu alloy produced by the sputtering method was used for the wiring. This process was previously (11
A wafer having a (0) surface and an orientation flat of <110>,
The surface of a wafer having a (110) plane and an orientation flat of <100> is oxidized, and one of them is thinned by a thermal process at 950 ° C. for 30 minutes, and then one of them is thinned by reactive ion etching. Similar parts could be produced by removing parts and forming PMOS and NMOS at suitable crystal axes. At this time, if only the LOCOS element is separated, it is advantageous in terms of positioning and a stopper during polishing for thinning. The same effect is applied when a (311) plane wafer is used as shown in FIG. Further, as shown in FIG. 9, in the P channel and the N channel, the channel directions with high mobility are different from each other by 90 degrees.
That is, P-chan is parallel to <110> and N-chan is vertical, that is, parallel to <001>. In the case of the (011) wafer, this has a positional relationship in which the normal line is rotated by 45 degrees with respect to each other.

FIG. 10 shows (110) for the N channel.
When the (111) plane having a higher mobility than the plane is used as the upper substrate, or when the GaAs substrate is used as the upper substrate,
A semiconductor device is separated by making the lower wafer a (100) wafer or a (110) wafer, a cleavage plane that is crystallographically stable can be used in a so-called dicing process, and a square chip can be cut out. It is a fourth embodiment of the invention. Although the method of heating by sandwiching the thermal oxide film between the wafers has been described as an example for bonding the wafers, the thermal oxide film and the silicon or the silicon and the silicon can be similarly bonded. In addition, the silicon-based adhesive silanol (SiH
The same effect could be obtained by using ( ₃ OH) or the like or an organic adhesive. Further, the same effect can be obtained as long as it is a method of bonding a wafer without departing from the scope of the present invention.

Further, although silicon has been taken as an example of the wafer for description, other than silicon, Ge, GaAs, In may be used.
Similar effects can be obtained by combining substrates of group IV, group III-V, group II-VI, etc. such as P.

[0014]

According to the present invention, it is possible to freely perform element layout and use appropriate semiconductor substrates for various elements, and it is also possible to form elements on each substrate in advance and then combine them. It is possible, and it is possible to improve the degree of integration, multifunctionality, operation speed, and workability.
For example, in a semiconductor device, P-ch, N-ch MO
The element characteristics of S can be made equal to a required value, and a good circuit element configuration can be achieved by using a substrate suitable for each operation. Further, not only the integration degree is simply improved by stacking, but also the channel directions of the P-ch and N-ch MOSs can be aligned with the respective suitable crystal axes to align the directions of the respective channels. It was possible to improve the degree of integration. Furthermore, even when a substrate such as a (111) substrate that is difficult to cut with a perpendicular cutting surface is used, it is possible to cut into a square chip.

[Brief description of drawings]

FIG. 1 is a perspective view illustrating a first embodiment of the present invention.

FIG. 2 is a perspective view illustrating a conventional method.

FIG. 3 is a curve diagram showing an example of an oxidation rate depending on crystal orientation.

FIG. 4 is a curve diagram showing the relationship between crystal orientation and mobility.

FIG. 5 is a sectional perspective view showing a second embodiment of the present invention.

FIG. 6 is a curve diagram showing a relationship between a crystal plane and Nss.

FIG. 7 is a perspective view showing a third embodiment of the present invention.

FIG. 8 is a characteristic diagram showing the relationship between the crystal axis, the channel direction, and the mobility.

FIG. 9 is a characteristic diagram showing a relationship between crystal axes, channel directions, and mobilities.

FIG. 10 is a perspective view showing a fourth embodiment of the present invention.

[Explanation of symbols]

1 ... (100) Silicon substrate 2 ... Insulating film 3 ... (11
0) Substrate 4 ... (100) Silicon substrate 5 ... Insulating film
6 ... (100) substrate 7 ... (211) substrate 8 ... Insulating film 9 ... NMOS 10
... PMOS 11 ... Gate 12 ... (011) substrate

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (10)

[Claims] 1. A single crystal thin film semiconductor device comprising two or more wafers having different crystal orientations bonded to each other, and elements being formed on these wafers. 2. At least one of the plane orientation of the wafer and the plane orientation of the wafer adhered thereon is a (100) plane, and at least one is a (111) plane. Item 1. A single crystal thin film semiconductor device according to item 1. 3. The surface orientation of the wafer and the surface orientation of the wafer adhered thereon are at least one (100) plane and at least one is a (110) plane. Item 1. A single crystal thin film semiconductor device according to item 1. 4. The at least one of the plane orientation of the wafer and the plane orientation of the wafer adhered thereon is a (110) plane, and at least one is a (111) plane. Item 1. A single crystal thin film semiconductor device according to item 1. 5. The plane orientation of the wafer and the plane orientation of the wafer adhered thereon are set to (110), and the crystal axes of the normal line to this plane are the rotation axes, and they are in rotation positions within the range of 43 to 48 degrees. The single crystal thin film semiconductor device according to claim 1. 6. The single crystal thin film semiconductor device according to claim 1, wherein the thickness of the wafer bonded onto the wafer is 0.1 μm or less. 7. The single crystal thin film semiconductor device according to claim 1, wherein heat treatment is used for bonding the wafer. 8. The single crystal thin film semiconductor device according to claim 1, wherein the bonding wafer is bonded by immersing it in a liquid having a low viscosity such as pure water and then drying it. 9. The wafer is adhered by using a silicon-based adhesive having a low viscosity, immersing the wafer to be adhered in the adhesive, adhering the wafers in a liquid, and then drying and solidifying the wafers. The single crystal thin film semiconductor device described. 10. The wafer is adhered by using an organic adhesive having a low viscosity, immersing the wafer to be adhered in the adhesive, bonding them in a liquid, and then drying and solidifying the wafer. The single crystal thin film semiconductor device described.