JPH0588913A - System interrupt device - Google Patents

Abstract

PURPOSE:To surely generate an interrupt to a main CPU during driving of a software program by sending a second interrupt signal to the main CPU at the time of not detecting the start of the stop operation of the main CPU within a prescribed time. CONSTITUTION:When generating an interrupt signal INT1, a PMU 13 sends this signal to a main CPU 11 and sets a timer 15. If a register read command is not received from the main CPU 11 by the PMU 13 within a prescribed time and the timer 15 expires, the timer 15 reports the elapse of the time to the PMU 13. Then, the PMU 13 generates an interrupt signal INT2 to the main CPU 11. Thus, the main CPU 11 is interrupted by the second signal INT2 sent after the certain time even if it is not interrupted by the interrupt signal INT1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system interrupt device which sends an interrupt signal for interrupting a main CPU while a software program is being driven.

[0002]

2. Description of the Related Art Conventionally, in a personal computer or the like, when a system interrupt is required, an interrupt signal, that is, an interrupt signal is sent to a main central processing unit (hereinafter referred to as "CPU"). For example, when the user activates the so-called resume function, this interrupt signal is issued. When the CPU receives the interrupt signal, the CPU suspends the operation of the system until the release signal is issued. When the release signal is issued, the system restarts from the interrupted position.

[0003]

However, in the conventional device, there is a problem that the desired interrupt cannot be applied unless the main CPU accepts the interrupt signal. For example, there is a case where the application program being executed is in a state of not accepting an interrupt when the interrupt signal is issued. In such a case, the resume function does not work even if the user tries to use the resume function.

The present invention solves the above-mentioned problems and provides a main CP
It is an object of the present invention to provide a system interrupt device which surely generates an interrupt for U while driving a software program.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides means for sending a first interrupt signal to a main CPU and, after sending the first interrupt signal, A detection means for detecting the presence / absence of an interrupt operation in the main CPU, and a means for sending a second interrupt signal to the main CPU when the detection by the detection means is not made within a predetermined period. It is prepared and configured.

[0006]

According to the present invention, when the software program currently being driven needs to be interrupted by the above configuration, the control system of the unit sends a first interrupt signal to the main CPU. After sending the first interrupt signal, the control system detects whether or not the main CPU has started the stop operation by the detection means. When the detecting means does not detect the start of the stop operation of the main CPU within a predetermined time, the control system sends a second interrupt signal to the main CPU.

[0007]

The present invention will be described below with reference to examples. Figure 1
FIG. 1 is a block diagram showing an embodiment of the present invention. INDUSTRIAL APPLICABILITY The present invention can be applied to various computers such as notebook type, laptop type, desktop type and the like.
FIG. 1 is an example of a case of implementation in a computer. A main CPU 11 that controls the entire system and drives an application program, and a power management CPU.
(Power Management CPU, hereinafter referred to as "PMU") 13 is connected to the system. PMU13
Is a central processing unit for controlling the power supply of each part of the computer. Further, the PMU 13 is equipped with a timer 15.

In this structure, while the application program is being executed, the PMU 1 should temporarily hold the necessary data so that the work of the personal computer can be temporarily stopped and the work can be resumed from the same state later.
Consider the case where the interrupt signal INT1 is applied from 3 to the main CPU 11.

At this time, in the main CPU 11, the application program does not accept the interrupt signal, that is, the interrupt signal INT1 is masked, or the application program has its own meaning. If it has been processed, the desired interrupt is not applied. When the interrupt is not applied, the main CPU 11 does not read the register of the PMU 13, so that it is understood that the PMU 13 does not receive the desired interrupt from the main CPU 11.

The operation flow for this determination is shown in FIG. When the PMU 13 generates the interrupt signal INT1 (step 21), it sends the signal to the main CPU 11 and sets the timer 15 (step 2).
2). The timer 15 starts counting time by this setting. If there is a register read command from the main CPU 11 to the PMU 13 before the timer 15 elapses a predetermined time (step 23), the timer 15 causes the PMU 13 to read.
Is reset by and the counting is stopped (step 2).
4). If the register reading command is not received within the predetermined time and the timer 15 counts up after the predetermined time has elapsed (step 25), the timer 15 causes the PMU 13
To inform the passage of time. Therefore, the PMU 13 causes the main CPU 11 to generate the interrupt signal INT2 (step 26). As a result, even if the interrupt signal INT1 is not interrupted, it is interrupted by the second signal INT2 issued after a certain period of time.

Next, the processing in the case where the application program also masks the interrupt signal INT2 will be described with reference to FIG. The hardware configuration is the same as in FIG.
First, when the computer user executes the function to use the resume function, the PMU 13 causes the timer 1 to operate.
Is set (step 31). Then interrupt signal INT
1 is generated (step 32), and timer 2 is set (step 33). The set of timer 1 and timer 2 is
The timer 1 is set beforehand at an appropriate time automatically or manually, but the set time is longer in the timer 1 than in the timer 2.

After the processing of step 33, the main CPU 1
It is judged whether or not 1 has read the register by receiving the signal (step 34), and if not, the timer 1
Determines whether a predetermined time has passed (step 35), and if that time has not passed, it is determined whether the timer 2 has passed a predetermined time (step 36). If the time has not passed in step 36, step 3 is performed again.
Return to 4.

When the register read signal is received in step 34, the timers 1 and 2 are reset because they are interrupted within the predetermined time (step 37), and this process ends.

In step 35, when the timer 1 has passed a predetermined time, it is impossible to interrupt within a certain time. Therefore, a display process of "Could not be suspended" is performed (step 38), and the process is ended. .. This allows the user to know that the resume function execution has failed. In the past, in order to determine whether or not the resume function has failed, the user had to look at the movement of the screen, etc., but by positively displaying the next action to the user. Can be urged.

Next, at step 36, when the timer 2 has passed a predetermined time, an interrupt signal INT2 is generated (step 39). Then, the timer 2 is set (step 40). Thereafter, it is judged whether or not the register read signal is received (step 41), and if not received, it is judged whether or not the timer 1 has passed a predetermined time (step 4).
2) If it has not elapsed, it is determined whether the timer 2 has elapsed a predetermined time (step 43). Step 43
If the timer 2 has not elapsed the predetermined time, the process returns to step 41.

At step 41, when the register read signal is received, that is, when the interrupt signal INT1 fails but the interrupt signal INT2 can be interrupted,
The timers 1 and 2 are reset (step 44), and the process ends.

In step 42, when the timer 1 has elapsed for a predetermined time, it is determined that the timer 1 has failed due to the interrupt signal INT1 or has failed to interrupt the interrupt signal INT1 and INT2 several times. This means that, in order to notify the user of the interrupt failure, the display processing of "Could not be suspended" is performed (step 45), and the processing is ended. This point is similar to step 38.

In step 43, when the timer 2 has not elapsed the predetermined time, the process returns to step 41. Step 43
Then, when the timer 2 has passed the predetermined time,
Since it is within the set time, the interrupt signal INT1 is generated again (step 46), the process returns to step 33, and the process is repeated.

As described above, even if the interrupt is interrupted by the second interrupt signal INT2 as well, if the timer 1 is within the fixed time, the interrupt signals INT1 and INT2 are repeatedly output to try the suspend process. It will be. This can reduce the troublesomeness of the repeated action of the user.

In addition, the interrupt signals INT1 and I are temporarily interrupted.
Even if both NT2s are masked by the application program, an interrupt is applied when the application program releases the masking.

Next, another embodiment will be described with reference to FIG. In the embodiment shown in FIG. 3, when the timer 1 counts up, the display processing of "Could not be suspended" is performed to the user. However, since the display will destroy the screen content, the subsequent processing Is required. Therefore, the method to be described next is a method of utilizing the processing of the instruction buffer instead of the screen display processing.

In FIG. 4, steps having the same reference numerals as those in FIG. 3 indicate the same processing contents, and therefore description thereof will be omitted. The difference is that when the predetermined time of the timer 1 has elapsed (step 35
And the processing after step 42). When the timer 1 counts up, it means that the user's resume instruction could not be executed. Therefore, the instruction that could not be executed is stored in the first-in first-out memory (FIFO memory), and the type of the stored instruction is determined (step 5).
0). At this time, in order to increase the processing speed, a table for each instruction is provided, and a flag is set in the table to determine whether the same instruction is stored again among the instructions that could not be executed. .. This is the process of determining the factor flag in step 50.

The cause flag is determined (step 5
0) If the cause is not already in the instruction buffer, the instruction buffer is processed (step 52). In the instruction buffer process, the instruction is put in the FIFO memory, and it is retried as an unexecuted instruction at a predetermined timing.
On the other hand, if the instruction is already in the instruction buffer in step 51, the instruction buffer processing as in step 52 is not performed (step 53).

Further, this point will be described in detail. Figure 5
It is assumed that an instruction table as described above is provided and the FIFO memory of FIG. 6 has instructions B, C, and N as unexecuted ones. If this resume function command is command C,
When the resume function cannot be executed, it is judged whether the instruction C in FIG. 5 has a flag (step 50). If the flag is present, the instruction C already exists in the FIFO memory, so the instruction buffer processing is not performed. This is the case (step 53).

However, when the flag of the instruction C has not been reached, there is no instruction C in the FIFO memory, so a flag is set at the instruction C in the instruction table and the instruction C is stored in the FIFO memory. When the instruction stored in the instruction buffer is executed, it disappears from the FIFO memory,
The corresponding flag in the instruction table is also cleared. Step 5
The contents of 4, 55, 56, and 57 are the same, so the description thereof will be omitted.

As described above, in the case of this embodiment, since this function is executed by the instruction buffer processing without notifying the user of the failure, the user also has the same consciousness as when a normal instruction fails. There is an advantage that you can know the instruction processing.

Further, since the interrupt process is tried after executing another instruction previously stored in the first-in first-out FIFO buffer, the instruction stored in the first-in first-out instruction buffer does not overflow.

Although the above description has been made with respect to two cases of the interrupt signals INT1 and INT2, it is not limited to two, and
The present invention can be applied to various types and levels.

[0029]

As described above, according to the present invention,
Even if the main CPU is driven by an application program that masks the interrupt signal or performs its own processing, the desired interrupt can be applied more reliably.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a flow chart for explaining the operation of one embodiment of the present invention.

FIG. 3 is a flowchart for explaining the operation of another embodiment of the present invention.

FIG. 4 is a flow chart for explaining the operation of still another embodiment of the present invention.

FIG. 5 is a diagram showing an instruction table according to an embodiment of the present invention.

FIG. 6 is a diagram showing a FIFO memory according to an embodiment of the present invention.

[Explanation of symbols]

 11 Main CPU 13 PMU 15 Timer

Claims (5)

[Claims] 1. An apparatus for sending an interrupt signal to a main CPU during driving of a software program, said means for sending a first interrupt signal to said main CPU, Second interrupt signal to the main CPU based on the fact that the main CPU does not detect the interrupt operation within a predetermined period after the interrupt signal is transmitted. A system interrupt device comprising: means for sending a signal. 2. The device according to claim 1, further comprising means for repeating the transmission of the first interrupt signal when the interrupt operation is not performed by the second interrupt signal.
System interrupt device. 3. An apparatus for transmitting an interrupt signal to a main CPU during driving a software program, said means for transmitting a first interrupt signal to said main CPU, and said first means. Means for setting the first timer means after sending the interrupt signal, and detecting means for detecting the presence or absence of an interrupt operation in the main CPU after sending the first interrupt signal. A means for sending a second interrupt signal to the main CPU based on the fact that the detection by the detection means is not made within a predetermined period by the second timer means, and the second interrupt signal is the second interrupt signal. Means for sending the first interrupt signal when the timer means does not perform within a predetermined time, and when the first timer means has elapsed a predetermined time, it indicates that the interrupt operation has not been performed. Display means for System interrupt device. 4. An apparatus for sending an interrupt signal to a main CPU during driving a software program, said means for sending a first interrupt signal to said main CPU, and said first means. Means for setting the first timer means after sending the interrupt signal, and detecting means for detecting the presence or absence of an interrupt operation in the main CPU after sending the first interrupt signal. A means for sending a second interrupt signal to the main CPU based on the fact that the detection by the detection means is not made within a predetermined period by the second timer means, and the second interrupt signal is the second interrupt signal. Means for sending the first interrupt signal when the timer means does not perform within a predetermined time, and when the first timer means has passed a predetermined time, the instruction for which the interrupt operation has not been performed is buffered. Store and
A system interrupt device comprising: an instruction executing means for executing an interrupt operation by an instruction process stored in the buffer. 5. An instruction table for determining an instruction that has not been executed, wherein the buffer is a first-in first-out memory, and when the interrupt operation is not performed, the instruction table is used for the determination. The system interrupt device according to claim 4.