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JPH0581447A - Microcomputer - Google Patents

Microcomputer

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Publication number
JPH0581447A
JPH0581447A JP3242223A JP24222391A JPH0581447A JP H0581447 A JPH0581447 A JP H0581447A JP 3242223 A JP3242223 A JP 3242223A JP 24222391 A JP24222391 A JP 24222391A JP H0581447 A JPH0581447 A JP H0581447A
Authority
JP
Japan
Prior art keywords
clock
inputted
selecting means
peripheral
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3242223A
Other languages
Japanese (ja)
Inventor
Yuichi Iizuka
裕一 飯塚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3242223A priority Critical patent/JPH0581447A/en
Publication of JPH0581447A publication Critical patent/JPH0581447A/en
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE:To prevent an unnecessary current from flowing by providing each peripheral device with a frequency divider and a clock selecting means of the fundametal clock which controls the peripheral function. CONSTITUTION:A CPU 101 to which a clock phi is inputted, a frequency divider 1021 to which the clock phi is inputted, a clock selecting means 1031 to which the output of the frequency divider 1021 is inputted, and a peripheral device 1041 to which the output of the means 1031 is inputted are provided. Further, frequency dividers 102N (N=2,3...) to which the clock phi is inputted, clock selecting means 103N to which outputs of frequency dividers 102N are inputted, and peripheral devices 104N to which outputs of clock selecting means 103N are inputted are provided. The clock 4 is inputted to the CPU 101, and required clock frequencies are selected from the clock, which has the frequency divided by frequency dividers 102N, by clock selecting means 103N and are inputted to peripheral devices 104N. An arbitrary clock is inputted to the peripheral device whose processing speed is not high, and an unnecessary current does not flow.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はマイクロコンピュータに
関し、特に中央処理装置(CPU)と周辺とを備えたマ
イクロコンピュータに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer having a central processing unit (CPU) and peripherals.

【0002】[0002]

【従来の技術】従来のマイクロコンピュータは、図4に
示すように、クロックφを入力とするCPU401と、
クロックφを入力とする周辺4021から周辺402N
(N=2,3,…)とを有している。
2. Description of the Related Art A conventional microcomputer includes, as shown in FIG.
Peripheral 4021 to peripheral 402N using clock φ as input
(N = 2, 3, ...).

【0003】CPU401と周辺4021〜402Nに
同じクロックφが入力されていたため、高速な処理速度
を要しない周辺にも、高速な処理速度を要するCPU,
周辺と同じクロックφが入力され、余分な電流が流れて
いた。
Since the same clock φ is input to the CPU 401 and the peripherals 4021 to 402N, a CPU requiring a high processing speed is required even in a peripheral which does not require a high processing speed.
The same clock φ as the peripheral was input, and an extra current was flowing.

【0004】[0004]

【発明が解決しようとする課題】前述した従来のマイク
ロコンピュータは、高速な処理速度をしない周辺にも高
速な処理速度を要するCPU、周辺と同じクロックφが
入力され、余分な電流が流れていた。そのため、余分な
消費電力が生まれ、マイクロコンピュータの破壊,寿命
に影響していた。さらに、自己発熱の上昇により、他の
装置にも悪影響を与えていた。
In the above-described conventional microcomputer, a CPU requiring a high processing speed is input to a peripheral that does not operate at a high processing speed, and the same clock φ as that in the peripheral is input, and an extra current flows. . Therefore, extra power consumption is generated, which affects the destruction and life of the microcomputer. Furthermore, the increase in self-heating also adversely affects other devices.

【0005】本発明の目的は、前記問題点を解決し、余
分な電流が流れないようにし、高信頼性を確保したマイ
クロコンピュータを提供することにある。
An object of the present invention is to solve the above problems and to provide a microcomputer in which an extra current is prevented from flowing and high reliability is ensured.

【0006】[0006]

【課題を解決するための手段】本発明の構成は、1つの
CPUと複数の周辺とをもつマイクロコンピュータにお
いて、前記周辺にそれぞれ前記周辺機能をコントロール
する基本クロックの分周器とクロック選択手段とを備え
ていることを特徴とする。
According to the structure of the present invention, in a microcomputer having one CPU and a plurality of peripherals, a basic clock frequency divider and a clock selecting means for controlling the peripheral functions are provided in the peripherals. It is characterized by having.

【0007】[0007]

【実施例】図1は本発明の第1の実施例のマイクロコン
ピュータを示すブロック図である。
1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

【0008】図1において、本発明の第1の実施例は、
クロックφを入力とするCPU101と、クロックφを
入力とする分周器1021と、分周器1021の出力を
入力とするクロック選択手段1031と、手段1031
の出力を入力とする周辺1041と、さらにクロックφ
を入力とする分周器102N(N=2,3,…)と、分
周器102Nの出力を入力とするクロック選択手段10
3Nと、クロック選択手段103Nの出力を入力とする
周辺104Nとを備えている。
Referring to FIG. 1, the first embodiment of the present invention is as follows.
CPU 101 that receives clock φ, frequency divider 1021 that receives clock φ, clock selection means 1031 that receives the output of frequency divider 1021, and means 1031
1041 that receives the output of
Frequency divider 102N (N = 2, 3, ...) Having the input and clock selecting means 10 having the output of the frequency divider 102N as the input
3N and a peripheral 104N to which the output of the clock selection means 103N is input.

【0009】図2は図1の分周器で分周されるクロック
を示す波形図である。
FIG. 2 is a waveform diagram showing a clock divided by the divider of FIG.

【0010】図2において、クロックφは、φ/2,φ
/4,φ/8と分周され、クロック選択手段1031〜
103Nで選択することにより、CPU101と、周辺
104N(N=1,2,…)の周期をとることが出来
る。
In FIG. 2, clock φ is φ / 2, φ
Clock selection means 1031 to 10
By selecting with 103N, the cycle of the CPU 101 and the peripheral 104N (N = 1, 2, ...) Can be taken.

【0011】次に図1も用いて動作について説明する
と、CPU101には、クロックφが入力される。周辺
104Nには、分周器102Nで分周されたクロックを
クロック選択手段103Nで、必要とされるクロック周
波数を選択し、選択されたクロックが入力される。
Next, the operation will be described with reference to FIG. 1. The clock φ is input to the CPU 101. To the peripheral 104N, the clock divided by the frequency divider 102N is used by the clock selecting means 103N to select a required clock frequency, and the selected clock is input.

【0012】これにより、高速な処理速度をしない周辺
には、任意のクロックが入力され、余分な電流は流れな
くすることが出来る。
As a result, an arbitrary clock is input to the periphery where the processing speed is not high, and an extra current can be prevented from flowing.

【0013】図3は本発明の第2の実施例のマイクロコ
ンピュータを示すブロック図である。
FIG. 3 is a block diagram showing a microcomputer according to the second embodiment of the present invention.

【0014】図3において、本実施例は、CPUに対す
るストップ機能301を備え、さらにストップ機能30
31から303Nは各周辺に対するストップ機能で、他
の構成は第1の実施例と同様である。
In FIG. 3, this embodiment is provided with a stop function 301 for the CPU and further a stop function 30.
Reference numerals 31 to 303N are stop functions for the respective peripherals, and other configurations are the same as those in the first embodiment.

【0015】ここで、全く使用しないCPU,各周辺
は、ストップ機能によりストップさせて全く電流を流さ
なくする。使用するCPU,各周辺に対しては、第1の
実施例と同様にすれば、より低消費電力化をすることが
出来る。
Here, the CPU, which is not used at all, and each peripheral are stopped by the stop function so that no current flows. If the CPU to be used and the peripherals are the same as in the first embodiment, the power consumption can be further reduced.

【0016】[0016]

【発明の効果】以上説明したように、本発明は、周辺に
それぞれ前記周辺機能をコントロールする基本クロック
の分周器とクロック選択手段を備えるようにしたので、
高速な処理速度を要しない周辺には、任意のクロックが
入力され、余分な電流は流れなくすることが出来るとい
う効果を有する。
As described above, according to the present invention, the basic clock divider and the clock selecting means for controlling the peripheral functions are provided in the periphery.
An arbitrary clock is input to the periphery that does not require a high processing speed, which has an effect that an extra current can be prevented from flowing.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例のマイクロコンピュータ
を示すブロック図である。
FIG. 1 is a block diagram showing a microcomputer according to a first embodiment of the present invention.

【図2】図1の分周器で分周されるクロックの例を示す
波形図である。
FIG. 2 is a waveform diagram showing an example of a clock divided by the divider of FIG.

【図3】本発明の第2の実施例を示すブロック図であ
る。
FIG. 3 is a block diagram showing a second embodiment of the present invention.

【図4】従来のマイクロコンンピュータを示すブロック
図である。
FIG. 4 is a block diagram showing a conventional micro-computer.

【符号の説明】[Explanation of symbols]

101,302,401 CPU 1021,102N,3041,304N,4021,
402N 分周器 1031,103N,3051,305N クロック
選択手段 1041,104N,3061,306N,4021,
402N 周辺 301,3031,303N ストップ機能
101, 302, 401 CPU 1021, 102N, 3041, 304N, 4021
402N frequency divider 1031, 103N, 3051, 305N clock selecting means 1041, 104N, 3061, 306N, 4021
402N peripheral 301,3031,303N Stop function

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 1つの中央処理装置と複数の周辺とをも
つマイクロコンピュータにおいて、前記周辺にそれぞれ
前記周辺機能をコントロールする基本クロックの分周器
とクロック選択手段とを備えたことを特徴とするマイク
ロコンピュータ。
1. A microcomputer having one central processing unit and a plurality of peripherals, characterized in that each of the peripherals is provided with a basic clock frequency divider for controlling the peripheral functions and a clock selecting means. Microcomputer.
JP3242223A 1991-09-24 1991-09-24 Microcomputer Pending JPH0581447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3242223A JPH0581447A (en) 1991-09-24 1991-09-24 Microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3242223A JPH0581447A (en) 1991-09-24 1991-09-24 Microcomputer

Publications (1)

Publication Number Publication Date
JPH0581447A true JPH0581447A (en) 1993-04-02

Family

ID=17086067

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3242223A Pending JPH0581447A (en) 1991-09-24 1991-09-24 Microcomputer

Country Status (1)

Country Link
JP (1) JPH0581447A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08179847A (en) * 1994-12-26 1996-07-12 Sony Corp Clock signal generator
US5774702A (en) * 1994-11-22 1998-06-30 Hitachi, Ltd. Integrated circuit having function blocks operating in response to clock signals
US6211715B1 (en) 1997-03-31 2001-04-03 Nec Corporation Semiconductor integrated circuit incorporating therein clock supply circuit
JP2003022145A (en) * 2001-07-05 2003-01-24 Fujitsu Ltd Clock controller and method for controlling clock

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5774702A (en) * 1994-11-22 1998-06-30 Hitachi, Ltd. Integrated circuit having function blocks operating in response to clock signals
JPH08179847A (en) * 1994-12-26 1996-07-12 Sony Corp Clock signal generator
US6211715B1 (en) 1997-03-31 2001-04-03 Nec Corporation Semiconductor integrated circuit incorporating therein clock supply circuit
JP2003022145A (en) * 2001-07-05 2003-01-24 Fujitsu Ltd Clock controller and method for controlling clock
JP4686065B2 (en) * 2001-07-05 2011-05-18 富士通セミコンダクター株式会社 Clock control apparatus and clock control method

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