JPH056621A - Medium and apparatus for recording digital data - Google Patents

Abstract

PURPOSE:To judge the logics of digital data accurately. CONSTITUTION:Reference data are recorded,in a magneto-optical disk in synchronization with a clock in opposite phase with respect to the case of digital data. In regeneration, the reference data are read in synchronization with the clock in the positive phase in a reference reading circuit 68. In averaging circuits 63 and 64, the levels of the reference data which are read with the reference reading circuit 68 are averaged, and threshold levels TH1 and TH2 are outputted into comparing circuits 61 and 62, respectively. In the comparing circuits 61 and 62, the data which are reproduced from a magneto-optical disk are compared with the threshold levels TH1 or TH2, and the logic is judged.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data recording medium and a recording device suitable for use in, for example, a magneto-optical disk and a magneto-optical disk device.

[0002]

2. Description of the Related Art In a magneto-optical disk, a partial response method may be used when recording data digitally. When the recording is performed by the partial response method, the reproduction signal is a ternary signal of 1, 0 or -1. When reading this reproduction signal, threshold levels are set between -1 and 0 and between 0 and 1, respectively, and it is determined which logic is based on the threshold level.

[0003]

Information is not always recorded continuously on a magneto-optical disk.
After the predetermined information is recorded, some days have passed and then other information is recorded. Therefore, the recording condition is not always constant. For example, when the power of the laser beam during information recording changes, the size of the mark (pit) formed on the magneto-optical disk also changes. Further, since the magneto-optical disk once recorded is not always reproduced in the same device, its reproduction condition (for example, frequency characteristic) may vary during reproduction.

As described above, since the level of the reproduced signal changes when the conditions during recording or reproduction change,
If the threshold level for determining the logic is fixed, there is a risk that the logic may be erroneously determined.

The present invention has been made in view of such a situation, and makes it possible to accurately determine a logic.

[0006]

In the digital data recording medium of the present invention, a block composed of, for example, a sector is further divided into a data recording area and a control data recording area at a position preceding the data recording area, and control data is recorded. At the beginning of the recording area, reference data for setting the threshold level for judging the logic of the digital data recorded in the data recording area is recorded in synchronization with the clock of the opposite phase to the digital data in the data recording area. It is characterized by

Further, in the digital data recording apparatus of the present invention, reference data for setting a threshold level for judging the logic of digital data is generated in synchronization with a clock having a phase opposite to that of the clock for recording the digital data. It is characterized in that it is provided with a reference data generating means.

In the embodiment, the reference data generating means is composed of the reference generating circuit 51.

[0009]

In the digital data recording medium having the above structure, each sector is divided into a data recording area and a control data recording area, digital data is recorded in the data recording area, and the data recording area is provided at the beginning of the control data recording area. Reference data is recorded in synchronism with a clock having a phase opposite to the clock of the digital data in. Therefore,
When reading the reference data on the playback device,
It is possible to realize a recording medium that can be easily read because it is not necessary to make clocks in opposite phases.

Further, in the digital data recording apparatus having the above structure, the reference data is generated in synchronization with the clock having a phase opposite to that of the digital data. Therefore, it becomes possible to easily set the threshold level for judging the logic of digital data from the reference data without adding a clock inverting circuit in the reproducing apparatus.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION In the digital data recording medium and recording apparatus of the present invention, digital data is recorded and reproduced by the partial response method. Therefore, first, the principle of recording / reproducing in the partial response system will be described.

FIG. 2 is a block diagram for explaining the principle of recording and reproduction by the partial response method. The encoder 1 encodes write data input from a circuit (not shown). The data encoded by the encoder 1 is supplied to and recorded on the magneto-optical disc 2. Then, the data reproduced from the magneto-optical disk 2 is supplied to the decoder 3, is decoded, and the data output from the decoder 3 is input to the multi-level discriminating circuit 4, and the logical 1
It is determined whether it is 0 or -1, and it is output as demodulated data.

Now, for example, the NRZI system (PR (1,-
Assuming that the digital data is modulated according to 1)), the encoder 1 can be configured as shown in FIG. That is, the encoder 1 includes an adder 11 that performs modulo 2 addition and a delay circuit 12 that delays the input data by 1 bit and outputs the delayed data. The adder 11 adds modulo 2 to the input data and the data supplied from the delay circuit 12, and outputs the result. The delay circuit 12 delays the output of the adder 11 and outputs it to the adder 11 again. In this way, for example, 0100110 as shown in FIG.
The input digital data consisting of 01000 is 01110
It is supplied to the magneto-optical disk 2 as 1110,000 and recorded.

On the other hand, the decoder 3 is composed of a subtractor 21 and a delay circuit 22, as shown in FIG. 4, for example. The data reproduced from the magneto-optical disk 2 is supplied to the subtractor 21, and after being delayed by one bit by the delay circuit 22, it is supplied to the subtractor 21. The subtractor 21 calculates the difference between both inputs and outputs the difference to the multi-value discrimination circuit 4.

As a result, for example, 0111 shown in FIG.
The recording data of the magneto-optical disk 2 including the data of 01110000 is processed by the decoder 3 and 0100-1
Multi-value discrimination circuit 4 as ternary data of 100-1000
Will be supplied to.

The eye pattern of the data input to the multi-level discriminating circuit 4 is as shown in FIG. Multi-value discrimination circuit 4
Determines whether the data is -1 or 0 with reference to the threshold level TH1 in FIG. 6, and with reference to the threshold level TH2,
It is determined whether it is 0 or 1.

The decoder 3 shown in FIG. 4 can be omitted if it is substantially formed by a magnetic head, an amplifier, a high frequency compensating circuit, etc. in the reproducing system.

Next, an embodiment of the digital data recording and reproducing apparatus of the present invention will be described with reference to FIG.
In the figure, for example, a sample servo type magneto-optical disk 31 (corresponding to the magneto-optical disk 2 in FIG. 2).
Is rotated by a spindle motor 32 controlled by a spindle servo circuit 33, and data is recorded by an optical head 34 and a magnetic head 35.

The drive circuit 36 includes a write encoder 37.
The magnetic head 35 is driven according to the output of the. The write encoder 37 drives a laser drive circuit 39 via a laser power control circuit 38 to drive a laser diode (not shown) built in the optical head 34.

The signal reproduced from the magneto-optical disk 31 by the optical head 34 is input to the matrix amplifier 40 and reproduced from the magneto-optical area and the sum signal (PRF signal) obtained from the servo byte section of the magneto-optical disk 31. Signal (MORF signal) and a focus error signal. The PRF signal is input to the PLL circuit 41 and the A / D converter 43. The servo clock generated by the PLL circuit 41 is supplied to the timing generator 42, the A / D converter 43, the address decoder 44, the tracking error signal generation circuit 45, the tracking and focus servo circuit 46, and the gray code decoder 47, respectively. The data clock generated by the PLL circuit 41 is supplied to the write encoder 37, the timing generator 42, the A / D converter 48, the MO decoder 49, the reference generation circuit 51, and the like.

The output of the A / D converter 43 is supplied to the address decoder 44, the tracking error signal generating circuit 45, and the gray code decoder 47. Various timing signals generated by the timing generator 42 are supplied to the write encoder 37, the laser power control circuit 38, the SCSI / ECC circuit 50, the reference generation circuit 51, and the like.

The MORF signal is supplied to the MO decoder 49 via the A / D converter 48. The output of the MO decoder 49 is supplied to the SCSI / ECC circuit 50. The SCSI / ECC circuit 50 exchanges data with a host interface (not shown).

Next, the operation will be described. In the recording mode, recording data is input to the SCSI / ECC circuit 50 via a host interface (not shown). The SCSI / ECC circuit 50 performs processing such as adding an error detection code and interleaving on the input digital data, and outputs it to the write encoder 37. The write encoder 37 performs the above-described processing of the partial response system (processing of the encoder 1 in FIG. 2) on the input data, and then, the drive circuit 3 corresponding to the data.
The magnetic head 35 is driven via 6. Magnetic head 35
Applies an N pole (for example, logic 1) or S pole (logic 0) magnetic field to the magneto-optical disk 31 in accordance with the recording data.

On the other hand, the laser power control circuit 38
When a write command is input from the write encoder 37, the optical head 34 is transmitted via the laser drive circuit 39.
The laser diode of is emitted at the level in the recording mode. As a result, the laser light emitted from the optical head 34 is applied to the magneto-optical disk 31. In this way, digital data is recorded on the magneto-optical disk 31 by the so-called magnetic field modulation method.

Next, in the reproduction mode, the laser power control circuit 38 drives the laser diode of the optical head 34 via the laser drive circuit 39, and the level of the laser light emitted from the laser diode is changed to the reproduction level (level during recording). Weaker level). Then, the optical head 34 receives the reflected light of the laser light with which the magneto-optical disk 31 is irradiated, and the matrix amplifier 40
Outputs a MORF signal. This MORF signal is a signal reproduced from the magneto-optical recording layer on the magneto-optical disk 31. This MORF signal is converted to A by the A / D converter 48.
After being D / D converted, it is input to the MO decoder 49.

The MO decoder 49 operates the decoder 3 and the multilevel discriminator circuit 4 shown in FIG. The MO decoder 49 further decodes the data demodulated into three values of 1, 0 and -1 into the original digital data of 1 and 0. Then, the output of the MO decoder 49 is input to the SCSI / ECC circuit 50, subjected to processing such as deinterleaving, error detection and correction, and then output to a device (not shown) via the host interface.

In the above recording mode and reproduction mode, the servo circuit 46 controls the optical head 34 based on the focus error signal output from the matrix amplifier 40.
The objective lens built in is driven to perform focus control. Further, the tracking error signal generation circuit 45 has a PR corresponding to the wobbled pit in the servo byte section.
Generate a tracking error signal from the F signal level,
It is output to the servo circuit 46. The servo circuit 46 controls the tracking of the optical head 34 in response to the tracking error signal. The address decoder 44 also reads the address data in the servo byte section and outputs the read result to the timing generator 42. The timing generator 42 supplies a timing signal to each part at a predetermined timing corresponding to the input address data.

The Gray code decoder 47 detects a Gray code in the servo byte section and outputs the detection result to the servo circuit 46. The servo circuit 46 is
The position of the optical head 34 is determined from the output of the Gray code decoder 47, and the optical head 34 is moved to a desired track.

The PLL circuit 41 extracts a signal from a clock pit, which serves as a reference for executing various operations as described above, from the output of the matrix amplifier 40, and generates a clock signal in synchronization with this. Then, this clock signal is supplied to various circuits.

Next, a method of setting the threshold level in the above embodiment will be described. For example, when the eye pattern of the reproduction signal is as shown in FIG. 8, the threshold level TH1 between -1 and 0 is set on the line connecting the points A1 and A2. Further, the threshold level TH2 between 0 and 1 is set on the line connecting the points B1 and B2.
When the threshold level is set at this position, even if the clock shifts before and after it due to the jitter, the margin becomes maximum and the threshold becomes strong against the jitter. For example −
Although it is possible to set each threshold level to a level intermediate between 1 and 0, or 0 and 1, the width of the threshold level in the horizontal direction becomes narrower and the margin for jitter becomes narrower. .
Therefore, it is preferable to set the threshold level on the line connecting the points A1 and A2 and the points B1 and B2 as in the embodiment.

Therefore, in the present invention, reference data for setting this threshold level (see FIG. 8) is used.
Data that can obtain the eye pattern as shown in
Are recorded in advance on the magneto-optical disk 31.

The magneto-optical disk 31 is divided into a plurality of sectors, and data is recorded in each sector according to the format shown in FIG. That is, 1
Each sector is composed of 152 rows, and one row is composed of 5 bytes of data. Of the continuous 10 bytes of 2 rows, the first 2 bytes are the servo bytes, and the subsequent 8 bytes are the data bytes for recording various data. An ID code including an address and the like is arranged in the first two rows of data bytes. The second 2-row data byte contains the ALPC for controlling the preamble and laser power intensity.
The data is located. The third 2 rows of data bytes are used as a reference area, and reference data for setting the threshold level is recorded therein.

In the data bytes of the following 130 rows,
Data (video data, audio data, etc.) that should originally be recorded and reproduced is recorded. Then, the error detection and correction code (ECC) is added to the data bytes of the last 16 rows.
Is recorded.

The above-mentioned ID code is formed in advance as prepits on the magneto-optical disk 31, and various data after the second row of the second row are recorded as needed on the magneto-optical recording layer of the magneto-optical disk 31. Will be recorded above.

Reference generation circuit 51 shown in FIG.
Generates reference data as shown in FIG. 10, for example, in synchronization with a clock having a phase opposite to the clock generated by the PLL circuit 41, and outputs the reference data to the write encoder 37. The write encoder 37 arranges this reference data in the reference area of the format shown in FIG. 9, supplies it to the magnetic head 35 via the drive circuit 36, and records it on the magneto-optical disk 31. That is, the reference data is recorded at the beginning of each sector.

At the time of reproduction, the MO decoder 49 has a built-in multilevel discriminating circuit 4 having a structure as shown in FIG. 1, for example, in order to set the threshold level by referring to the reference data. In this embodiment, the decoder 3
The output data is supplied to the comparison circuits 61 and 62 and the reference reading circuit 68.
The output of the reference reading circuit 68 is the averaging circuits 63 and 6
4 and the outputs of the averaging circuits 63 and 64 are used as threshold levels TH1 and TH2, respectively.
1 and 62. Then, the outputs of the comparison circuit 61 and 62 are output as the determination signals of logic 1 or logic -1, respectively, and the result calculated by the logic circuit including the inverters 65 and 66 and the AND gate 67 is logic 0. It is designed to be output as a determination signal.

Next, the operation will be described. The reference reading circuit 68 separates the reference data from the data supplied from the decoder 3 and reads the reference data. At this time, the clock generated by the PLL circuit 41 of FIG. 7 remains unchanged (without phase inversion) of the reference reading circuit 6
8 are being supplied. Therefore, as shown in FIG. 11, the reference reading circuit 68 reads the level of the reference data recorded in synchronization with the clock whose phase is inverted at the timing synchronized with the rising edge of the clock. As shown in FIG. 8, points A1, A2, B1, and B2, which serve as reference points for setting the threshold level, are located at positions synchronized with the falling edge of the clock. Therefore, in the present embodiment, the phase of the clock is inverted when the reference data is recorded, and the reproduced reference data is read in synchronization with the rising edge of the clock that is not inverted during the reproduction. The level of the reference signal at is detected.

The averaging circuit 63 averages low-level read data among the read data output by the reference reading circuit 68. As a result, the threshold level TH1 set between -1 and 0 is set. Then, this threshold level TH1 is supplied to the comparison circuit 61. Similarly, the averaging circuit 64
Of the read data output from the reference read circuit 68 averages the high-level read data and outputs the average value to the comparison circuit 62 as the threshold level TH2.

The comparison circuit 61 compares the reproduction data supplied from the decoder 3 with the threshold level TH1 supplied from the averaging circuit 63, and outputs a logic 1 when the reproduction data is smaller than the threshold level TH1. When it is larger, a logical 0 is output. In addition, the comparison circuit 62
Compares the reproduction data with the threshold level TH2 supplied from the averaging circuit 64, and outputs a logic 1 when the reproduction data is higher than the threshold level TH2, and outputs a logic 0 when the reproduction data is smaller than the threshold level TH2.

The outputs of the comparison circuits 61 and 62 are inverted by inverters 65 and 66, respectively, and then input to an AND gate 67 to calculate the logical product. Thus, when the outputs of the comparison circuits 61 and 62 are both logic 0, the AND gate 67 outputs a logic 1, and when at least one of the comparison circuits 61 and 62 is a logic 1, the AND gate 67 outputs a logic 1. The output will be a logic zero. Therefore, from the outputs of the comparison circuit 61, the AND gate 67 and the comparison circuit 62, a judgment output of -1, 0 or 1 can be obtained.

In the above description, when the digital data is recorded, the reference data for setting the threshold level is recorded at the same time. However, the read-only ROM data should also be recorded in advance. You can Further, in the above embodiment, the case where the data is recorded by the magnetic field modulation method has been described as an example, but the present invention can be applied to the case where the data is recorded by the optical modulation method.

In the above embodiment, the reference data is recorded in units of sectors.
Not limited to the sector, it can be placed at the beginning of a predetermined block.

[0043]

As described above, according to the digital data recording medium of the present invention, the reference data is recorded at the beginning of the control data recording area in synchronization with the clock having a phase opposite to that of the digital data in the data recording area. Because I did
Even in a reproducing apparatus that does not have a device that inverts a clock, it is possible to realize a digital data recording medium that can determine the threshold level based on the reference data and accurately determine the logic.

Further, according to the digital data recording apparatus of the present invention, the reference data is recorded in synchronization with the clock having a phase opposite to that in the case of recording the digital data, so that the reference data is read in the reproducing apparatus. Eliminates the need to reverse the clock. Therefore, it is possible to accurately determine the logic.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a multi-value identification circuit 4 in an MO decoder 49 of the embodiment of FIG.

FIG. 2 is a block diagram illustrating a recording / reproducing principle of a partial response system.

FIG. 3 is a block diagram showing a configuration example of an encoder 1 in the embodiment of FIG.

FIG. 4 is a block diagram showing a configuration example of a decoder 3 in the embodiment of FIG.

5 is a timing chart explaining the operation of the embodiment of FIG.

FIG. 6 is an eye pattern diagram for explaining the operation of the embodiment of FIG.

FIG. 7 is a block diagram showing a configuration of an embodiment of a digital data recording device of the present invention.

FIG. 8 is a diagram illustrating a phase relationship between an eye pattern of reference data and a clock in the embodiment of FIG.

FIG. 9 is a diagram for explaining a format of a sector of the magneto-optical disk 31 in the embodiment of FIG.

FIG. 10 is a waveform diagram illustrating phases of write reference data and an inverted clock.

FIG. 11 is a diagram illustrating the phases of a reproduction reference signal and a clock.

[Explanation of symbols]

1 encoder 2 magneto-optical disk 3 decoder 4 Multi-value discrimination circuit 11 adder 12 Delay circuit 21 Subtractor 22 Delay circuit 31 magneto-optical disk 34 Optical head 35 magnetic head 36 Drive circuit 37 Writing encoder 40 matrix amplifier 41 PLL circuit 45 Tracking error signal generation circuit 46 Servo circuit 49 MO decoder 51 Reference generator 61, 62 comparison circuit 63, 64 averaging circuit 68 Reference reading circuit

Claims (2)

[Claims] 1. A digital data recording medium in which digital data is recorded by dividing it into blocks, and the blocks are further divided into a data recording area and a control data recording area at a position preceding the data recording area. At the beginning of the control data recording area, reference data for setting a threshold level for judging the logic of the digital data recorded in the data recording area is used as a clock having a phase opposite to that of the digital data in the data recording area. A digital data recording medium characterized by being recorded in synchronization. 2. A clock generation means for generating a clock, a reference data generation means for generating reference data for setting a threshold level for judging the logic of digital data in synchronization with a clock of an opposite phase, and the reference data. Is arranged at the beginning of a predetermined block, and recording means for recording on a recording medium is provided.