JPH0564820B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a direct memory access control method,
Channel data necessary for controlling data transfer between the memory and the input/output device is stored in the storage means, and the channel data indicated by the channel data address holding section is fetched from the storage means to control the data transfer, and the data transfer is controlled. By setting the chain channel data address in the channel data address holding section in response to the completion of the transfer, channel data chaining becomes possible and transfer control of a plurality of data can be performed continuously.

[Industrial application field]

This invention uses direct memory access (hereinafter referred to as "direct memory access"), which directly controls data transfer between memory and input/output devices, in information processing devices using microprocessors, especially in facsimile devices that transfer high-density image information at high speed. (referred to as ``DMA''.) Concerning control methods.

[Conventional technology]

Conventional facsimile devices require high-speed data transfer between the device's internal memory and input/output devices, so the microprocessor (main control section) does not directly control data transfer.
Typically, a DMA controller controls data transfers between memory and input/output devices independent of microprocessor operation.

FIG. 3 is a block diagram illustrating a conventional DMA control method used in facsimile devices.

Under the control of the DMA control device 300, the memory 3
Data transfer is performed between 50 and input/output device 360.

Register group 310 of DMA control device 300 that holds channel data necessary for data transfer control
are a control register 311, a status register 312,
It is composed of an address register 313 and a transfer word count register 314. The control register 311 stores information indicating the type of operation (direction of data transfer between memory and input/output device), and the status register 312 stores information indicating the status of data transfer at that time. Register 313 stores address information of a memory from which data is to be read or written, and transfer word count register 314 stores information on the amount of data to be transferred.

The operation of sequentially transferring a plurality of data blocks 351 to 354 in the memory 350 to the input/output device 360 will be described below.

The microprocessor 370 is connected to a common bus 380.
from the memory 350 to the control register 311 in the DMA control device 300 via the input/output device 3
The address register 313 holds the storage address of the data block 351, and the transfer word count register 314 holds the number of words in the data block 351.

Here, the microprocessor 370 instructs the input/output device 360 to start the data output operation. From then on, microprocessor 370 is freed from data transfer operations and can perform other tasks.

On the other hand, the control unit 330 of the DMA control device 300
Based on the channel data held in the register group 310 and in accordance with the data transfer request signal 391 of the input/output device 360, the data block 351 in the memory 350 is sequentially read and transferred to the input/output device 360. The data transfer here is
Word by word, the value in the address register 313 is incremented by 1, and the value in the transfer word count register 314 is subtracted by 1, until the subtraction result in the transfer word count register 314 becomes 0, in accordance with the timing of the data transfer request.

When all data blocks 351 have been transferred, the control section 330 of the DMA control device 300 writes data transfer end information to the status register 312, and also notifies the microprocessor 370 of the end of data transfer by a normal interrupt signal 393. . The microprocessor 370 uses the interrupt to refer to the status register 312 in the DMA control device 300 and recognizes that the transfer of the data block 351 has been completed.

Microprocessor 370 then controls control register 31 in DMA controller 300 to transfer data block 352 to input/output device 360.
1 and causes the address register 313 to hold the first storage address of the data block 352,
By setting the number of words in the block in the transfer word count register 314, the DMA control device 30
0 starts data transfer to the input/output device 360 again. Thereafter, similar operations are repeated to sequentially transfer data blocks 353 and 354 in memory 350 to input/output device 360.

[Problem that the invention seeks to solve]

However, in such a conventional system, when a plurality of data blocks 351 to 354 are sequentially transferred as described above, control by the microprocessor 370 must be used each time each block is switched. That is, for example, when the transfer of the first data block 351 is completed, data transfer control between the memory 350 and the input/output device 360 is transferred from the DMA control device 300 to the microprocessor 370, and the next data transfer is started again. An instruction is issued to the DMA control device 300.

At this time, the microprocessor 370 recognizes that the interrupt signal indicating the end of the data transfer is an interrupt from the DMA control device 300 and indicates the end of the data transfer of the data block 351, and also sends the interrupt signal to the DMA control device 300. On the other hand, it was necessary to set channel data necessary for data transfer of the next data block 352 in the register group 310.

In this manner, the last data word of data block 351 is transferred before the next data block 35 is transferred.
Until the first data word in 2 is transferred,
The microprocessor 370 is processing control information, and the input/output device 360 is in a state of waiting for data transfer.

Here, if the input/output device 360 is a line input/output device connected to a line via a modem and a network control device, for example, if the data transmission speed of the connected line is about 64 kbit/s, the data The permissible range of the transfer waiting state is 1/(64000/8)=125×10 ^-6 [seconds], assuming that one word is 8 bits.

The allowable time for waiting for data transfer is a fairly strict condition for the processing speed of the microprocessor that performs the above-mentioned processing, and to cope with this, a dedicated microprocessor or a high-speed microprocessor is usually used. The need arose.

The present invention solves these conventional problems by providing a DMA control method that can continuously transfer a plurality of blocks of data without the intervention of a microprocessor. With the goal.

[Means for solving problems]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the channel data holding unit 101 is
Holds channel data for controlling data transfer between memory and input/output devices.

Control means 102 controls data transfer between the memory and the input/output device based on this channel data.

The channel data storage unit 103 stores channel data to be written to the channel data holding unit 101 and a storage address for the channel data to be subsequently written.

Channel data address holding unit 104 holds a storage address of channel data written to channel data holding unit 101.

Chain channel data address holding unit 105
holds the storage address of the channel data to be written subsequently.

The rewriting control means 106 performs rewriting control of the channel data that has been addressed and read by the channel data address holding section 104, and when the data transfer control using the channel data of the channel data holding section 101 is completed. , rewrites the address held in the channel data address holding unit 105 to the channel data address holding unit 104.

[Effect]

According to the address set in the channel data address holding unit 104 during data transfer control, channel data is fetched from the channel data storage unit 103 into the channel data holding unit 101 via the rewriting control unit 106, and the control unit 102 Data transfer control between the memory and the input/output device is performed based on the data.

The channel data storage unit 103 in which channel data is stored stores the storage address of the channel data to be chained, and the read address is held in the chain channel data address holding unit 105.

Upon completion of transfer of data indicated by one channel data, the rewrite control means 106 transfers the address held in the chain channel data address holding unit 105 to the channel data address holding unit 104.
The channel data specified by the address is continuously stored in the channel data holding unit 101.
By importing data into a data block, channel data can be chained, and transfer control of a plurality of data blocks can be performed continuously.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a block configuration diagram showing the configuration of an embodiment of the present invention. Note that this embodiment is an example of a configuration related to data transfer control between a memory and a line input/output device in a facsimile device.

Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The channel data holding unit 101 is a control register.
CT211, status register ST212, address register AD213 and transfer word count register BC2
14, the channel data address holding unit 1
04 corresponds to the channel address register 216, and the channel data address holding section 10
6 corresponds to value chain register NX215.
Each register constitutes a register group 210.

The control means 102 corresponds to the control section 230.

Channel data storage means 103 includes memory 25
0, and stores channel data 255 to 257 including the address of the channel data and data blocks 251 to 153.

The rewrite control means 106 is a read/write control unit 2
It corresponds to 20.

Note that the register group 210, the read/write control section 220, and the control section 230 constitute the DMA control device 200.

Configuration of Embodiment Embodiments of the present invention will be described below, assuming that the above-mentioned correspondence exists.

In FIG. 2, a microprocessor 270 is connected to a DMA controller 20 via a common bus 280.
0, memory 250 and input/output device 260 are connected. The memory 250 is composed of a RAM (random read/write memory), and stores a plurality of data blocks 251 to 253 and channel data 255 to 257 corresponding to each data block. The input/output device 260 connects to a communication line 265 via a modem 261 and a network control unit NCU 263.
connected to.

The DMA control device 200 includes a register group 210 that holds channel data necessary for data transfer control.
, a read/write control section 220 that controls reading and writing of channel data between the memory 250 and the register group 210, and a control section 230. The control section 230 is connected to the register group 210 and the read/write control section 220, receives a data transfer request signal 291 from the input/output device 260, and sends an interrupt signal 293 to the microprocessor 270.

Operation of Embodiment In this embodiment, the data blocks 251 to 253 in the memory 250 are transferred to the input/output device 260 and the modem 2.
61 and the network control unit NCU 263 to the communication line 265 will be described. Note that the data block 25 in the memory 250
Channel data 255 to 257 necessary to control the transfer of data 1 to 253 to the input/output device 260 are stored in a part of the memory 250 in advance.

The microprocessor 270 sets the address where the channel data 255 necessary for transferring the data block 251 is stored in the channel address register 216 for the DMA control device 200, and also sends the data to the input/output device 260. instruct them to do so.

The input/output device 260 includes a microprocessor 27
Upon receiving the instruction to start transmission from 0, the data transfer request signal 291 is sent to the DMA control device 200.

This data transfer request signal 291 is input
The control unit 230 of the DMA control device 200 activates the read/write control unit 220, reads the channel address register 216, and controls the channel data within the address set in the register to be read into the register group 210. That is, the control data CT, status data ST, address data AD, transfer word count data BC, and chain address NX of channel data to be chained are stored in the control register 211, status register 212, and channel data 255 corresponding to the data block 251, respectively. Address register 213, transfer word count register 214 and chain register 215
will be written to.

The control unit 230 determines by the control register 211 that data is to be transferred from the memory 250 to the input/output device 260, and reads the first word of the data block 251 according to the address set in the address register 213. Input/output device 260
Transfer to. At this time, address register 213
The value of the transfer word count register 214 is updated by 1, and the value of the transfer word count register 214 is subtracted by 1.

The input/output device 260 converts one word of data transferred from the memory 250 into serial data one bit at a time, and sends it to the modem 261 and network control unit NCU 26.
3 to the communication line 265. At the same time, a data transfer request signal 291 is sent to the control unit 230 of the DMA control device 200.

Thereafter, similar operations are repeated to sequentially transfer all data in the data block 251. When all data blocks 251 are transferred to the input/output device 260 and further transmitted to the communication line 265,
Transfer word count register 214 of DMA control device 200
The subtraction result becomes 0, and the control unit 230 writes to the status register 212 that the transfer of the data block 251 has been completed. At the same time, the control unit 230 checks the contents of the control register 211 and, if there is an instruction to perform a data chain, instructs the read/write control unit 220 to write the value of the chain register 215 to the channel address register 216.

The chain address data held in the chain register 215 is the storage address of the channel data 256 necessary for transferring the data blocks 252 that are continuously transferred. The channel data 256 at the address specified by is stored in the register 211 of the register group 210.
~ 215 and notifies the control unit 230 of register setting completion, the control unit 2
30 starts operating, and data block 2 is continuously
52 transfer is started.

Similarly, the data block 253 is transferred to the input/output device 260, but the data block 253
If the control data of the channel data 257 corresponding to the data transfer does not instruct the data chain, the control unit 230 sends a command to the microprocessor 270 when all the data in the data block 253 has been transferred. interrupt signal 29
3 to notify the end of data transfer.

Modifications of the Invention In this embodiment, a DMA control method performed between one input/output device and a memory in a method of sequentially chaining a plurality of data blocks and performing continuous data transfer has been described. The same can be realized in data transfer between an input/output device and a memory.

In that case, in accordance with the data transfer request signal notified to the control unit 230 from one of the plurality of input/output devices, the channel address register 216
, the corresponding channel data is loaded into the register group 210, data is transferred word by word, and then the channel data is returned. The address setting of the channel address register 216 can be performed without increasing the hardware by reading the data stored in the fixed address of the memory 250 corresponding to the input/output device that sent the data transfer request signal. It can support simultaneous control of output devices.

Note that the plurality of input/output devices include, in addition to the device for inputting and outputting data to and from the communication line shown in this embodiment, for example, a keyboard for inputting data, a display for outputting information, a scanner for reading a transmitted document, There are printer devices that output received original documents and image data compression/expansion devices.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to control the continuous transfer of a plurality of blocks of data between a memory and an input/output device without intervening control by a microprocessor. Therefore, it is possible to perform high-speed data transfer under DMA control without using a dedicated microprocessor or a high-speed microprocessor, which is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram illustrating a conventional DMA control system. In the figure, 101 is a channel data holding unit;
102 is a control means, 103 is a channel data storage means, 104 is a channel data address holding section,
105 is a chain channel data address holding section, 106 is a rewrite control means, and 200 and 300 are
DMA control device, 210 and 310 are register groups,
211, 311 are control registers, 212, 312
is a status register, 213 and 313 are address registers, 214 and 314 are transfer word count registers, 21
5 is a chain register, 216 is a channel address register, 220 is a read/write control unit, 23
0,330 is a control unit, 250,350 is a memory,
251-253, 351-354 are data blocks, 255-257 are channel data, 260,
360 is an input/output device, 261 is a modem, 263 is a network control unit NCU, 265 is a communication line, 270,
370 is a microprocessor, 280 and 380 are common buses, 291 and 391 are data transfer request signals, and 293 and 393 are interrupt signals.

Claims (1)

[Scope of Claims] 1. A direct memory access control device comprising channel data storage means 103 storing channel data for controlling data transfer between a memory and an input/output device, wherein the channel data comprises: The channel includes an instruction as to whether or not to perform continuous data transfer and the address of the channel data storage means 103 in which channel data for performing the continuous transfer is stored; a channel data holding section 101 that holds data; a channel data address holding section 104 that holds an address of the channel data storage means 103 in which channel data written in the channel data holding section 101 is stored; a chain channel data address storage unit 105 that holds the address of the channel data storage means 103 in which channel data for continuous transfer of is stored; a control means 102 that controls data transfer between the memory and the input/output device, and determines whether or not the channel data holding unit 101 is instructed to continuously transfer data;
and rewriting the channel data held in the channel data holding unit 101 to channel data read out from the channel data storage unit 103 based on the address held in the channel data address holding unit 104, and When the data transfer control based on the channel data held in the channel data holding unit 101 is completed, the control means 102 determines that the channel data holding unit 101 is instructed to continuously transfer data. In this case, the present invention is characterized by comprising a rewrite control means 106 for rewriting the address held in the channel data address holding unit 104 to the address held in the chain channel data address holding unit 105. Direct memory access control device.