JPH0563118A - Mounting system for semiconductor circuit element - Google Patents

Abstract

PURPOSE:To enable the stable high-speed operation of a semiconductor circuit element by installing the sub-ground plane structure of another member composed of an insulating layer and a conductor layer to the lead section of the semiconductor circuit element and electrically connecting the conductor layer to the ground plane of a board. CONSTITUTION:A sub-ground plane can be formed while holding insulating layers 7, 9 between the top face or underside of a lead 3 by mounting the sub- ground plane structure 6 of another member to the lead 3 of a semiconductor circuit element 2 and connecting the conductor layer 8 of the sub-ground plane structure 6 to the ground plane 5 of a printed board 1, thus forming the lead 3 in microstrip structure in a dummy manner. Each characteristic impedance of the lead 3 of the semiconductor circuit element 2 and the wiring pattern 4 of the board 1 can be matched easily by adjusting the thickness of the insulating layers 7, 9 of the sub-ground plane structure 6. Accordingly, the stable high-speed operation of the semiconductor circuit element 2 is enabled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor circuit element on a printed circuit board or the like, and more particularly to a technique capable of stably operating a semiconductor circuit element at high speed.

[0002]

Conventionally, for example SOP (Small Outline Package (S mall O utline P ackage) ), QFP
(Kuwodo flat package (Q uad F lat P ackag
A semiconductor circuit element having a package such as e)) is soldered with a lead of the semiconductor circuit element on a wiring pattern formed on a printed circuit board, as described in, for example, JP-A-63-284892. Generally, it is connected and implemented by.

[0003]

In the above prior art, even when the characteristic impedance is controlled by using a well-known microstrip line or strip line for the wiring pattern of the printed circuit board, the leads of the semiconductor circuit element and the wiring pattern of the printed circuit board. A characteristic impedance discontinuity is generated between the lead wire and the ground plane, and the lead is far from the ground plane, resulting in high lead inductance and dense lead-to-lead coupling, resulting in signal reflection, ringing, crosstalk noise, etc. Causes waveform distortion. Particularly, in a semiconductor circuit element that operates at high speed, there is a problem that such waveform distortion causes malfunction or unstable operation of the element. In recent years, the signal processing speed has increased with the increasing functionality of various electronic devices, and the need for operating semiconductor circuit elements at high speed has increased, so this problem is important.

Further, Japanese Patent Laid-Open No. 63-149540,
JP-A-2-291140 and JP-A-2-36066
Japanese Patent Laid-Open No. 2-47052 and Japanese Patent Laid-Open No. 2-47052 disclose techniques for solving the above problems. However, in these, a semiconductor circuit element having a package or the printed circuit board itself is integrally provided with a shield conductor layer, a shield cover, or a conductive electromagnetic shield layer via an insulating layer. Therefore, the characteristic impedance of the lead of the semiconductor circuit element and the characteristic impedance of the wiring pattern of the printed circuit board cannot be matched, and the printed circuit board or the semiconductor circuit is matched with the characteristic impedance of the lead of the semiconductor circuit element or the wiring pattern of the printed circuit board. It was necessary to fabricate the device.

An object of the present invention is to suppress the waveform distortion and the malfunction of the element due to the above-mentioned signal reflection, ringing, crosstalk noise, etc., and to operate the semiconductor circuit element stably at high speed. A device mounting method may be provided.

Another object of the present invention is to provide a mounting method of a semiconductor circuit element which can easily match the characteristic impedance of the leads of various semiconductor circuit elements with the characteristic impedance of the wiring pattern of the printed circuit board. Especially.

[0007]

In order to achieve the above object, the present invention provides an upper surface of a lead portion of the semiconductor circuit element,
On at least one of the lower surfaces, a sub-ground plane structure that is a separate member including at least two layers of an insulating layer and a conductor layer is provided so that the insulating layer contacts the lead portion.
Further, the conductive layer is electrically connected to the ground plane of the printed circuit board.

Further, the sub-ground plane structure is composed of at least three layers of a first insulating layer / a conductor layer / a second insulating layer, and one of the insulating layers is provided so as to be in contact with the lead. It is characterized by

Further, the invention is characterized in that the insulating layer, which is not in contact with the lead portion, is formed by oxidizing the conductor layer.

Further, the sub-ground plane structure is characterized by having a flexible structure in which the thin conductive layer is sandwiched between the film-shaped flexible first and second insulating layers.

Further, the conductive layer of the sub-ground plane structure is connected to the ground plane of the printed circuit board by soldering at four corners of the sub-ground plane structure, for example.

[0012]

In the present invention, the sub-ground plane structure, which is a separate member, is provided on the lead of the semiconductor circuit element, and the conductive layer of the sub-ground plane structure is connected to the ground plane of the printed circuit board, whereby the upper surface of the lead is improved. Alternatively, since the sub-ground plane can be formed by sandwiching the insulating layer on the lower surface, the lead has a pseudo microstrip structure. Further, by adjusting the thickness of the insulating layer of the sub-ground plane structure, the characteristic impedance of the leads of the semiconductor circuit element and the characteristic impedance of the wiring pattern of the printed circuit board can be easily matched, and the characteristic impedance The discontinuity point of can be eliminated. In addition, since the sub-ground plane is formed near the leads, the inductance of the leads is reduced, and the electric lines of force of the leads of the semiconductor circuit element do not go to other semiconductor circuit elements, so that the sub-ground plane is Since it is attracted toward the conductor layer of the structure (Fig. 3
As shown in FIG. 3A from FIG. 3B), the coupling between the leads is also weakened, and signal reflection, ringing, and crosstalk noise can be reduced. As a result, since the waveform distortion of the signal can be suppressed, malfunction of the semiconductor circuit element can be suppressed, and the semiconductor circuit element can be operated stably and at high speed. Furthermore, since the lead portion of the semiconductor circuit element is shielded by the sub-ground plane structure, it is possible to suppress the emission and mixing of electromagnetic interference waves.

[0013]

EXAMPLE 1 FIG. 1 is a perspective view showing a first example of the present invention, and FIG.
1 is a sectional view taken along the line AA ′ in FIG. 1, and FIG. 3 is a sectional view showing the effect of the present embodiment in comparison with the conventional technique.

1 is a printed circuit board, 2 is a semiconductor circuit element,
3 is a lead of the semiconductor circuit element 1, 4 (FIG. 2) is a wiring pattern of the printed board 2, 5 is a ground plane of the printed board 2, 6 is a sub-ground plane structure, and 7 is a first insulation made of polyimide or the like. Layer, 8 is a conductor layer made of copper, aluminum, silver or the like, 9 is a second insulating layer made of polyimide or the like, 10 (FIG. 1) is the conductor layer 8 of the sub-ground plane structure 6 and is the ground of the printed circuit board 1. Soldered connection portions provided at four corners of the sub-ground plane structure 6 for electrically connecting to the plane 5, t is the thickness of the first insulating layer 7, and 11 (FIG. 3) is the semiconductor circuit element 2 It is a line of electric force generated from 2 '.

The leads 3 of the semiconductor circuit element 2 are connected to the wiring pattern 4 formed on the printed board 1 by soldering. The lead 3 of the semiconductor circuit element 2 is covered with a sub-ground plane structure 6 composed of three layers of a first insulating layer 7 / a conductor layer 8 / a second insulating layer 9, and a sub-ground plane structure is formed. Since the conductive layer 8 of 6 is electrically connected to the ground plane 5 of the printed circuit board 1 by the soldering connection portion 10, the conductive layer 8 is connected to the upper side of the lead 3 via the first insulating layer 7 and the sub-ground. Since the plane is formed, the lead 3 has a pseudo microstrip structure. Further, by adjusting the thickness of the first insulating layer 7 of the sub-ground plane structure 6, the characteristic impedance of the lead 3 of the semiconductor circuit element 2 and the characteristic impedance of the wiring pattern 4 of the printed circuit board 1 can be easily adjusted. Matching can be performed, and discontinuity points of characteristic impedance can be eliminated. In addition, since the sub-ground plane is formed in the vicinity of the lead 3, the inductance of the lead 3 is reduced, and as shown in FIG. 3A, since the semiconductor circuit element 3'is attracted toward the conductor layer 8 of the sub-ground plane structure 6 as shown in FIG. 3A, the coupling between the leads is weakened and signal reflection, It is possible to reduce ringing and crosstalk noise. As a result, since the waveform distortion of the signal can be suppressed, the malfunction and unstable operation of the semiconductor circuit element can be suppressed, and the semiconductor circuit element can be operated stably and at high speed. Furthermore, since the leads 3 of the semiconductor circuit element 2 are shielded by the sub-ground plane structure 6, it goes without saying that there is an effect of suppressing the emission and mixing of electromagnetic interference waves.

Second Embodiment FIG. 4 is a sectional view similar to FIG. 2, showing a second embodiment of the present invention.

In the sub-ground plane structure 6 of this embodiment, copper, copper, etc. are formed on the first insulating layer 7 made of polyimide or the like.
A conductor layer 8 made of aluminum, silver or the like is formed, and an oxide film 9'of the conductor layer 8 is formed on the conductor layer 8 by oxidizing the surface of the conductor layer 8. The oxide film 9 ′ serves as an insulating layer (second insulating layer). It goes without saying that this embodiment also has the same effect as that of the first embodiment.

Embodiment 3 FIG. 5 is a perspective view showing a third embodiment of the present invention, and FIG.
FIG. 6 is a sectional view taken along line BB ′ of FIG. 5.

The sub-ground plane structure 6 of this embodiment has a structure in which a thin conductor layer 80 of copper, aluminum, silver or the like is sandwiched by flexible insulating films 70, 90 made of polyimide film, polyester film or the like. Is becoming That is, since the sub-ground plane structure 6 can have a flexible structure, the sub-ground plane structure 6 can be applied to semiconductor circuit elements having various shapes and structures. It goes without saying that this embodiment also has the same effects as those of the first and second embodiments.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. .. For example, in the above embodiment, as shown in FIGS. 1 and 5, the square-shaped sub-ground plane structure 6 is covered on the lead portion of the semiconductor circuit element 2 excluding the main body, but the main body is also covered. A rectangular sub-ground plane structure may be covered. When the main body is also covered, the heat dissipation effect of the semiconductor circuit element 2 may be obtained by removing the insulating layer on the main body and exposing the conductive layer. Alternatively, a cross-shaped sub-ground plane structure in which the four corners where the lead portion does not exist is removed may be used to cover only the lead portion. Further, in the above embodiment, the sub-ground plane structure 6 is covered only on the upper surface of the lead portion, but a similar sub-ground plane structure may be provided on the lower surface of the lead portion. Insulating layers 9, 9 ', 9 which do not contact the leads 3 on the conductive layers 8, 80
0 may not be provided. Furthermore, although soldering is used to connect the conductive layers 8 and 80 of the sub-ground plane structure 6 to the ground plane 5 of the printed circuit board 1 in the above-described embodiment, various types of conductive rubber, spot welding, etc. may be used. Electrical connection means can be used.

[0021]

As described above, it is possible to provide a semiconductor circuit element that operates stably and at high speed. Further, the characteristic impedance of the leads of the semiconductor circuit element and the characteristic impedance of the wiring pattern of the printed board can be easily matched.

[Brief description of drawings]

FIG. 1 is a perspective view showing a first embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ in FIG.

FIG. 3 is a cross-sectional view showing the effect of the present embodiment in comparison with the related art.

FIG. 4 is a sectional view similar to FIG. 2, showing a second embodiment of the present invention.

FIG. 5 is a perspective view showing a third embodiment of the present invention.

6 is a sectional view taken along line BB ′ of FIG.

[Explanation of symbols]

1 ... Printed circuit board, 2 ... Semiconductor circuit element, 3 ... Lead,
4 ... Wiring pattern, 5 ... Ground plane, 6 ... Sub-
Ground plane structure, 7 ... First insulating layer, 8 ... Conductor layer, 9 ... Second insulating layer, 9 '... Oxide film 10 ... Soldering connection part, t ... Thickness, 11 ... Electric force line, 70 , 80 ... Insulating film.

Claims (5)

[Claims] 1. A method of mounting a semiconductor circuit element on a printed circuit board, wherein an upper surface of a lead portion of the semiconductor circuit element,
On at least one of the lower surfaces, a sub-ground plane structure that is a separate member including at least two layers of an insulating layer and a conductor layer is provided so that the insulating layer contacts the lead portion
A method of mounting a semiconductor circuit element, wherein the conductive layer is electrically connected to a ground plane of the printed board. 2. The sub-ground plane structure comprises at least three layers of a first insulating layer / a conductor layer / a second insulating layer, and one of the insulating layers is provided so as to be in contact with the lead. A method of mounting a semiconductor circuit element, which is characterized in that 3. The mounting method for a semiconductor circuit element according to claim 2, wherein the insulating layer which is not in contact with the lead portion is formed by oxidizing the conductor layer. 4. The sub-ground plane structure has a flexible structure in which the thin conductive layer is sandwiched between the film-shaped flexible first and second insulating layers. 2. The mounting method of the semiconductor circuit element according to 2. 5. The sub-ground plane structure, wherein the conductive layer is electrically connected to the ground plane of the printed circuit board by soldering.
2. A mounting method of a semiconductor circuit element according to 2, 3 or 4.