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JPH0563955B2 - - Google Patents

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Publication number
JPH0563955B2
JPH0563955B2 JP59146035A JP14603584A JPH0563955B2 JP H0563955 B2 JPH0563955 B2 JP H0563955B2 JP 59146035 A JP59146035 A JP 59146035A JP 14603584 A JP14603584 A JP 14603584A JP H0563955 B2 JPH0563955 B2 JP H0563955B2
Authority
JP
Japan
Prior art keywords
thin film
film layer
wiring board
thickness
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59146035A
Other languages
Japanese (ja)
Other versions
JPS6126282A (en
Inventor
Koji Kanehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP14603584A priority Critical patent/JPS6126282A/en
Priority to FR858510660A priority patent/FR2567709B1/en
Publication of JPS6126282A publication Critical patent/JPS6126282A/en
Priority to FR8615585A priority patent/FR2590105A1/en
Priority to US07/115,565 priority patent/US4840924A/en
Publication of JPH0563955B2 publication Critical patent/JPH0563955B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は多層配線基板の構造、とくに設計変更
電極の構造に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to the structure of a multilayer wiring board, and particularly to the structure of a redesigned electrode.

〔従来技術〕[Prior art]

従来、多層配線基板において設計変更が発生し
た場合の接続変更の方法として、例えば、A.J.
Blodgett,D.R.Barbour,Thermal Conduction
Module:A High−Performance Multilayer
Ceramic Package,IBM J.RES.DEVELOP.26
30〜36(1982)に示されるように、多層配線基板
の最上層に、設計変更電極として、内層の導電層
からチツプへつながる導体配線と、設計変更時に
ワイヤーの接続に使用する接続部分とを形成し、
設計変更が必要な時に表面の導体配線を切断し、
内層導電層とチツプとを切離し、接続部分にボン
デイングでワイヤーを接続するというものがあ
る。しかしこの方法では切断用導体配線とワイヤ
ー接続部分とが同一工程で形成されるため、切断
部分も接続部分と同じ構造で形成される。上記文
献に記載された多層基板における設計変更電極
は、第1図に示されるように、2つの接続部分1
1と1つの切断部分12よりなり、各部分の導体
材料も導体厚も同じであり構造上の差異はない。
しかし本来、接続部と切断部はその目的・機能が
異なつている。すなわち、接続部は設計変更用の
布線やICリードが接続される部分であり、はん
だ付けや熱圧着、超音波圧着などに対してすぐれ
た特性を有する必要がある。一方切断部は、通常
は高信頼度な導体であるとともに必要時には容易
に切断できるものでなければならない。このよう
に異なる機能を有する接続部と切断部を同一の構
造で形成していては、それぞれの必要とする特性
を十分に得ることができないという問題点があつ
た。
Conventionally, when a design change occurs in a multilayer wiring board, the connection change method is, for example, AJ.
Blodgett, DRBarbour, Thermal Conduction
Module:A High-Performance Multilayer
Ceramic Package, IBM J.RES.DEVELOP. 26 ,
30-36 (1982), on the top layer of a multilayer wiring board, conductor wiring connecting from the conductive layer in the inner layer to the chip as a design change electrode, and a connection part used for connecting wires at the time of design change are installed. form,
When design changes are necessary, cut the surface conductor wiring,
There is a method in which the inner conductive layer and the chip are separated and a wire is connected to the connection part by bonding. However, in this method, the cutting conductor wiring and the wire connection part are formed in the same process, so the cutting part is also formed with the same structure as the connection part. The redesigned electrode in the multilayer board described in the above document has two connection parts 1 as shown in FIG.
1 and one cut portion 12, the conductor material and conductor thickness of each portion are the same, and there is no structural difference.
However, originally, the purpose and function of the connection part and the disconnection part are different. That is, the connection part is a part to which wiring and IC leads for design changes are connected, and must have excellent properties for soldering, thermocompression bonding, ultrasonic compression bonding, etc. On the other hand, the cutting part must normally be a highly reliable conductor and must be able to be easily cut when necessary. If the connecting portion and the cutting portion having different functions are formed in the same structure as described above, there is a problem in that the characteristics required by each cannot be sufficiently obtained.

〔発明の概要〕[Summary of the invention]

本発明はこのような点に鑑みてなされたもので
あり、その目的とするところは、接続性、切断性
に対してすぐれた特性を持つ設計変更電極を有す
る多層配線基板を提供することにある。
The present invention has been made in view of these points, and its purpose is to provide a multilayer wiring board having redesigned electrodes that have excellent characteristics in terms of connectivity and disconnectability. .

このような目的を達成するために本発明は、設
計変更電極の切断部と接続部とを異なる導体層構
成にしたものである。
In order to achieve such an object, the present invention provides a cutting section and a connecting section of a redesigned electrode with different conductor layer configurations.

〔実施例〕〔Example〕

本発明を実施例に基づき詳細に説明する。第2
図に本発明に係わる多層配線基板の一実施例を示
す。
The present invention will be explained in detail based on examples. Second
The figure shows an embodiment of a multilayer wiring board according to the present invention.

第2図において、21は接続部、22は切断部
である。以下導体材料の構成について述べる。接
続部21は基板上(図示されていない)のクロ
ム、パラジウムの薄膜層の上に銅メツキがされて
いる。クロムの厚さは500〜1000Å、パラジウム
の厚さは300〜3000Åの範囲である。銅メツキの
厚みは3〜20μmの範囲である。場合によつては
銅メツキ上に、1〜5μm厚のニツケルメツキと
0.5〜2μm厚の金メツキとが形成され、あるいは
0.5〜4μm厚のパラジウムメツキが形成される。
これらのメタル材料は、ワイヤーを接続する方
法、すなわちはんだ付け、熱圧着、超音波接続な
どの種々の方法に応じて選択される。また薄膜層
の材料として上記クロムの代わりにチタン、タン
グステン、ニクロム、アルミニウム、タンタル等
の金属を用いてもよい。また上記パラジウムの代
わりに白金、ニツケル、銅等の金属を用いてもよ
い。切断部22は基板上(図示されていない)の
クロム、パラジウム、銅の薄膜層の上にニツケル
メツキと金メツキがほどこされている。クロムの
厚さは500〜1000Å、パラジウムの厚さは300〜
3000Å、銅の厚さは1000〜5000Åの範囲である。
ニツケルメツキと金メツキの両方の厚さの合計が
4μm以下であることが切断のために好ましい。切
断はレーザや超音波カツタ、ダイヤモンドカツ
タ、超硬ナイフ等で行なわれる。
In FIG. 2, 21 is a connecting portion and 22 is a cutting portion. The structure of the conductor material will be described below. The connection portion 21 is formed by copper plating on a thin film layer of chromium and palladium on a substrate (not shown). The thickness of chromium ranges from 500 to 1000 Å, and the thickness of palladium ranges from 300 to 3000 Å. The thickness of the copper plating ranges from 3 to 20 μm. In some cases, nickel plating with a thickness of 1 to 5 μm is applied on the copper plating.
Gold plating with a thickness of 0.5 to 2 μm is formed, or
A palladium plating with a thickness of 0.5-4 μm is formed.
These metal materials are selected depending on the method of connecting the wires, ie, various methods such as soldering, thermocompression bonding, ultrasonic bonding, etc. Further, as a material for the thin film layer, metals such as titanium, tungsten, nichrome, aluminum, tantalum, etc. may be used instead of the above-mentioned chromium. Moreover, metals such as platinum, nickel, copper, etc. may be used instead of the above-mentioned palladium. The cutting portion 22 is formed by nickel plating and gold plating on thin film layers of chromium, palladium, and copper on a substrate (not shown). Chromium thickness is 500~1000Å, palladium thickness is 300~
3000 Å, copper thickness ranges from 1000 to 5000 Å.
The total thickness of both nickel plating and gold plating is
A diameter of 4 μm or less is preferred for cutting. Cutting is performed using a laser, an ultrasonic cutter, a diamond cutter, a carbide knife, or the like.

この設計変更電極の製造方法の一例は次の通り
である。絶縁層の上にクロム、パラジウム、銅の
多層薄膜導体層を、例えば、スパツタリングや蒸
着などで形成する。この層構成は、絶縁層と後の
工程で形成される配線層との密着性等を考慮して
適宜決められる。次にフオトレジストをこの薄膜
導体層上に塗布し、露光、現像の工程を経て切断
部を含むパターンを形成する。次にニツケルおよ
び金の多層メツキ工程により切断部を含む配線層
を形成する。ここでニツケルおよび金の層構成と
したのは、金が赤外線レーザ光で容易に切断でき
るからであり、また下層のニツケルは、下地の薄
膜銅と金との密着を得るため、およびハンダ付け
部分から金錫ハンダが切断部のパターンにまで流
れこんできた場合に配線層の金が金錫ハンダなど
に食われて断線してしまわないため必要である。
この層の構成は、切断に用いる高エネルギー放射
線等の性質や切断方法を考慮して適宜決められ
る。次にフオトレジストを剥離し、再度フオトレ
ジストを塗布し、露光、現像の工程を経て接続部
を有するパターンを形成し、メツキ工程により接
続部を有する配線層を形成する。この配線層に用
いる金属は接続方法によつて決められ、たとえ
ば、金錫ハンダによつて接続を行なう場合は銅、
パラジウムなどを用いる。次にフオトレジストを
剥離し、エツチング工程により配線層以外の薄膜
導体層を取り除く。これで、切断部を接続部と異
なる導体層構成にして切断しやすくした配線基板
が形成される。
An example of a method for manufacturing this redesigned electrode is as follows. A multilayer thin film conductor layer of chromium, palladium, and copper is formed on the insulating layer by, for example, sputtering or vapor deposition. This layer structure is appropriately determined in consideration of the adhesion between the insulating layer and the wiring layer to be formed in a later step. Next, a photoresist is applied onto this thin film conductor layer, and a pattern including cut portions is formed through exposure and development steps. Next, a wiring layer including the cut portions is formed by a multilayer plating process of nickel and gold. The reason for the layer structure of nickel and gold here is that gold can be easily cut with infrared laser light, and the lower layer of nickel is used to ensure close contact between the underlying thin film copper and gold, and for soldering areas. This is necessary to prevent the gold in the wiring layer from being eaten away by the gold-tin solder and disconnection if the gold-tin solder flows into the cut pattern.
The structure of this layer is appropriately determined in consideration of the properties of the high-energy radiation used for cutting and the cutting method. Next, the photoresist is peeled off, photoresist is applied again, and a pattern having a connection portion is formed through exposure and development steps, and a wiring layer having a connection portion is formed through a plating step. The metal used for this wiring layer is determined by the connection method; for example, if the connection is made by gold-tin solder, copper,
Use palladium, etc. Next, the photoresist is peeled off and the thin film conductor layer other than the wiring layer is removed by an etching process. In this way, a wiring board is formed in which the cutting portion has a conductor layer structure different from that of the connecting portion, making it easier to cut.

本発明の第2の実施例として、切断部をニツケ
ル、金のメツキで、接続部を銅のメツキで形成し
た基板の例を第3図に示す。第3図において、3
0は内層および表面層に導体回路が形成されたセ
ラミツク多層基板、31は接続部、32は切断
部、33はチタン薄膜層、34はパラジウム薄膜
層、35は銅薄膜層、36は銅メツキ、37はニ
ツケルメツキ、38は金メツキ、39は設計変更
電極と内層信号配線部もしくはICチツプリード
端子接続部とをつなぐビアホールおよび配線であ
る。チタン薄膜層33、パラジウム薄膜層34、
銅薄膜層35のそれぞれの厚さは500Å〜3000Å
の範囲にある。接続部31は主に厚さ10μm程度
の銅メツキ36で形成されている。切断部32は
ニツケルメツキ37と金メツキ38の2層メツキ
で形成されていて、厚さは、それぞれ1μmと2μm
である。
As a second embodiment of the present invention, FIG. 3 shows an example of a substrate in which the cut portions are plated with nickel and gold, and the connection portions are plated with copper. In Figure 3, 3
0 is a ceramic multilayer substrate with conductor circuits formed on the inner layer and surface layer, 31 is a connecting portion, 32 is a cutting portion, 33 is a titanium thin film layer, 34 is a palladium thin film layer, 35 is a copper thin film layer, 36 is copper plating, 37 is nickel plating, 38 is gold plating, and 39 is a via hole and wiring connecting the design-changed electrode and the inner layer signal wiring section or the IC chip lead terminal connection section. titanium thin film layer 33, palladium thin film layer 34,
The thickness of each copper thin film layer 35 is 500 Å to 3000 Å.
within the range of The connecting portion 31 is mainly formed of copper plating 36 with a thickness of about 10 μm. The cutting part 32 is formed of two layers of nickel plating 37 and gold plating 38, and the thickness is 1 μm and 2 μm, respectively.
It is.

第4図に本発明の第3の実施例を示す。41は
接続部、42は切断部である。接続部41、切断
部42ともに基板上(図示されていない)のニク
ロム薄膜層の上にニツケル薄膜層が形成され、そ
の上に金メツキがほどこされている。ニクロム薄
膜層の厚さは500〜2000Å、ニツケル薄膜層の厚
さは1000〜3000Åである。金メツキの厚さは、接
続部41で5〜10μm、切断部42で1.5〜3μmと
なつており、両者の厚さは異なる。これは、接続
部41は信頼性の高い接続を得るために5μm以上
の厚さが望ましいのに対し、切断部42は切断の
しやすさから3μm以下が好ましいためである。
FIG. 4 shows a third embodiment of the invention. 41 is a connecting portion, and 42 is a cutting portion. For both the connecting portion 41 and the cutting portion 42, a nickel thin film layer is formed on a nichrome thin film layer on a substrate (not shown), and gold plating is applied thereon. The thickness of the nichrome thin film layer is 500-2000 Å, and the thickness of the nickel thin film layer is 1000-3000 Å. The thickness of the gold plating is 5 to 10 μm at the connecting portion 41 and 1.5 to 3 μm at the cutting portion 42, and the thicknesses of the two are different. This is because the thickness of the connecting portion 41 is preferably 5 μm or more in order to obtain a highly reliable connection, whereas the thickness of the cutting portion 42 is preferably 3 μm or less for ease of cutting.

〔発明の効果〕〔Effect of the invention〕

以上述べたように本発明は、設計変更電極の切
断部と接続部とを異なる導体材料あるいは導体厚
の導体層構成としたので、接続性、切断性に対し
てすぐれた特性を持つ設計変更電極を形成できる
という効果がある。
As described above, in the present invention, the cutting part and the connecting part of the redesigned electrode are made of conductor layers having different conductor materials or conductor thicknesses, so the redesigned electrode has excellent characteristics in terms of connectivity and disconnectability. It has the effect of being able to form.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の多層配線基板を示す斜視図、第
2図は本発明に係わる多層配線基板の一実施例を
示す斜視図、第3図はその第2の実施例を示す縦
断面図、第4図はその第3の実施例を示す斜視図
である。 21,31,41……接続部、22,32,4
2……切断部、33……チタン薄膜層、34……
パラジウム薄膜層、35……銅薄膜層、36……
銅メツキ、37……ニツケルメツキ、38……金
メツキ、39……ビアホールおよび配線。
FIG. 1 is a perspective view showing a conventional multilayer wiring board, FIG. 2 is a perspective view showing an embodiment of the multilayer wiring board according to the present invention, and FIG. 3 is a longitudinal sectional view showing the second embodiment. FIG. 4 is a perspective view showing the third embodiment. 21, 31, 41... Connection part, 22, 32, 4
2...Cut portion, 33...Titanium thin film layer, 34...
Palladium thin film layer, 35... Copper thin film layer, 36...
Copper plating, 37...nickel plating, 38...gold plating, 39...via hole and wiring.

Claims (1)

【特許請求の範囲】 1 接続部と切断部とから構成された設計変更電
極を有する多層配線基板において、 前記接続部は、前記基板上に形成した金属薄膜
層上に形成され、設計変更用の布線あるいはIC
のリードまたはバンプと良好に接続可能な性質を
有する少なくとも1つの金属メツキから成り、 前記切断部は、前記基板上に形成した金属薄膜
層上に形成され、通常使用時に高い接続信頼性を
有するとともに設計変更時に容易に切断可能な性
質を有し、前記金属メツキと異なる導体材料の複
数層の金属メツキから成ることを特徴とする多層
配線基板。 2 接続部と切断部とから構成された設計変更電
極を有する多層配線基板において、 前記接続部は、前記基板上に形成した金属薄膜
層上に、設計変更用の布線あるいはICのリード
またはバンプと良好に接続可能な性質を有し、か
つ5μm以上の厚さで形成された金属メツキから成
り、 前記切断部は、前記基板上に形成した金属薄膜
層上に、通常使用時に高い接続信頼性を有すると
ともに設計変更時に容易に切断可能な性質を有
し、かつ4μm以下の厚さで形成された前記金属メ
ツキと同じ導体材料の金属メツキから成ることを
特徴とする多層配線基板。
[Scope of Claims] 1. A multilayer wiring board having a design change electrode composed of a connection part and a cutting part, wherein the connection part is formed on a metal thin film layer formed on the substrate, and the connection part is formed on a metal thin film layer formed on the substrate, Wiring or IC
The cutting portion is formed on the metal thin film layer formed on the substrate and has high connection reliability during normal use. What is claimed is: 1. A multilayer wiring board, characterized in that the multilayer wiring board has a property that can be easily cut when changing the design, and is made of a plurality of layers of metal plating made of a conductive material different from the metal plating. 2. In a multilayer wiring board having a design change electrode composed of a connection part and a cutting part, the connection part is a wiring for design change or an IC lead or bump on a metal thin film layer formed on the substrate. The cutting portion is formed of a metal plating formed with a thickness of 5 μm or more and has properties that allow good connection with What is claimed is: 1. A multilayer wiring board comprising a metal plating made of the same conductive material as the metal plating and having a property of being easily cut when changing the design and having a thickness of 4 μm or less.
JP14603584A 1984-07-11 1984-07-16 Multilayer cirucit board Granted JPS6126282A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP14603584A JPS6126282A (en) 1984-07-16 1984-07-16 Multilayer cirucit board
FR858510660A FR2567709B1 (en) 1984-07-11 1985-07-11 GLITTER ASSEMBLY INCLUDING A MULTI-LAYER WIRING SUBSTRATE
FR8615585A FR2590105A1 (en) 1984-07-11 1986-11-07 GLITTER ASSEMBLY COMPRISING A MULTILAYER WIRING SUBSTRATE
US07/115,565 US4840924A (en) 1984-07-11 1987-10-29 Method of fabricating a multichip package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14603584A JPS6126282A (en) 1984-07-16 1984-07-16 Multilayer cirucit board

Publications (2)

Publication Number Publication Date
JPS6126282A JPS6126282A (en) 1986-02-05
JPH0563955B2 true JPH0563955B2 (en) 1993-09-13

Family

ID=15398632

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14603584A Granted JPS6126282A (en) 1984-07-11 1984-07-16 Multilayer cirucit board

Country Status (1)

Country Link
JP (1) JPS6126282A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62239596A (en) * 1986-04-11 1987-10-20 株式会社日立製作所 Wiring board
JP2552159B2 (en) * 1987-02-02 1996-11-06 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof
JP4890983B2 (en) * 2006-07-18 2012-03-07 矢崎総業株式会社 Connector and connector unit
JP5439900B2 (en) * 2009-03-30 2014-03-12 株式会社村田製作所 Land structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5427956A (en) * 1977-08-01 1979-03-02 Nippon Electric Co Method of making thick film integrated circuit
JPS5759473B2 (en) * 1973-07-25 1982-12-15 Bosch Gmbh Robert

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS593588Y2 (en) * 1980-01-10 1984-01-31 株式会社精工舎 circuit board
JPS5930551Y2 (en) * 1980-09-26 1984-08-31 株式会社日立製作所 Wiring board with lines for wiring repair

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5759473B2 (en) * 1973-07-25 1982-12-15 Bosch Gmbh Robert
JPS5427956A (en) * 1977-08-01 1979-03-02 Nippon Electric Co Method of making thick film integrated circuit

Also Published As

Publication number Publication date
JPS6126282A (en) 1986-02-05

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