JPH0560250B2 - - Google Patents
Info
- Publication number
- JPH0560250B2 JPH0560250B2 JP26881384A JP26881384A JPH0560250B2 JP H0560250 B2 JPH0560250 B2 JP H0560250B2 JP 26881384 A JP26881384 A JP 26881384A JP 26881384 A JP26881384 A JP 26881384A JP H0560250 B2 JPH0560250 B2 JP H0560250B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- polished
- wafer
- bonding
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 235000012431 wafers Nutrition 0.000 claims description 60
- 239000004065 semiconductor Substances 0.000 claims description 44
- 238000000034 method Methods 0.000 claims description 18
- 238000005452 bending Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、シリコンなどの半導体ウエーハ同士
を直接接着させる方法およびその方法に使用する
治具に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for directly bonding semiconductor wafers such as silicon to each other, and a jig used in the method.
鏡面研磨されたシリコンなどの二枚の半導体ウ
エーハを、その研磨面同士を清浄な条件下で接触
させると強固な接合体ウエーハが得られる。この
方法は、ウエーハ間に接着材等の異種物質を介在
させる必要がないため、その後の高温処理や各種
化学処理が自由にでき、またpn接合や誘電体埋
め込みも簡便にできる、といつた利点を有する。
When two mirror-polished semiconductor wafers such as silicon are brought into contact with their polished surfaces under clean conditions, a strong bonded wafer can be obtained. This method does not require dissimilar materials such as adhesives to be interposed between the wafers, so subsequent high-temperature treatments and various chemical treatments can be carried out freely, and the advantages include that p-n junctions and dielectric embedding can be easily performed. has.
ところでこの方法で半導体ウエーハを接着させ
る場合、ウエーハの反り等のため周辺部が先に接
着し、接合部に気泡が取り残されることがしばし
ばある。この対策として、真空中で接着すること
が考えられる。しかしこれでは、装置が大掛りな
ものとなる。 However, when semiconductor wafers are bonded using this method, the peripheral portion is often bonded first due to warpage of the wafer, and air bubbles are often left behind at the bonded portion. As a countermeasure to this problem, bonding in a vacuum may be considered. However, this requires a large-scale device.
本発明は、半導体ウエーハ同士を内部に気泡を
残すことなく簡便に接着する方法およびその方法
に使用する治具を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for simply bonding semiconductor wafers together without leaving any air bubbles inside, and a jig for use in the method.
本発明の方法は、鏡面研磨された二枚の半導体
ウエーハの研磨面同士を接着させるに当たつて、
少なくとも一方の半導体ウエーハをその研磨面中
央部が凸型となるようにたわませた状態でその凸
型面を他方の半導体ウエーハに接触させて、両ウ
エーハの接着を行なうことを特徴とする。
In the method of the present invention, when bonding the polished surfaces of two mirror-polished semiconductor wafers together,
The method is characterized in that at least one semiconductor wafer is bent so that the central portion of its polished surface is convex, and the convex surface is brought into contact with the other semiconductor wafer to bond both wafers together.
本発明の治具は、上記のように一方に半導体研
磨面中央部を凸型にたわませて保持するためのも
のであり、表面中央部が凸型となるようにテーパ
面または曲面成型されその表面に開口する排気孔
を有する基台と、この基台に重ねられ、半導体ウ
エーハが載置される面の外周部に溝が形成されか
つその溝に沿つて前記基台の排気孔と連通する複
数個の排気孔が形成された弾性体からなるチヤツ
クを備える。そしてチヤツク上に載せられた半導
体ウエーハを、チヤツクの排気孔および基台の排
気孔を介して真空吸引することにより、チヤツク
と共に半導体ウエーハを基台の表面形状を反映し
て中央部が凸型となる状態で保持するようにした
ものである。 As described above, the jig of the present invention is for holding the central part of the semiconductor polishing surface in a convex shape on one side, and is formed into a tapered or curved surface so that the central part of the surface is convex. A base having an exhaust hole opening on its surface, and a groove formed on the outer periphery of the surface on which the semiconductor wafer is placed and placed over the base, and communicating with the exhaust hole of the base along the groove. The chuck is made of an elastic body and has a plurality of exhaust holes formed therein. Then, by vacuum suctioning the semiconductor wafer placed on the chuck through the chuck's exhaust hole and the base's exhaust hole, the semiconductor wafer and the chuck are shaped into a convex center reflecting the surface shape of the base. It is designed to be maintained in a certain state.
本発明の方法および治具を用いれば、二枚の半
導体ウエーハ同士を内部に気泡が残らないように
接着して強固な接合体ウエーハを得ることができ
る。しかも真空中での接着と異なり、大掛りな装
置を要せず、極めて簡便に接着を行なうことがで
きる。
By using the method and jig of the present invention, a strong bonded wafer can be obtained by bonding two semiconductor wafers together without leaving any air bubbles inside. Moreover, unlike bonding in a vacuum, the bonding can be performed extremely easily without requiring any large-scale equipment.
以下本発明の実施例を説明する。 Examples of the present invention will be described below.
第１図ａ〜ｃは一実施例の方法を説明するため
の図である。これらの図において、１１，１２は
接着すべき二枚の半導体ウエーハであり、それぞ
れの接着すべき面は鏡面研磨されている。１３は
一方の半導体ウエーハ１１を保持する治具であ
り、１４は他方の半導体ウエーハ１２を平坦に支
持する支持台である。第１図ａに示すように、治
具１３はその表面が中央部が凸型となるように曲
面加工されており、半導体ウエーハ１１はこの治
具１３により研磨面が中央部凸型となるように保
持される。このように保持された半導体ウエーハ
１１を、第１図ｂに示すように他方の半導体ウエ
ーハ１２に凸型の中央部から接触させ、治具１３
による半導体ウエーハ１１の保持を解除すること
により、第１図ｃに示すように、半導体ウエーハ
１１，１２を接着させる。 FIGS. 1a to 1c are diagrams for explaining the method of one embodiment. In these figures, 11 and 12 are two semiconductor wafers to be bonded, and the surfaces to be bonded are mirror-polished. 13 is a jig that holds one semiconductor wafer 11, and 14 is a support stand that flatly supports the other semiconductor wafer 12. As shown in FIG. 1a, the surface of the jig 13 is curved so that the central part is convex, and the semiconductor wafer 11 is polished by this jig 13 so that the central part is convex. is maintained. The semiconductor wafer 11 held in this way is brought into contact with the other semiconductor wafer 12 from the center of the convex shape as shown in FIG.
By releasing the holding of the semiconductor wafer 11 by the semiconductor wafers 11 and 12, the semiconductor wafers 11 and 12 are bonded together as shown in FIG. 1c.
この方法によれば、二枚の半導体ウエーハ１
１，１２を残留ガスなしに全面確実に接着させ
て、強固な接合体ウエーハを得ることができる。 According to this method, two semiconductor wafers 1
1 and 12 can be reliably bonded over the entire surface without residual gas, and a strong bonded wafer can be obtained.
第２図ａ，ｂは、第１図で示したウエーハ保持
治具１３の具体的な構成例を示す。ａは平面図で
あり、ｂはそのＡ−A′断面図である。２４は金
属等でつくつた基台であり、表面中央部が凸型と
なるように曲面加工されており、表面に開口する
排気孔２５が形成されている。２１は基台２４上
に被せられる、半導体ウエーハを載置するための
ラバー・チヤツクである。このラバー・チヤツク
２１の表面にはその外周部に半導体ウエーハを保
持するための溝２２が形成され、この溝２２に沿
つて複数の排気孔２３が形成されている。基台２
４の下に排気管２６が設けられており、この排気
管２６を介してラバー・チヤツク２１上に載置さ
れた半導体ウエーハを真空吸引するようになつて
いる。 FIGS. 2a and 2b show a specific example of the structure of the wafer holding jig 13 shown in FIG. A is a plan view, and b is a sectional view taken along line A-A'. Reference numeral 24 denotes a base made of metal or the like, the surface of which is curved so as to have a convex central portion, and has an exhaust hole 25 opening in the surface. A rubber chuck 21 is placed on the base 24 and is used to place a semiconductor wafer. A groove 22 for holding a semiconductor wafer is formed on the outer periphery of the surface of the rubber chuck 21, and a plurality of exhaust holes 23 are formed along the groove 22. Base 2
An exhaust pipe 26 is provided below the rubber chuck 21, and the semiconductor wafer placed on the rubber chuck 21 is vacuum-suctioned through the exhaust pipe 26.
第３図はこの治具１３を用いて半導体ウエーハ
１１を保持した様子を示している。図示のよう
に、排気管２６を介して真空吸引することによ
り、排気孔２５，２３を介して半導体ウエーハ１
１の外周部が引張られてラバー・チヤツク２１が
基台２４の表面形状に従つてたわみ、この結果半
導体ウエーハ１１は中央部が凸型いなつた状態で
保持される。 FIG. 3 shows how the semiconductor wafer 11 is held using this jig 13. As shown in the figure, by vacuum suctioning through the exhaust pipe 26, the semiconductor wafer 1 is transferred through the exhaust holes 25 and 23.
The outer periphery of the semiconductor wafer 11 is stretched, causing the rubber chuck 21 to bend in accordance with the surface shape of the base 24, and as a result, the semiconductor wafer 11 is held in a convex, flattened state at the center.
このようにして保持した半導体ウエーハ１１
を、第１図で説明したようにもう一方の半導体ウ
エーハ１２に接触させ、ラバー・チヤツク２１内
に空気等を少しずつ導入して半導体ウエーハ１１
のたわみを徐々に回復させる。これにより、接着
面は中央部から周辺部に向かつて広がり、気泡を
取り込むことなくウエーハ１１，１２を接着する
ことができる。 Semiconductor wafer 11 held in this way
is brought into contact with the other semiconductor wafer 12 as explained in FIG.
Gradually restore the deflection. As a result, the bonding surface spreads from the center toward the periphery, and the wafers 11 and 12 can be bonded together without introducing air bubbles.
本発明は上記実施例に限られない。例えば第１
図の方法では、半導体ウエーハ１２は平坦に支持
したが、これも半導体ウエーハ１１と同様に中央
部が凸型となるようにたわませて保持してもよ
い。また第１図において、支持台１４をゴムなど
の弾性体とし、ｂの状態から治具１３を押しつけ
る荷重を増すことにより両ウエーハ１１，１２の
接触面積を徐々に増していく、という方法をとつ
てもよい。さらに本発明の方法において、半導体
ウエーハをたわませるには、例えばウエーハの周
辺を機械的に保持し中央部を押すことによつても
可能である。 The present invention is not limited to the above embodiments. For example, the first
In the illustrated method, the semiconductor wafer 12 is supported flatly, but like the semiconductor wafer 11, it may also be held in a bent manner so that the central portion is convex. In addition, in FIG. 1, a method is used in which the support base 14 is made of an elastic body such as rubber, and the contact area between both wafers 11 and 12 is gradually increased by increasing the load pressing the jig 13 from state b. It's good to wear. Further, in the method of the present invention, the semiconductor wafer can be bent by, for example, mechanically holding the wafer around the wafer and pushing the central part.
また第２図のウエーハ保持治具において、ラバ
ー・チヤツク２１は他の弾性材料を用いて構成す
ることができる。また基台２４の表面は必ずしも
曲面でなくてもよく、例えば中央部が凸型となる
テーパ面であつてもよい。 Furthermore, in the wafer holding jig shown in FIG. 2, the rubber chuck 21 can be constructed using other elastic materials. Further, the surface of the base 24 does not necessarily have to be a curved surface, and may be a tapered surface with a convex central portion, for example.
第１図ａ〜ｃは本発明の一実施例の方法を説明
するための図、第２図ａ，ｂはその方法に使用し
たウエーハ保持治具を示す図、第３図はこの保持
治具によりウエーハを保持した様子を示す図であ
る。
１１，１２……半導体ウエーハ、１３……ウエ
ーハ保持治具、１４……ウエーハ支持台、２１…
…ラバー・チヤツク、２２……溝、２３……排気
孔、２４……基台、２５……排気孔、２６……排
気管。
Figures 1 a to c are diagrams for explaining a method according to an embodiment of the present invention, Figures 2 a and b are diagrams showing a wafer holding jig used in the method, and Figure 3 is a diagram showing this holding jig. FIG. 11, 12...Semiconductor wafer, 13...Wafer holding jig, 14...Wafer support stand, 21...
...Rubber chuck, 22...Groove, 23...Exhaust hole, 24...Base, 25...Exhaust hole, 26...Exhaust pipe.
Claims (1)
面同士を清浄な条件下で直接接着させて接合体ウ
エーハを得る方法において、少なくとも一方の半
導体ウエーハの研磨面を、中央部が凸型となるよ
うにたわませて他方の半導体ウエーハの研磨面に
接触させて接着を行なうことを特徴とする半導体
ウエーハの接着方法。 ２ 鏡面研磨された二枚の半導体ウエーハの研磨
面同士を清浄な条件下で直接接着させて接合体ウ
エーハを得るための治具であつて、表面中央部が
凸型となるようにテーパ面または曲面成型され、
その表面に開口する排気孔を有する基台と、この
基台に重ねられ、半導体ウエーハが載置される面
の外周部に溝が形成されかつその溝に沿つて前記
基台の排気孔と連通する複数個の排気孔が形成さ
れた弾性体からなるチヤツクとを備え、前記チヤ
ツク上に載せられた半導体ウエーハを、チヤツク
の排気孔および基台の排気孔を介して真空吸引し
てその中央部が凸型となる状態で保持するように
したことを特徴とする半導体ウエーハの接着治
具。[Claims] 1. In a method for obtaining a bonded wafer by directly bonding the polished surfaces of two mirror-polished semiconductor wafers to each other under clean conditions, the polished surface of at least one semiconductor wafer is 1. A method for bonding semiconductor wafers, characterized in that bonding is performed by bending the semiconductor wafer into a convex shape and bringing it into contact with the polished surface of the other semiconductor wafer. 2 A jig for obtaining a bonded wafer by directly bonding the polished surfaces of two mirror-polished semiconductor wafers together under clean conditions, with a tapered surface or Curved surface molded,
A base having an exhaust hole opening on its surface, and a groove formed on the outer periphery of the surface on which the semiconductor wafer is placed and placed over the base, and communicating with the exhaust hole of the base along the groove. a chuck made of an elastic body with a plurality of exhaust holes formed therein; A semiconductor wafer bonding jig, characterized in that the semiconductor wafer is held in a convex state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26881384A JPS61145839A (en) | 1984-12-20 | 1984-12-20 | Semiconductor wafer bonding method and bonding jig |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26881384A JPS61145839A (en) | 1984-12-20 | 1984-12-20 | Semiconductor wafer bonding method and bonding jig |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61145839A JPS61145839A (en) | 1986-07-03 |
| JPH0560250B2 true JPH0560250B2 (en) | 1993-09-01 |
Family
ID=17463609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26881384A Granted JPS61145839A (en) | 1984-12-20 | 1984-12-20 | Semiconductor wafer bonding method and bonding jig |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61145839A (en) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6271215A (en) * | 1985-09-25 | 1987-04-01 | Toshiba Corp | Wafer jointing apparatus |
| JP2642645B2 (en) * | 1987-11-19 | 1997-08-20 | 株式会社日立製作所 | Method of manufacturing semiconductor substrate and method of manufacturing semiconductor device |
| JP2589994B2 (en) * | 1987-12-24 | 1997-03-12 | 富士通株式会社 | Wafer bonding method |
| US4837177A (en) * | 1987-12-28 | 1989-06-06 | Motorola Inc. | Method of making bipolar semiconductor device having a conductive recombination layer |
| US6635941B2 (en) * | 2001-03-21 | 2003-10-21 | Canon Kabushiki Kaisha | Structure of semiconductor device with improved reliability |
| TWI283906B (en) * | 2001-12-21 | 2007-07-11 | Esec Trading Sa | Pick-up tool for mounting semiconductor chips |
| US7192841B2 (en) | 2002-04-30 | 2007-03-20 | Agency For Science, Technology And Research | Method of wafer/substrate bonding |
| US7361593B2 (en) | 2002-12-17 | 2008-04-22 | Finisar Corporation | Methods of forming vias in multilayer substrates |
| US7259466B2 (en) | 2002-12-17 | 2007-08-21 | Finisar Corporation | Low temperature bonding of multilayer substrates |
| FR2860178B1 (en) * | 2003-09-30 | 2005-11-04 | Commissariat Energie Atomique | METHOD OF SEPARATING GLUE PLATES BETWEEN THEM TO CONSTITUTE A STACKED STRUCTURE. |
| US7650688B2 (en) | 2003-12-31 | 2010-01-26 | Chippac, Inc. | Bonding tool for mounting semiconductor chips |
| US7153759B2 (en) | 2004-04-20 | 2006-12-26 | Agency For Science Technology And Research | Method of fabricating microelectromechanical system structures |
| EP2053635A4 (en) * | 2006-06-29 | 2010-09-22 | Nikon Corp | Wafer bonding apparatus |
| KR20100108418A (en) * | 2008-11-14 | 2010-10-06 | 도쿄엘렉트론가부시키가이샤 | Bonding apparatus and bonding method |
| US7927975B2 (en) | 2009-02-04 | 2011-04-19 | Micron Technology, Inc. | Semiconductor material manufacture |
| JP6501447B2 (en) | 2013-03-26 | 2019-04-17 | 芝浦メカトロニクス株式会社 | Bonding device and method of manufacturing bonded substrate |
| JP6348500B2 (en) | 2013-09-25 | 2018-06-27 | 芝浦メカトロニクス株式会社 | Adsorption stage, bonding apparatus, and manufacturing method of bonding substrate |
| KR102274677B1 (en) * | 2017-09-21 | 2021-07-08 | 에베 그룹 에. 탈너 게엠베하 | Device and method for bonding substrates |
-
1984
- 1984-12-20 JP JP26881384A patent/JPS61145839A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61145839A (en) | 1986-07-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |