JPH0547924A - Semiconductor wafer - Google Patents
Semiconductor waferInfo
- Publication number
- JPH0547924A JPH0547924A JP20912691A JP20912691A JPH0547924A JP H0547924 A JPH0547924 A JP H0547924A JP 20912691 A JP20912691 A JP 20912691A JP 20912691 A JP20912691 A JP 20912691A JP H0547924 A JPH0547924 A JP H0547924A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- wafer
- semiconductor wafer
- thick oxide
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、半導体ウェーハに関
し、特にシリコン基板上に酸化膜を絶縁物として回路を
構成している半導体チップに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer, and more particularly to a semiconductor chip in which a circuit is formed on a silicon substrate using an oxide film as an insulator.
【0002】[0002]
【従来の技術】半導体装置を製造する場合、従来図3に
示すような半導体ウェーハ1が用いられており、この半
導体ウェーハ1に酸化,不純物拡散,フォトエッチン
グ,配線形成等の諸工程を行い素子を製造している。こ
の半導体ウェーハ1上の半導体チップの構造を図4にお
いて説明する。図4は図3の一部を拡大したものであ
る。図4において、2は半導体チップ,3は半導体回路
を構成するエリアで薄い酸化膜,4はチップの絶縁性を
高めるために付けられた厚い酸化膜,5はチップを個片
に切断するために設けられたスクライブ線である。ただ
し、ここには酸化膜は付いていない。以上のような構成
の半導体装置を個片に分割してリードフレーム(図示せ
ず)に搭載し、金属ワイヤ等で接続,モールド被覆をし
て製品としている。2. Description of the Related Art When manufacturing a semiconductor device, a semiconductor wafer 1 as shown in FIG. 3 is conventionally used, and various steps such as oxidation, impurity diffusion, photo-etching and wiring formation are performed on the semiconductor wafer 1. Are manufactured. The structure of the semiconductor chip on the semiconductor wafer 1 will be described with reference to FIG. FIG. 4 is an enlarged view of a part of FIG. In FIG. 4, 2 is a semiconductor chip, 3 is a thin oxide film in an area constituting a semiconductor circuit, 4 is a thick oxide film attached to enhance the insulating property of the chip, and 5 is for cutting the chip into individual pieces. It is a scribe line provided. However, no oxide film is attached here. The semiconductor device having the above-described structure is divided into individual pieces, mounted on a lead frame (not shown), connected with metal wires or the like, and covered with a mold to obtain a product.
【0003】[0003]
【発明が解決しようとする課題】ところが、上記の従来
の素子構造はペレットの外周部(特に高耐圧のパワー素
子において)厚い酸化膜をループ状に配設していた。こ
のような構造をとるとシリコン基板と酸化膜の膨張率の
差によりペレット内で応力が発生し、しいてはウェーハ
全体としてソリが発生してしまうという欠点があった。
またペレットを縦に電流が流れるパワー素子について
は、抵抗を下げるためにウェーハの厚さを極力薄くして
いる関係で、ウェーハのソリに対しては不利である。However, in the above conventional element structure, a thick oxide film is arranged in a loop shape on the outer peripheral portion of the pellet (especially in a power element having a high breakdown voltage). Such a structure has a drawback in that stress is generated in the pellet due to the difference in expansion coefficient between the silicon substrate and the oxide film, which causes warpage in the entire wafer.
In addition, the power element in which a current flows vertically through the pellet is disadvantageous for warping of the wafer because the thickness of the wafer is made as thin as possible in order to reduce the resistance.
【0004】[0004]
【課題を解決するための手段】そこでこの発明は、シリ
コン基板上に酸化膜を絶縁物として回路を構成している
半導体チップ中において、厚い酸化膜をアイランド状に
付けることを特徴としている。Therefore, the present invention is characterized in that a thick oxide film is formed in an island shape in a semiconductor chip that constitutes a circuit using an oxide film as an insulator on a silicon substrate.
【0005】[0005]
【作用】上記構成によると、ペレット内部の応力を半導
体チップのスクライブ線上に逃がすことができるため
に、ウェーハ全体のソリを防止できる。また、これによ
りウェーハ厚さを現状よりもさらに薄くすることができ
るので、特性面の改善も期待できる。According to the above construction, the stress inside the pellet can be released to the scribe line of the semiconductor chip, so that the warp of the entire wafer can be prevented. Further, as a result of this, the wafer thickness can be made thinner than the current one, so that improvement in characteristics can be expected.
【0006】[0006]
【実施例】以下この発明について図面を参照して説明す
る。図1はこの発明の一実施例の平面図である。この図
1は図3と同様なウェーハの一部の拡大図であり、2は
半導体チップ(素子),3は薄い酸化膜,4’は厚い酸
化膜,5はスクライブラインである。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an embodiment of the present invention. 1 is an enlarged view of a part of a wafer similar to FIG. 3, in which 2 is a semiconductor chip (element), 3 is a thin oxide film, 4'is a thick oxide film, and 5 is a scribe line.
【0007】図1において、薄い酸化膜3や厚い酸化膜
4’は、アイランド状に配置されている。薄い酸化膜3
の付いているエリアには、半導体素子の回路や外部電極
とのコンタクトを取る窓(ボンディングパットといいこ
こには図示しない)等を形成する。厚い酸化膜4’は絶
縁性を高めるために設けられており、この付近に高圧が
かかる回路等を設けておく。この実施例によれば、下地
のシリコンと酸化膜3,4’の膨張率の差があっても、
スクライブ線5によって酸化膜がアイランド状に分割さ
れているので、応力がチップ2内で分散してしまうとい
う利点がある。このような構成によって、ウェーハ全体
にかかる応力が低減でき、ひいてはウェーハのソリを防
止できる。また従来と比べて回路として使用できるエリ
ア(薄い酸化膜を付けた3の部分)が広がるので積層度
の向上も図れる利点もある。In FIG. 1, the thin oxide film 3 and the thick oxide film 4'are arranged in an island shape. Thin oxide film 3
In the area marked with, a window (called a bonding pad, not shown here) for making contact with the circuit of the semiconductor element or an external electrode is formed. The thick oxide film 4'is provided to enhance the insulating property, and a high voltage circuit or the like is provided in the vicinity thereof. According to this embodiment, even if there is a difference in expansion coefficient between the underlying silicon and the oxide films 3 and 4 ′,
Since the oxide film is divided into islands by the scribe lines 5, there is an advantage that stress is dispersed in the chip 2. With such a configuration, the stress applied to the entire wafer can be reduced, and the warp of the wafer can be prevented. Further, as compared with the conventional case, the area that can be used as a circuit (the portion 3 where a thin oxide film is attached) is expanded, so that there is an advantage that the stacking degree can be improved.
【0008】[0008]
【実施例2】図2はこの発明の第2実施例の平面図であ
る。この実施例は、前記第1の実施例の厚い酸化膜4’
の付け方を変えた点を除いては、第1の実施例と同様で
あるため、同一部分には同一参照符号を付して、その説
明を省略する。Second Embodiment FIG. 2 is a plan view of a second embodiment of the present invention. In this embodiment, the thick oxide film 4'of the first embodiment is used.
Since the second embodiment is the same as the first embodiment except that the way of attaching is changed, the same portions are denoted by the same reference numerals and the description thereof will be omitted.
【0009】この実施例では、厚い酸化膜4”が、一部
が欠落した枠状であるCの字に複数個重なって配置され
ており、第1の実施例よりも絶縁性を高めたい場合など
に用いると良い。このような構造にすれば絶縁性を損な
うことなく、ペレットの内部の応力を減少させることが
できるという利点がある。In this embodiment, a plurality of thick oxide films 4 "are arranged so as to overlap a part of the frame-like C-shape, and when it is desired to enhance the insulating property as compared with the first embodiment. Such a structure has an advantage that the stress inside the pellet can be reduced without impairing the insulating property.
【0010】[0010]
【発明の効果】以上説明したように、この発明はシリコ
ン基板上に形成する厚い酸化膜をアイランド状に配置す
ることにより、ペレット内部に発生する応力を分散,軽
減したことによりウェーハ全体のソリを防止できる効果
がある。As described above, according to the present invention, by arranging the thick oxide film formed on the silicon substrate in an island shape, the stress generated inside the pellets is dispersed and reduced, so that the warpage of the entire wafer is prevented. There is an effect that can be prevented.
【図1】 この発明の第1実施例の平面図FIG. 1 is a plan view of a first embodiment of the present invention.
【図2】 この発明の第2実施例の平面図FIG. 2 is a plan view of a second embodiment of the present invention.
【図3】 半導体装置を製造する上で材料となるシリコ
ンの基板FIG. 3 is a substrate of silicon which is a material for manufacturing a semiconductor device.
【図4】 従来の実施例を示す平面図FIG. 4 is a plan view showing a conventional example.
1 半導体ウェーハ 2 半導体チップ 3 薄い酸化膜 4’,4” 厚い酸化膜 5 スクライブ線 1 semiconductor wafer 2 semiconductor chip 3 thin oxide film 4 ', 4 "thick oxide film 5 scribe line
Claims (2)
回路を構成している半導体チップ中において、厚い酸化
膜をアイランド状に付けることを特徴とする半導体ウェ
ーハ。1. A semiconductor wafer, wherein a thick oxide film is formed in an island shape in a semiconductor chip that constitutes a circuit using an oxide film as an insulator on a silicon substrate.
ランド状に付けることを特徴とする半導体ウェーハ。2. A semiconductor wafer, characterized in that a thick oxide film is formed in a frame-like island shape with a part missing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20912691A JPH0547924A (en) | 1991-08-21 | 1991-08-21 | Semiconductor wafer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP20912691A JPH0547924A (en) | 1991-08-21 | 1991-08-21 | Semiconductor wafer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0547924A true JPH0547924A (en) | 1993-02-26 |
Family
ID=16567718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP20912691A Pending JPH0547924A (en) | 1991-08-21 | 1991-08-21 | Semiconductor wafer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0547924A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100925483B1 (en) * | 2007-12-07 | 2009-11-06 | 한국전자통신연구원 | Fabrication Method of MEMS Structure |
US9165941B2 (en) | 2013-07-02 | 2015-10-20 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods for fabricating the same |
-
1991
- 1991-08-21 JP JP20912691A patent/JPH0547924A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100925483B1 (en) * | 2007-12-07 | 2009-11-06 | 한국전자통신연구원 | Fabrication Method of MEMS Structure |
US9165941B2 (en) | 2013-07-02 | 2015-10-20 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and methods for fabricating the same |
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