JPH0546487A - Detector for erroneous mounting of file panel - Google Patents

Abstract

PURPOSE:To detect an erroneous mounting of a file panel. CONSTITUTION:A CPU 107 outputs an address and a device number to an address bus 100 and to a signal line 105 respectively. An address conversion circuit 21 converts the address from the CPU 107 into the prescribed address based on the device number, supplying it to a PROM 20. Receiving the data from the PROM 20, the CPU 107 calculates the check sum, and the data is judged to be normal when the result is coincident with the value of the check sum read from the PROM 20. However, in the case of erroneous mounting of a file panel, the device number which the CPU 107 gives to the address conversion circuit 21 does not correspond to the file panel which was mounted erroneously, and data will not be read out from the right address area in the ROM 20. As the result of the check sum, the data is judged to be abnormal, enabling an erroneous detection of the file panel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for detecting when a file board composed of an EEPROM used in a transmission device or the like is erroneously mounted.

[0002]

2. Description of the Related Art An EEPROM is often used for backing up information necessary for a device because it has a characteristic that written data is retained even when power supply to the device is stopped. In addition, the function of holding the state of the device in the transmission device etc.
It is realized by a file board using OM.

The file board is usually designed so that it can be easily attached to and detached from the apparatus in consideration of the life of the EEPROM, and is often treated as one package. The EEPROM mounted on the file board is EEPR
In order to be able to verify the normality of the data stored in the OM, a checksum is usually calculated for each defined block of data written to the EEPROM and written to the EEPROM along with the data.

An example of an apparatus using such a file board is shown in FIG. This device consists of a CPU board 1 and a file board 2.
The CPU board 1 includes the CPU 10 and the file board 2
Each has an EEPROM 20. The CPU 10 and the EEPROM 20 are connected to the address bus 1
00, a data bus 101, a write signal line 102, a read signal line 103, and an EEPROM chip enable signal line 104.

When the CPU 10 writes data to the EEPROM 20, the CPU 10 first outputs the address data to the address bus 100, then outputs the data to be written to the data bus 101 and the write signal to the signal line 102, and also outputs the signal. Output the chip enable signal on line 104. As a result, the data bus 101 is set to the address specified by the address data of the EEPROM 20.
The data output to is written.

On the other hand, when the CPU 10 reads data from the EEPROM 20, the CPU 10 outputs address data to the address bus 100, and at the same time, a read signal and a chip enable signal are sent to the signal lines 103 and 1, respectively.
Output to 04. Upon receiving these data and signals, the EEPROM 20 outputs the data of the address specified by the address data to the data bus 101, and the CP
Send to U10.

FIG. 4 shows a format of data stored in the EEPROM 20. As shown in the figure, the storage area of the EEPROM 20 is divided into a block 200, a checksum area 201 of the block 200, a block 202, and a checksum area 203 of the block 202. The data 300 and the checksum data of the data 300 are respectively divided. 301, data 302, and checksum data 303 of the data 302 are stored.

Therefore, the CPU 10 reads, for example, the data 300 from the EEPROM 20, calculates the checksum thereof, and if the result matches the value of the checksum data 301 read from the EEPROM 20, it is judged that the read data 300 is normal. To do. Similarly for the data 302, the normality is determined using the checksum data 303.

[0009]

However, in a device using such a conventional file board, even if a file board for another device is erroneously mounted, it cannot be detected. That is, as described above, the EEP
Calculate the checksum of the data read from ROM,
Even if the result is compared with the value of the checksum data read from the EEPROM, as long as the data is normal, even if the file board is for another device, the two values are the same and erroneous. The file board that is implemented as described above will be handled in the same way as the original file board.

An object of the present invention is to solve the above problems and provide a file board erroneous mounting detection apparatus for detecting erroneous mounting of a file board.

[0011]

According to the present invention, there is provided an apparatus for detecting erroneous mounting of a file board composed of an EEPROM in which data and its checksum data are stored at predetermined addresses, respectively. Address generating means for outputting corresponding predetermined data, an address conversion circuit for giving address data to the PROM based on the address data and the predetermined data output by the address generating means, and the PRO.
Data inspection means for inspecting the data read from the PROM based on the data read from M and its checksum data is provided.

[0012]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows an example of a file board erroneous mounting detection device according to the present invention. This apparatus includes a CPU board 108 and a file board 222, and the CPU board 108 includes a CPU 107.
However, the file board 200 is provided with an EEPROM 20 and an address conversion circuit 21, respectively. And C
The PU 107 and the EEPROM 20 are the data bus 101,
They are connected by a write signal line 102, a read signal line 103, and an EEPROM chip enable signal line 104. The CPU 101 and the address conversion circuit 21 are connected by the address bus 100 and the device number signal line 105, and the address conversion circuit 21 and the EE are connected.
It is connected to the PROM 20 by an address bus 106.

The address conversion circuit 21 is a circuit for converting the address data from the CPU 107 into a predetermined address based on the device number signal from the CPU 107, and when the device number represented by the given device number signal is different. Converts the same address data from the CPU 107 into different address data. And E
The EPROM 20 stores data and a checksum at different addresses for each file board according to the address data output by the address conversion circuit 21. FIG. 2 shows a format of data stored in the EEPROM 20. As shown in the figure, the storage area of the EEPROM 20 is divided into a block 210, a checksum area 220 of the block 210, a block 211, and a checksum area 221 of the block 211. The data 300 and the checksum data of the data 300 are respectively divided. Thirty
1, data 302, and checksum data 303 of the data 302 are stored. Then, the blocks 210 and 211
The widths of the areas 220 and 221 are the same for all file boards, but the addresses are different for each file board as described above. The address conversion circuit 21 can perform address conversion by various methods, but here, as an example, the device number represented by the device number signal is added to the address from the CPU to perform address conversion.

Next, the operation when the CPU 107 writes and reads data in the EEPROM 20 will be described. CPU 107 is EEPROM 20
When writing data to the CPU 107, the CPU 107 first outputs address data to the address bus 100, and the signal line 105
, A device number signal indicating the device number corresponding to the correctly mounted file board 222 is output. CPU107
Next outputs data to be written to the data bus 101, outputs a write signal to the signal line 102, and outputs a chip enable signal to the signal line 104. When the address conversion circuit 21 receives the address data through the address bus 100, the address conversion circuit 21 sends the address data to the signal line 105.
The address is converted into a predetermined address on the basis of the device number signal supplied from the device and supplied to the EEPROM 20 through the address bus 106. As a result, the EEPROM 20 specified by the address data output from the address conversion circuit 21
The data output to the data bus 101 is written to the address of.

On the other hand, when the CPU 107 reads the data from the EEPROM 20, the CPU 107 outputs the address data to the address bus 100 and the device number signal to the signal line 105, and simultaneously outputs the read signal and the chip enable signal. Output to 103 and 104. When the address conversion circuit 21 receives the address data through the address bus 100, the address conversion circuit 21 converts the address data into a predetermined address based on the device number signal supplied from the signal line 105, and supplies the address to the EEPROM 20 through the address bus 106. Upon receiving these data and signals, the EEPROM 20 outputs the data at the address designated by the address data to the data bus 101 and sends it to the CPU 107.

As described above, in this embodiment, the EEPR is
Writing and reading data to and from the OM20
It can be done as usual without any restrictions.

Next, the operation when the file board of another device is mounted will be described. CPU107 EEP the data
When reading from the ROM 20, the address data and the device number signal are output to the address bus 100 and the signal line 105, respectively, as in the above case. The address conversion circuit 21 converts the address data from the CPU 107 into predetermined address data based on the device number signal, and E
It is given to the EPROM 20. Then, the CPU 107 sets EE
For example, the data 300 is received from the PROM 20, its checksum is calculated, and if the result matches the value of the checksum data 301 read from the EEPROM 20, it is judged that the read data 300 is normal.
However, in this case, since the device number given by the CPU 107 to the address conversion circuit 21 does not correspond to the file board that is erroneously mounted, the data cannot be read from the correct address area from the EEPROM 20, and therefore,
The calculated checksum does not match the value of the read checksum data, and the data is determined to be abnormal. That is, when the file board is erroneously mounted, the data read from the EEPROM is determined to be abnormal, and as a result, the erroneous mounting of the file board can be detected.

[0018]

As described above, in the file erroneous mounting detection device of the present invention, the address given to the EEPROM is converted by the address conversion circuit based on predetermined data. Therefore, by making the predetermined data different for each file board, if the file board is mounted by mistake, the data and checksum data cannot be read from the correct address, and as a result,
Inspection based on the checksum makes it possible to detect erroneous mounting of the file board.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a file board erroneous mounting detection device according to the present invention.

2 is a block diagram of the file board error mounting detection device of FIG.
It is a figure which shows the data format of EPROM.

FIG. 3 is a block diagram showing an example of a conventional file board mismounting detection device.

[Fig. 4] E constituting the file board error mounting detection device of Fig. 3
It is a figure which shows the data format of EPROM.

[Explanation of symbols]

 20 EEPROM 21 address conversion circuit 100, 106 address bus 101 data bus 102 write signal line 103 read signal line 104 chip enable signal 105 device number signal line 107 CPU 108 CPU board 210, 211 data block 220, 221 checksum area 300, 302 Data 301,303 Checksum

Claims (1)

[Claims] 1. An apparatus for detecting erroneous mounting of a file board composed of an EEPROM in which data and its checksum data are stored at predetermined addresses, and outputs address data and predetermined data corresponding to the file board. Address generating means, an address conversion circuit for giving address data to the PROM based on the address data and the predetermined data output from the address generating means, data read from the PROM and its checksum data And a data inspection means for inspecting data read from the PROM based on the above.