JPH05327489A - Digital control phase synchronizing oscillator - Google Patents

Abstract

PURPOSE:To prevent the unnecessary phase vibration from being generated at the time of starting even by constituting a phase synchronizing oscillator employing a digital control oscillators whose central frequency is different from the nominal frequency. CONSTITUTION:A digital phase comparator 2 outputs the digital phase difference signal corresponding to the phase difference of both a reference clock signal inputted to an input terminal 1 and an output clock signal of a digital control oscillator 6. An arithmetic unit 3 receives the digital phase difference signal, and outputs a 1st digital control signal proportional to the phase difference from a proportionality control term 31. By adding the same digital phase difference signal to an integral control term 32, an integrated 2nd digital control signal integrated after multiplying a very small coefficient by a digital phase difference signal is outputted. a second digital control signal is stored in a nonvolatile memory 4. An adder 5 adds the output from the nonvolatile memory 4 to the 1st digital control signal from the arithmetic unit 3, then outputs a control signal to the digital control oscillator 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digitally controlled phase locked oscillator which is frequently used in a network synchronizer or the like installed for the purpose of establishing synchronization of the entire network. The present invention relates to a digitally controlled phase locked oscillator capable of automatically compensating.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram showing the configuration of a conventional digitally controlled phase locked oscillator. In FIG.
Reference numeral 1 is an input terminal for supplying a reference clock signal to the digitally controlled phase locked oscillator, and 7 is an output terminal of the digitally controlled phase locked oscillator. Reference numeral 2 denotes a phase difference between the reference clock signal given from the input terminal 1 and the output signal of the present digitally controlled phase locked oscillator outputted from the output terminal 7, and a digital phase difference signal corresponding to the phase difference between the two signals. Is a digital phase comparator for generating a signal, and is composed of, for example, a phase comparator used in a normal analog type phase locked oscillator and an appropriate A / D converter. Reference numeral 8 denotes an arithmetic unit that adds predetermined arithmetic processing to the digital phase difference signal to generate a digital control signal, and is usually realized by a microprocessor or the like. Here, the computing unit 8
Is a portion corresponding to a loop filter in a normal analog phase-locked oscillator, and can be variously determined according to the characteristics required of the phase-locked oscillator. For example, when the characteristic of the digital control phase locked oscillator is the primary loop characteristic, the digital control signal proportional to the input digital phase difference signal is obtained by multiplying the digital phase difference signal received by the calculator 8 by a necessary coefficient. Is generated. When the digital control phase locked oscillator has a secondary loop characteristic, the digital control signal can be generated by adding and integrating the input digital phase difference signals. Reference numeral 6 denotes a digital control oscillator for generating an output signal having a frequency corresponding to a given digital control signal, which is composed of, for example, an appropriate D / A converter and an ordinary voltage control oscillator.

As is clear from the above description, the digitally controlled phase locked oscillator is a part of the general phase locked oscillator which is equivalent to the loop filter realized by digital arithmetic processing. Performs the same operation as a synchronous oscillator. As described above, the digitally controlled phase-locked oscillator has a feature that the phase-locking characteristic can be arbitrarily determined by the calculation process of the calculation unit, and therefore it is difficult to realize with the analog phase-locked oscillator due to the advanced calculation process. It is used as a means for realizing complicated characteristics. For example, in the case of an ultra-stable phase-locked oscillator required for a network synchronizer or the like, a phase difference signal as indicated by a broken line in the calculator 8 of FIG. And a proportional control term 81 for performing control proportional to the digital control oscillator, and an integral control term 82 obtained by multiplying the phase difference signal by a very small coefficient for integration for the purpose of compensating for a change with time of the digitally controlled oscillator, and adding the two to obtain a digital control term. The control signal is generated, and as a result, the transient characteristics such as pull-in and the jitter suppression characteristics are almost the same as those of the phase-locked oscillator having the first-order filter. Even when the wave number is different from the nominal frequency, such as not to generate a steady phase error, the steady-state characteristic is realized digitally controlled phase locked oscillator having the features of the phase-locked oscillator having a second- or higher-order filter.

[0004]

In such a conventional digitally controlled phase locked oscillator, the initial value of the integral control term is preset to a fixed value, for example, "0", and a very small coefficient is used. Since it is multiplied, the effective integral control term is not generated unless the digital phase difference signal obtained from the digital phase comparator is integrated for a long time. That is, in the digital control signal generated at the initial stage of startup, the integral control term is almost “0”, and as a result, it is almost equal to the proportional control term, and the integral control term added for the purpose of improving the steady-state characteristic. It means that the effect of cannot be obtained. Therefore, when the center frequency of the digitally controlled oscillator exactly matches the nominal frequency, a large steady phase error does not occur, but
If the difference between the center frequency of the digitally controlled oscillator and the nominal frequency increases after a long time has passed since the manufacture, the period of the reference input signal It is unavoidable that a large steady phase error occurs depending on the difference between the frequency and the center frequency of the digitally controlled oscillator, and this steady phase error decreases as the integral control term is generated. Therefore, in such a conventional digitally controlled phase locked oscillator, there is a problem that the phase fluctuation as described above occurs every time the control is activated, and a network synchronization device using such a digitally controlled phase locked oscillator is encountered. However, there is a problem that the reference clock phase in the network is changed each time it is activated.

Although the characteristics of the digitally controlled oscillators are generally different from each other, in the conventional digitally controlled phase locked oscillators, the center frequencies of all the digitally controlled oscillators are accurately measured in order to minimize the steady phase error in the initial stage of startup. It matched the nominal frequency. For this reason, it is necessary to make different strict adjustments for each digitally controlled oscillator, which not only takes a lot of time for manufacturing, but also mass production is extremely difficult, resulting in high manufacturing cost. Had a point.

An object of the present invention is to prevent unnecessary phase fluctuation at the time of start-up even if a phase-locked oscillator is constructed using a digitally controlled oscillator whose center frequency is different from the nominal frequency due to aging or individual difference. It is in.

[0007]

To achieve the above object, the present invention compares the phases of an input signal and an output signal given from the outside and generates a digital phase difference signal according to the phase difference between the two signals. A digital phase comparator, and an arithmetic unit that performs an arithmetic process for generating a first digital control signal proportional to the digital phase difference signal and an arithmetic process for generating a second digital control signal by integrating the same digital phase difference signal A non-volatile memory for storing the second digital control signal, an adder for adding the first digital control signal and the output signal of the non-volatile memory to generate a control signal for the digitally controlled oscillator, and an adder for responding to the control signal. And a digitally controlled oscillator for generating a clock signal of different frequency.

Further, in order to achieve the above-mentioned object, the present invention uses the initial value of the integral operation of the arithmetic unit as the output signal of the non-volatile memory.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a digitally controlled phase locked oscillator according to the present invention. Among the constituent elements in the figure, the elements 1, 2, 6 and 7 have the same functions as the elements with the same numbers shown in FIG. 2 as the configuration of the conventional phase locked oscillator. In this embodiment, the digital phase comparator 2 is assumed to generate a natural binary number having a magnitude corresponding to the phase difference between the two input signals, and the two input signals have the same phase. In this case, "0" is output, and when the phase of the signal output from the output terminal 7 lags behind the reference input signal given from the input terminal 1, the digital phase difference signal having a positive value is output, and vice versa. If the signal is leading, it shall generate a negative digital phase difference signal.

3 adds the digital phase difference signal generated by the digital phase comparator 2 to the proportional control term 31 to integrate the first digital control signal proportional to the digital phase difference signal and the same digital phase difference signal. By adding to the control term 32, it is a computing unit that separately generates a second digital control signal obtained by multiplying the digital phase difference signal by a very small coefficient and then integrating. Reference numeral 4 denotes a non-volatile memory that stores the second digital control signal output from the integral control term 32. The written signal is always output immediately after writing, and is left in a state where the power is turned off. However, the contents do not disappear. It is assumed that a predetermined value is written at the time of manufacturing, and "0" is written in this embodiment. Also, the computing unit 3
When the digital control phase-locked oscillator is started and the arithmetic processing is started, the second digital control signal stored in the non-volatile memory 4 is read out, and this value is used as the initial value of the integral control term 32 for the arithmetic operation. Start. 5 is a computing unit 3
This is an adder that adds the first digital control signal generated in step 2 and the second digital control signal stored in the nonvolatile memory 4 to generate the control signal of the digital control oscillator 6.

Next, the operation of the digitally controlled phase locked oscillator of the present invention will be described. The reference clock signal supplied from the input terminal 1 and the output clock signal of the digital control oscillator 6, that is, the output signal of the digital control phase locked oscillator output from the output terminal 7 are compared in phase by the digital phase comparator 2. Then, a digital phase difference signal corresponding to the phase difference between the two signals is generated. The arithmetic unit 3 receives this digital phase difference signal, calculates the average value of this signal, and outputs the first digital control signal proportional to the phase difference by the proportional control term 31 to output the same digital phase difference signal. By adding to the integral control term 32, the digital phase difference signal is multiplied by a very small coefficient and integrated to output a second digital control signal. Here, the initial value of the integral calculation is the nonvolatile memory 4 as described above.
The value stored in is read and applied to it, but when the calculation is first started after manufacturing, the value is “0”. The second digital control signal output from the computing unit 3 is immediately stored in the non-volatile memory 4, and
It is given to the adder 5. The adder 5 adds the second digital control signal from the nonvolatile memory 4 and the first digital control signal from the arithmetic unit 3 to generate a control signal for the digital control oscillator 6. Here, since the control signal actually given to the digital control oscillator 6 is the sum of the signals output from the proportional control term 31 and the integral control term 32, the above-mentioned conventional digital control phase locked oscillator. It has exactly the same value as the control signal given to the digitally controlled oscillator 6 of FIG.

Generally, since the center frequency of the digitally controlled oscillator 6 does not exactly match the nominal frequency, the phases of both signals change according to the frequency difference immediately after the start-up. Therefore, the digital phase comparator 2 outputs a positive (or negative) digital phase difference signal according to the phase difference each time, and the calculator 3 performs the above calculation based on this value, , Generate a second digital control signal. Here, as described above, the initial value of the integral calculation performed by the calculator 3 is "0", and since it is multiplied by a very small coefficient, the second digital control signal at the beginning of activation is almost " It is "0". Therefore, even if the control is started, the phase difference between the two signals does not immediately become "0", and the digital phase difference signal corresponding to the steady phase error is continuously output. As a result, the integral control term 32 in the arithmetic unit 3 is gradually accumulated, and the second digital control signal gradually increases (or decreases). As described above, since the control signal actually given to the digitally controlled oscillator 6 is a signal obtained by adding the first and second digital control signals,
If the frequency error of the digitally controlled oscillator 6 is constant,
As the second digital control signal increases (or decreases), the first digital control signal decreases (or increases). Such an operation is continued until the phases of the two signals applied to the digital phase comparator 2 coincide with each other and a digital phase difference signal of "0" is generated, and the first digital control signal becomes "0". , The second digital control signal only has a value corresponding to the frequency error and is in a steady state. Of course, if a phase fluctuation occurs in the reference input signal in this state, the first digital control signal changes according to the fluctuation amount, but the second digital control signal is multiplied by a very small coefficient. Therefore, the value hardly changes with the phase fluctuation in a short time. However, when the frequency is gradually changed like the time-dependent change of the digitally controlled oscillator 6, the signal output from the integral control term 32, that is, the second digital control signal is also changed according to the frequency change. Will be done. in this way,
In the digitally controlled phase locked oscillator of the present invention, by appropriately determining the coefficient of the integral control term 32, the control corresponding to the short-term fluctuation of the reference input signal is performed by the first digital control signal. Only the control corresponding to the steady change such as the change with time can be performed by the second digital control signal.

Next, the operation when the digitally controlled oscillator 6 is restarted when a long time has passed after the manufacturing and the difference between the center frequency and the nominal frequency becomes large will be described. In this case as well, the same operation as in the case of starting immediately after manufacturing is performed, but since the second digital control signal calculated by the past control is already stored in the nonvolatile memory 4, this value Is set as the initial value of the integral control term 32, a signal sufficient to compensate the error of the center frequency is immediately generated from the integral control term 32, and a digital control signal equal to the steady state is obtained immediately after restarting. become.

[0015]

As is apparent from the above description, in the digitally controlled phase locked oscillator of the present invention, a control signal sufficient for compensating the frequency deviation of the digitally controlled oscillator is provided after the operation for a certain period. Even if a digitally controlled oscillator that can be generated immediately after start-up and whose center frequency changes greatly due to changes over time is used, there is an effect that unnecessary phase fluctuations do not occur at restarting. Even if the characteristics of the time-dependent changes of the individual digitally controlled oscillators are different, the digitally controlled oscillators and the control signals for compensating for the frequency deviation are physically integrated, so that the individual digitally controlled oscillators are always controlled. A control signal corresponding to the oscillator can be generated, and there is an effect that unnecessary phase fluctuation does not occur even if the digital control oscillator is replaced. Furthermore, even if the center frequencies of the digitally controlled oscillators are different at the time of manufacture, a control signal that compensates for the frequency error of each digitally controlled oscillator is automatically generated and stored by operating for a certain period of time. There is an effect that it is not necessary to make different strict adjustments individually for each digitally controlled oscillator, and a large amount can be produced in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digitally controlled phase locked oscillator of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional digitally controlled phase locked oscillator.

[Explanation of symbols]

 1 Input Terminal 2 Digital Phase Comparator 3 Arithmetic Unit 31 Proportional Control Term 32 Integral Control Term 4 Nonvolatile Memory 5 Adder 6 Digitally Controlled Oscillator 7 Output Terminal

Claims (2)

[Claims] 1. A digital phase comparator for comparing the phases of an input signal and an output signal given from the outside to generate a digital phase difference signal according to the phase difference between both signals, and a first phase proportional to the digital phase difference signal. The second which integrates the same digital phase difference signal as the arithmetic processing for generating the digital control signal
And a non-volatile memory for storing a second digital control signal, a first digital control signal and an output signal of the non-volatile memory, and a digital control oscillator. And a digital control oscillator for generating a clock signal having a frequency according to the control signal. 2. The digitally controlled phase-locked oscillator according to claim 1, wherein an initial value of the integral operation of the arithmetic unit is an output signal of the non-volatile memory.