JPH05327443A - Buffer circuit - Google Patents

Abstract

PURPOSE:To suppress deviation in an electric potential at an output terminal, a power supply terminal and a ground terminal due to a parasitic inductance of a wire, etc., and to ensure a high speed output inversion. CONSTITUTION:The buffer circuit is provided with a 1st buffer circuit 100 and a 2nd buffer circuit 200 and each output connects to the same output terminal 700. A stop signal generating circuit 50 of a control circuit section 300 stops drive of the 2nd buffer circuit 200 in the 1st and 2nd buffer circuits 100, 200 driven simultaneously by detecting a change in an electric potential at the output terminal 700 to keep a high speed output inversion and to suppress fluctuation in an electric potential at an output terminal, a power supply terminal and a ground terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a buffer circuit.

[0002]

2. Description of the Related Art A buffer circuit of this type will be described by taking an output buffer circuit used for output of a logic circuit as an example.

FIG. 5 is a circuit diagram showing an example of a conventional output buffer circuit. This output buffer circuit is connected in series between the power supply terminal 400 and the ground terminal 500.
An inverter having a channel MOS transistor (hereinafter, referred to as a PMOS transistor) 31 and an N channel MOS transistor (hereinafter, referred to as an NMOS transistor) 32, the gate electrodes of the two transistors are commonly connected, and an input terminal 600 is used as an input. The output signal of 30 is input to the gate electrode.

The common drain electrode is the output terminal 70.
Connected to 0. Generally, since the load of the output buffer circuit is large, the current driving capability of the driving transistor is large. Especially when high speed is required, the current driving capability must be further increased.

[0005]

A large drive current flows when the output signal of the conventional output buffer circuit changes from a high potential to a low potential or from a low potential to a high potential.

However, as shown in FIG.
And the PMOS transistor 31 have a parasitic inductance 33, the ground terminal 500 and the NMOS transistor 32 have a parasitic inductance 34, and the output terminal 700 and the drain electrodes of both transistors have a parasitic inductance 35. There is.

Therefore, as shown in FIG. 6, when the potential of the output terminal 700 changes from a high potential to a low potential with respect to the change of the potential of the input terminal 600, the potential further lowers from the ground level.
Next, it rises above the ground level and oscillates with a certain period.

When the potential of the output terminal 700 changes from a low potential to a high potential, the output level further rises above the power supply level, then falls below the power supply level, and oscillates with a certain period.

Further, when the potential of the output terminal 700 fluctuates, the potential of the power supply terminal 400 and the ground terminal 500 are changed.
The potential of is influenced by the potential of the output terminal 700 and swings.
The greater the drive capability of the transistor, the greater the amplitude of these swings.

Further, due to the swing of the potential of the power supply terminal 400 and the potential of the ground terminal 500, the output potential of another output buffer circuit connected to the same power supply terminal and the ground terminal and the signal potential of the peripheral logic circuit simultaneously swing.

[0011] The fluctuation of the potential of the output terminal 700, the fluctuation of the potential of the power supply terminal 400, and the ground terminal 50.
The fluctuation of the potential of 0 reduces the operation margin of its own buffer circuit and peripheral circuits.

The above-mentioned fluctuation of the potential has become a particularly serious problem in recent high-speed, highly integrated, large-scale semiconductor integrated circuits.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a buffer circuit which has the above-mentioned problems of the conventional buffer circuit and which maintains high speed and is less likely to cause fluctuations in the potentials of the output, the power supply and the ground.

[0014]

In order to achieve the above object, a buffer circuit according to the present invention is a buffer circuit having a first buffer circuit and a second buffer circuit, and a control circuit section. The first buffer circuit and the second buffer circuit are connected in parallel between the input terminal and the output terminal and driven at the same time, or only one of them is driven, and the control circuit unit includes a stop signal generation circuit. The stop signal generation circuit is for generating a drive stop command according to a potential change of the output terminal to the second buffer circuit of the simultaneously driven first and second buffer circuits.

Further, the stop signal generating circuit of the control circuit section has an output judging inverter and a delay circuit which have the potential of the output terminal as an input signal and have an appropriate logical threshold value. When the potential of the output terminal changes, the output signal of the output determination inverter is delayed by the delay circuit from the time when the potential of the output terminal reaches the logical threshold value of the output determination inverter, and the load and drive of the buffer circuit are driven. The driving of the second buffer circuit is stopped after a delay of an optimum delay time commensurate with the capability.

In the first buffer circuit, the P-channel MOS transistor and the N-channel MOS transistor are connected in a CMOS inverter structure, and the inverted signal obtained by inverting the input signal applied to the input terminal is input. And the second buffer circuit is a P-channel MOS
CM for transistor and N-channel MOS transistor
The stop signal generation circuit of the control circuit unit is connected to an OS inverter configuration, and a high potential detection inverter having a high logic threshold voltage and a low logic threshold for detecting the potential of the output terminal. A low potential detecting inverter having a value voltage, a NAND circuit having an input signal from the input terminal and an output signal of the high potential detecting inverter as an input, and an input signal from the input terminal and a low potential detecting inverter A NOR circuit that receives the output signal and the input,
The output signal of the NAND circuit is input to the gate of the P-channel MOS transistor of the second buffer circuit, and NOR
The output signal of the circuit is the N channel M of the second buffer circuit.
The configuration is such that it is input to the gate of the OS transistor.

In addition to the control circuit section, a through current prevention section is provided, and the through current prevention section is provided with the first buffer circuit and the second buffer circuit when the potential of the input terminal changes from a high potential to a low potential. When the P-channel MOS transistor of the buffer circuit of is changed from ON to OFF, the N-channel MOS transistor is changed from OFF to ON, and when the potential of the input terminal is changed from low potential to high potential, the N-channel MOS transistor is changed from ON to The signal processing is such that the P-channel MOS transistor is changed from OFF to ON after the change to OFF.
An enable terminal instead of the ND circuit and the NOR circuit,
A 3-input NAND circuit which receives the output signal for the P-channel MOS transistor of the shoot-through current prevention circuit part, the inverted signal of the enable terminal inverted by the inverter, and the output signal of the high-potential detection inverter, and the shoot-through current prevention circuit part A three-input NOR circuit that receives the N-channel MOS transistor output signal, the enable terminal input signal, and the low-potential detection inverter output signal as input, and the P-channel MOS transistor output signal of the shoot-through current prevention circuit section,
2-input NAND with inverted signal of enable terminal as input
It has a circuit and a 2-input NOR circuit which receives the output signal for the N-channel MOS transistor of the shoot-through current prevention circuit section and the input signal of the enable terminal.

[0018]

As shown in FIG. 1, the first buffer circuit 100
And the second buffer circuit 200, and their outputs are connected to the same output terminal 700. Control circuit unit 30
The stop signal generation circuit 50 of 0 stops the driving of the second buffer circuit 200 of the simultaneously driven first and second buffer circuits 100 and 200 by detecting the change in the potential of the output terminal 700. Therefore, the high speed of the output inversion is maintained and the fluctuation of the potentials of the output, the power supply and the ground is suppressed to be small.

[0019]

The present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention.

In FIG. 1, a first buffer circuit 100 in which a PMOS transistor 2 and an NMOS transistor 3 are connected in a CMOS inverter configuration, and a first buffer circuit 100 in which a PMOS transistor 8 and an NMOS transistor 9 are connected in a CMOS inverter configuration. Two buffer circuits 200
And a control circuit unit 300.

The output of the first buffer circuit 100 and the second buffer circuit 200 are the input terminal 600 and the output terminal 7.
00 and 50 are connected in parallel and are driven simultaneously, or only one of them is driven. The input signal of the input terminal 600 is input to the inverter 1, and its output signal is input to the first buffer circuit 100.

The control circuit section 300 includes a stop signal generation circuit 5
0, a NAND circuit 6 and a NOR circuit 7, the potential of the output terminal 700 is input to the stop signal generation circuit 50, the output signal and the input signal of the input terminal 600 are input to the NAND circuit 6, and the output thereof is a PMOS. It is input to the gate of the transistor 8.

The output of the stop signal generation circuit 50 and the input signal of the input terminal 600 are input to the NOR circuit 7, and the output thereof is input to the gate of the NMOS transistor 9.

The circuit operation of this embodiment will be described below. When the potential of the input terminal 600 changes from a high potential to a low potential, the PMOS transistors 2 and 8 are turned off and the NMOS
The transistors 3 and 9 are turned on.

At this time, the potential of the output terminal 700 changes from a high potential to a low potential. The stop signal generation circuit 50 detects the potential of the output terminal 700 and outputs a stop signal. This stop signal causes the NMOS of the second buffer circuit 200 to
The transistor 9 turns off.

On the contrary, when the potential of the input terminal 600 changes from the low potential to the high potential, the PMOS transistors 2 and 8 are turned on.
Then, the PMOS transistors 3 and 9 are turned off. At this time, the potential of the output terminal 700 changes from a low potential to a high potential. This potential change turns off the PMOS transistor 9 of the second buffer circuit 200.

As described above, in the buffer circuit of the present invention, when the signal at the input terminal 600 changes, the current driving capability of the first buffer circuit 100 and the current driving capability of the second buffer circuit 200 are summed to achieve high speed operation. , The potential of the output terminal 700 can be changed, and the change in the output is determined,
Or, when the change is complete, the first one being driven simultaneously
And by stopping the driving ability of the second buffer circuit 200 of the second buffer circuits 100 and 200,
The amplitude of fluctuations in the output potential, power supply potential, and ground potential after the output is determined is reduced.

FIG. 6 shows the output signal OUT 'of the output terminal 700.
Indicates. The amplitude of the fluctuation of the potential is smaller than that of the output signal OUT of the conventional example.

(Second Embodiment) FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

The present embodiment differs from the first embodiment shown in FIG. 1 in that the stop signal generating circuit is composed of an output judging inverter 25 and a delay circuit 26, and the potential of the output terminal 700 is the logic of the output judging inverter 25. The point is that the delay circuit 26 is limited to the stop signal generation circuit that delays the second buffer circuit 200 by delaying it for a certain period of time after the threshold value is reached.

The operation of the buffer circuit with respect to changes in the output level will be described below.

When the potential of the output terminal 700 changes from the high potential to the low potential, the output judging inverter 25 changes from the low potential to the high potential and is delayed by the time corresponding to the load of the buffer circuit, and the delay circuit 26. Output changes from low potential to high potential.

At this time, since the input terminal 600 is at the low potential, the output of the NAND circuit 6 is not changed and is at the high potential, and the PMOS transistor 8 remains OFF, while the output of the NOR circuit 7 is output. Changes from high potential to low potential, and the NMOS transistor 9 changes from ON to OFF.

Similarly, when the potential of the output terminal 700 changes from a low potential to a high potential, the NMOS transistor 9 becomes O.
It remains FF, and the PMOS transistor 8 changes from ON to OFF.

As described above, in the buffer circuit of the second embodiment, when the signal at the input terminal 600 changes, the output terminal is determined by the sum of the driving capacity of the first buffer circuit 100 and the driving capacity of the second buffer circuit 200. It is possible to drive the load connected to 700 at a high speed, and stop the second buffer circuit 200 with a delay from the time when the change in the output is determined and the time when the output is expected to be stable. Characterize.

(Embodiment 3) FIG. 3 is a circuit diagram showing Embodiment 3 of the present invention.

The present embodiment is different from the first embodiment shown in FIG. 1 in that the stop signal generating circuit is composed of a high potential detecting inverter 4 and a low potential detecting inverter 5, and an output terminal 700 is provided.
The point is that the stop signal generation circuit is limited so that the second buffer circuit 200 is stopped at the time when the potential changes to the high potential level or the low potential level.

The operation of the buffer circuit with respect to changes in the output level will be described below.

When the potential of the output terminal 700 changes from the high potential to the low potential, the output of the high potential detecting inverter 4 changes from the low potential to the high potential, and the input terminal 600 is at the low potential at this time. , The output of the NAND circuit 6 does not change and has a low potential, and the PMOS transistor 8 is turned off.
It remains.

On the other hand, the low potential detecting inverter 5 has a low logic threshold value, and its output is the output terminal 700.
Changes from a low potential to a high potential at a time when the voltage drops below the low potential level required for the buffer circuit, the NOR circuit 7
Output changes from high potential to low potential, and the NMOS transistor 9 changes from ON to OFF.

Similarly, when the output terminal 700 rapidly changes from a low potential to a high potential, the NMOS transistor 9 is OF
It remains F, and the PMOS transistor 8 goes from ON to O
Change to FF.

As described above, in the buffer circuit of the third embodiment, when the signal at the input terminal 600 changes, the output terminal is obtained by the sum of the driving capacity of the first buffer circuit 100 and the driving capacity of the second buffer circuit 200. Regardless of the size of the load connected to 700, it can be driven at high speed until the potential of the output terminal 700 becomes higher than the high potential level or becomes lower than the low potential level. The second buffer circuit 200 is stopped when the output level required by the buffer circuit is reached.

(Fourth Embodiment) FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

The present embodiment is different from the third embodiment shown in FIG. 3 in that the input signal of the input terminal 600 is input to the shoot-through current prevention circuit section 800, and one of the output signals is 2 NAN.
The other signal is input to the D circuit 18 and the 3NAND circuit 20, and the other signal is input to the 2NOR circuit 19 and the 3NOR circuit 21.

The input signal of the enable terminal 900 is 2N.
It is input to the OR circuit 19, the 3 NOR circuit 21 and the inverter 24, and the output signal of the inverter 24 is the 2 NAND circuit 1
8 and 3 are input to the NAND circuit 20.

The output of the 2NAND circuit 18 is input to the gate of the PMOS transistor 2 of the first buffer circuit 100, and the output of the 2NOR circuit 19 is input to the gate of the NMOS transistor 3 of the first buffer circuit 100.

The output of the 3NAND circuit 20 is input to the gate of the PMOS transistor 8 of the second buffer circuit 200, and the output of the 3NOR circuit 21 is input to the gate of the NMOS transistor 9 of the second buffer circuit 200.

The output signal of the second buffer circuit 200 is connected to the output terminal 700 of the first buffer circuit 100,
Further, it is inputted to the high potential detecting inverter 22 and the low potential detecting inverter 23.

The output signal of the high potential detecting inverter 22 is input to the 3NAND circuit 20, and the output signal of the low potential detecting inverter 23 is input to the 3NOR circuit 21.

The circuit operation of the fourth embodiment will be described below. When the input terminal 600 changes from the high potential to the low potential, the PMOS transistor 2 of the first buffer circuit 100 is turned on.
After FF, the NMOS transistor 3 of the first buffer circuit 100 and the NMOS transistor 9 of the second buffer circuit 200 change from OFF to ON, and the output terminal 700
Changes rapidly from a high potential to a low potential.

At this time, the output of the low potential detecting inverter 23 changes from the low potential to the high potential, the output of the 3NOR circuit 21 changes from the high potential to the low potential, and the second buffer circuit 2
The NMOS transistor 9 of 00 changes from ON to OFF.

Similarly, when the input terminal 600 changes from a low potential to a high potential, the NMOS transistor 3 turns off, the PMOS transistors 2 and 8 turn on, and the output terminal 700 changes from a low potential to a high potential. 8 changes from ON to OFF.

In addition, PM is output by the signal of the enable terminal.
OS transistors 2, 8 and NMOS transistors 3, 9
All driving can be stopped.

As described above, the fourth embodiment is characterized in that the buffer circuit of the third embodiment is provided with the through current prevention circuit portion 800 and the enable terminal 900.

[0056]

As described above, according to the present invention, the driving ability of the buffer circuit is divided into the first buffer circuit and the second buffer circuit, and the first buffer circuit is provided until the first period or before the completion of the output change. And the second buffer circuit are driven, and the driving of the second buffer circuit is stopped in the latter half of the output change or after the completion of the output change. Therefore, a large current drive buffer for driving a particularly large load is provided. In the circuit, fluctuations in the potentials of the output terminal, the power supply terminal, and the ground terminal are small, and it is possible to prevent an error in the output determination and to achieve a high inversion speed.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a conventional output buffer circuit.

FIG. 6 is a diagram showing changes in the potential of the output terminal with respect to changes in the potential of the input terminal.

[Explanation of symbols]

 4 Inverter for high potential detection 5 Inverter for low potential detection 25 Inverter for output determination 26 Delay circuit 50 Stop signal generation circuit 100 First buffer circuit 200 Second buffer circuit 300 Control circuit section 400 Power supply terminal 500 Ground terminal 600 Input terminal 700 Output terminal 800 Through current prevention circuit section 900 Enable terminal

Claims (4)

[Claims] 1. A buffer circuit having a first buffer circuit and a second buffer circuit, and a control circuit section, wherein the first buffer circuit and the second buffer circuit have an input terminal and an output terminal. Connected in parallel between them, driven simultaneously,
Alternatively, only one of them is driven, the control circuit section has a stop signal generation circuit, and the stop signal generation circuit is a second buffer circuit of the simultaneously driven first and second buffer circuits. And a buffer circuit for generating a drive stop command according to a change in the potential of the output terminal. 2. The buffer circuit according to claim 1, wherein the stop signal generation circuit of the control circuit section uses the potential of the output terminal as an input signal and has an output determination inverter having an appropriate logic threshold value. And a delay circuit, the control circuit unit outputs the output signal of the output judging inverter from the time when the potential of the output terminal reaches the logical threshold value of the output judging inverter when the potential of the output terminal changes. A buffer circuit which delays by a delay circuit and delays driving of the second buffer circuit with an optimum delay time commensurate with the load and driving capability of the buffer circuit. 3. The buffer circuit according to claim 1, wherein the first buffer circuit connects a P-channel MOS transistor and an N-channel MOS transistor in a CMOS inverter configuration, and an input applied to an input terminal. An inverted signal obtained by inverting a signal is input, and the second buffer circuit is configured by connecting a P-channel MOS transistor and an N-channel MOS transistor in a CMOS inverter configuration, and a stop signal of the control circuit unit. The generation circuit includes a high potential detection inverter having a high logic threshold voltage, a low potential detection inverter having a low logic threshold voltage, and an input from the input terminal for detecting the potential of the output terminal. Signal and an output signal of a high-potential detection inverter, and a NAND circuit having the input signal from the input terminal And a NOR circuit that receives the output signal of the low-potential detection inverter as input, and the output signal of the NAND circuit is input to the gate of the P-channel MOS transistor of the second buffer circuit, and NOR
The output signal of the circuit is the N channel M of the second buffer circuit.
A buffer circuit having a configuration of being input to a gate of an OS transistor. 4. The buffer circuit according to claim 3, further comprising a through current prevention unit in addition to the control circuit unit, wherein the through current prevention unit changes the potential of the input terminal from a high potential to a low potential. When changing, the N-channel MOS transistor changes from OFF to ON after the P-channel MOS transistors of the first buffer circuit and the second buffer circuit change from ON to OFF, and the potential of the input terminal changes from low potential to high potential. When the N-channel MOS transistor is changed from ON to OFF, the P-channel MOS transistor is changed from OFF to ON, and the control circuit unit controls the NAND circuit and the NOR circuit. Instead of the enable terminal, the output signal for the P-channel MOS transistor of the shoot-through current prevention circuit, and the inversion by the inverter A three-input NAND circuit that receives the inverted signal of the enable terminal and the output signal of the high-potential detection inverter, the output signal for the N-channel MOS transistor of the shoot-through current prevention circuit, the input signal of the enable terminal, and the low signal. A 3-input NOR circuit that receives the output signal of the potential detection inverter, a 2-input NAND circuit that receives the output signal for the P-channel MOS transistor of the shoot-through current prevention circuit section and the inverted signal of the enable terminal, and a shoot-through current prevention circuit Circuit for inputting the output signal for the N-channel MOS transistor of the same section and the input signal of the enable terminal.