JPH05324871A - Microcomputer - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a microcomputer by stopping the supply of operation clocks to the unnecessary hardware without using any HALT nor STOP instruction. CONSTITUTION:Each of peripheral hardware 41-44 is provided with an operation designating/storing means 54 which stores the data to previously designate the operation of its own device and outputs a prescribed signal, the sensor means 51 and 52 which sense the access of data given to its own device from a CPU 20, and individual clock control means 53 and 55 which supply the operation clock signals 102 supplied from the CPU 20 to a peripheral hardware core 56 as the operation clock signals 109 to be supplied to its own device when its own device receives an access and then stop the supply of the signal 102 which no access is applied to its own device based on the output signal of the means 54 and the output signals 107 of both means 51 and 52.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, and more particularly to a microcomputer provided with a means for reducing power consumption.

[0002]

2. Description of the Related Art Today, technological advances in the computer field have been remarkable, and notebook computers, palmtop computers, etc. have appeared on the market.

Under these circumstances, demands for low power consumption devices have recently been increased, and low power consumption microcomputers have been required to fulfill their central functions.

Generally, as the operation for such low power consumption, a method of stopping the operation of the CPU when the central processing unit (hereinafter referred to as CPU) of the microcomputer is unnecessary or an operation of the entire microcomputer is stopped. There is a method and both are often equipped with special instructions.

Usually, the former is a HALT command and the latter is an STO.
We call it P command.

The functions of the HALT instruction and the STOP instruction in the conventional microcomputer will be described below with reference to FIG.

FIG. 3 is a block diagram showing a main part of an example of a conventional microcomputer, which includes a CPU 20, a program section 10 in which a program is stored, and peripheral hardware 30.

Then, the CPU 20 decodes a program instruction, a decoder unit 21, a control unit 22 that performs various controls according to the decoding result, an operation clock signal 101 of the CPU 20, and an operation clock signal of the peripheral hardware 30. 102, CPU 20, peripheral hardware 30
And a clock control signal 103 and 104 output from the control unit 22 for controlling the clock, respectively. The wear 30 includes peripheral hardware (A) 31, peripheral hardware (B) 32, and peripheral hardware (C) 33.
A peripheral hardware (D) 34 and an external terminal 35 for the peripheral hardware (A) 31 to receive external data.
Includes and. In addition, peripheral hardware (A) 31
Receives the data input from the external terminal 35,
It has a means to transfer to U20.

Next, the operation of the CPU 20 when executing the HALT instruction will be described.

The CPU 20 reads the program from the program section 10, and the decoder section 21 decodes and executes the instruction. When the HALT instruction is read from the program unit 10 and decoded by the decoder unit 21, the control unit 22
Outputs the clock control signal 103 to the clock control unit 23, and the clock control unit 23 only supplies the operation clock signal 102 to the peripheral hardware 30.
The supply of the operation clock signal 101 to 0 is stopped. As a result, the CPU 20 stops operating, and the peripheral hardware (A) 31 and (B) 3 in the peripheral hardware 30.
Only 2, (C) 33, and (D) 34 operate.

Next, the operation when the CPU 20 executes the STOP instruction will be described.

When the CPU 20 reads the program from the program section 10 and decodes the STOP instruction by the decoder section 21 in the same manner as when the HALT instruction is executed, the control section 22 informs the clock control section 23 of the clock control signal 1
04 is output. Upon receiving the clock control signal 104, the clock control unit 23 stops the clock of the entire microcomputer, that is, the operation clock signals 101 and 102.

As a result, the entire microcomputer is stopped.

Next, the actual use of the HALT and STOP instructions will be described.

The HALT instruction is used to stop the CPU 20 and reduce power consumption when the CPU 20 does not need to operate.

For example, when the CPU 20 is executing a program and the next program processing cannot be performed until the peripheral hardware (A) 31 receives the data received from the external terminal 35, the CPU 20 determines that the peripheral hardware (A) 31
Waits until data is received. In such a case, if HALT instruction is described in the program, CP
The operation of U20 is stopped and put in a waiting state.

At this time, since the operation clock signal 102 input to the peripheral hardware 30 continues to be output, the peripheral hardware (A) 31, (B) 32, (C) 33 and (D) 34 are in the operating state. Yes, the CPU 20 stops the HALT after the peripheral hardware (A) 31 completes the data reception.
The state is released, data is received from the peripheral hardware (A) 31, and the following processing is performed.

The STOP instruction stops the operation of the microcomputer and suppresses the power consumption when the microcomputer completes a series of operations and no processing is required until the next external processing comes. It is effective in some cases.

In this case, the peripheral hardware 30 and the CPU
The operation of 20 stops completely.

[0020]

As described above,
In the conventional microcomputer, it is possible to stop the operation of the CPU by issuing the HALT instruction or stop the operation of the entire microcomputer by the STOP instruction, but only operate or stop specific peripheral hardware. Therefore, there is a problem that the operating clock signal is supplied to unnecessary peripheral hardware, and the power consumption of the entire system cannot be optimized.

If the HALT instruction is not described in the program, the power consumption cannot be reduced. Therefore, when the operation relationship of each hardware becomes complicated like the control program, it depends on the operation status of the hardware. There is a problem that power control becomes more difficult.

An object of the present invention is to solve the above-mentioned problems by using the HALT instruction and the STOP instruction,
An object of the present invention is to provide a microcomputer in which supply of an operation clock signal of unnecessary hardware is stopped to further reduce power consumption.

[0023]

According to the present invention, there is provided a central processing unit having a plurality of peripheral hardware and clock control means for controlling the supply of the operation clock signal including the operation clock signal to the plurality of peripheral hardware. In the microcomputer provided with, each of the peripheral hardware stores an operation designation storage unit that stores data designating the operation of the peripheral hardware in advance and outputs a predetermined signal, and the peripheral hardware from the central processing unit to the peripheral hardware. Means for detecting the data access of the device, and an individual for controlling the supply of the operation clock signal supplied from the central processing unit to its own peripheral hardware according to the output signal of the operation designation storage means and the output signal of the detection means. And a clock control means.

[0024]

In the operation designation storage means, data for designating whether or not the peripheral hardware operates is previously written via the CPU. For example, in the case of operation, "1" is inactive. "0" is output. Also,
The detection unit detects data access from the CPU to the peripheral hardware, and outputs “1” if detected and outputs “0” otherwise. Then, the individual clock control means supplies the operation clock signal from the CPU to its own peripheral hardware to perform the operation when the outputs of the operation designation storage means and the detection means are both "1", and otherwise, for example. In this case, the supply of the operation clock signal is stopped to stop the operation.

As a result, it is possible to stop the operation of unnecessary peripheral hardware without using the HALT instruction and the STOP instruction, and it is possible to further reduce the power consumption.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the essential parts of an embodiment of the present invention.

The present embodiment comprises the CPU 20 shown in FIG. 3 and a program section 10 in which a program is stored, peripheral hardware 40, and a bus 60 for exchanging data between the CPU 20 and peripheral hardware 40. ing.

The peripheral hardware 40 has a CP
Operation clock signal 102 from U20, and RD signal 105 and WR signal 1 which are control signals for data read / write.
06 and are given.

The peripheral hardware 40 also includes peripheral hardware (A) 41, peripheral hardware (B) 42, peripheral hardware (C) 43, and peripheral hardware (D) 44.

The peripheral hardware (A) 41 is
An address decoder 51 which decodes an address given from the CPU 20, an OR and gate 52,
A counter 53 that counts the operation clock signal 102
And the overflow signal 108 output from the counter 53
, Operation designation register 54, or and gate 55
And a peripheral hardware core 56 and an operation clock signal 109 to the peripheral hardware core 56.

Further, other peripheral hardware (B) 42,
(C) 43 and (D) 44 also have the same configuration as (A) 41.

The feature of the present invention is that peripheral hardware (A) 41, (B) 42, (C) in FIG.
Reference numerals 43 and (D) 44 respectively indicate an operation designation register 54 as an operation designation storage unit for storing data designating the operation of the peripheral hardware in advance and outputting a predetermined signal, and to the peripheral hardware from the CPU 20. Of the operation clock signal 102 from the CPU 20 to its own peripheral hardware in accordance with the address decoder 51 and the OR-and-gate 52 as the detecting means for detecting the data access of the CPU, and the output signal of the operation designation register 54 and the output signal of the OR-and gate 52. Counter 53 and OR and gate 5 as individual clock control means for controlling supply
5 and.

Next, the operation of each part of the peripheral hardware (A) 41 in this embodiment will be described with reference to the flow chart shown in FIG.

First, the case where the own peripheral hardware (A) 41 is accessed will be described.

The address decoder 51 decodes the address that the CPU 20 puts on the bus 60 for data access (step S1), and judges whether the given address corresponds to the peripheral hardware (A) 41. (Step S2).

The OR-and-gate 52 calculates the logical product of the output of the address decoder 51 and the logical sum of the RD signal 105 and the WR signal 106 output from the CPU 20, and the CPU 20
Becomes active “1” when the peripheral hardware (A) 41 is accessed. And or and gate 52
Is output as a reset signal 107, which is input to the counter 53 (step S3).

The counter 53 counts the clock signal 102 and is reset when the reset signal 107 becomes active "1", and sets the overflow signal 108 to "0" (step S4). Then, when the counter 53 overflows, the overflow signal 108 becomes active “1” and is input to the OR and gate 55.

On the other hand, the operation designation register 54 is a register for designating permission or prohibition of the power consumption reducing operation of the peripheral hardware (A) 41, and can be written by the CPU 20. The OR-and-gate 55 stops the operation clock signal 109 by setting it to "0" when both the operation designation register 54 and the overflow signal 108 become "1", and otherwise, the operation clock signal 10
9 is set to "1" and it is transmitted to the peripheral hardware core 56 (step S5).

The peripheral hardware core 56 is the functional portion of the peripheral hardware (A) 41, has the same configuration as the peripheral hardware (A) 31 shown in the conventional example, and when the operation clock signal 109 is "1". The operation is performed (step S6).

Next, a case where the peripheral hardware (A) 41 performs a power consumption reducing operation when the CPU 20 executes a program will be described.

In this description, in order to cause the peripheral hardware (A) 41 to reduce the power consumption, the value "1" is written in the operation designation register 54 at the time of initialization prior to the execution of the program. It is assumed to be rare.

While the CPU 20 is executing the program of the program section 10, if the CPU 20 at least accesses the peripheral hardware (A) 41, the peripheral hardware (A) 41 is operating and normally operates. A clock must be supplied to operate.

That is, at this time, each time the CPU 20 accesses the peripheral hardware (A) 41, the counter 53
Is reset and the overflow signal 108 is
The operation clock signal 109 is maintained at “0” and is supplied to the peripheral hardware core 56.

However, when the execution program of the CPU 20 does not use the peripheral hardware (A) 41 and does not access the peripheral hardware (A) 41 (step S2), the counter 53 indicates that the reset signal 107 is "0". (Step S7), the count operation is continued without being reset, and when the bit length of the counter is fully counted, the overflow signal 108 is activated to "1" (step S8).

When the overflow signal 108 becomes active "1", since the value of the operation designation register 54 is "1", the operation clock signal 109 becomes "0" and stops (step S9), and the peripheral hardware (A ) 41
Stops its operation (step S10).

If the CPU 20 accesses the peripheral hardware (A) 41 again, the counter 53 is reset and the operation clock signal 109 can be supplied with the clock again.

If the usage status of the hardware cannot be determined simply by the CPU 20 accessing or not accessing, the above-mentioned operation designation register 5
By setting "0" in 4, it is possible to prohibit the clock stop operation.

Further, the counter 53 may be of a presettable type.

In this case, although the scale of the hardware is slightly larger than that described above, the time for determining the operation stop of each peripheral hardware can be arbitrarily set for each hardware or each application. Because you can
It is possible to further reduce power consumption.

[0051]

As described above, the present invention makes it possible to independently stop each peripheral hardware in addition to the CPU in a power consumption reduction apparatus for a microcomputer, and without setting by software. Since each peripheral hardware itself can automatically reduce the power consumption depending on the frequency of access, the system clock can be provided to the minimum necessary hardware and the system power consumption can be minimized. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart showing the operation.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 10 Program Unit 20 Central Processing Unit (CPU) 21 Decoder Unit 22 Control Unit 23 Clock Control Unit 30, 40 Peripheral Hardware 31, 41 Peripheral Hardware (A) 32, 42 Peripheral Hardware (B) 33, 43 Peripheral Hardware (C) 34, 44 Peripheral hardware (D) 35 External terminal 51 Address decoder 52, 55 OR and gate 53 Counter 54 Operation designation register 56 Peripheral hardware core 60 Bus 101, 102, 109 Operation clock signal 103, 104 Clock control Signal 105 RD signal 106 WR signal 107 Reset signal 108 Overflow signal S1 to S10 steps

Claims (1)

[Claims] 1. A microcomputer comprising: a plurality of peripheral hardware; and a central processing unit having clock control means for controlling supply of an operation clock signal including an operation clock signal to the plurality of peripheral hardware. Peripheral hardware includes an operation designation storage unit that stores data that specifies the operation of the peripheral hardware in advance and outputs a predetermined signal, and a detection unit that detects data access from the central processing unit to the peripheral hardware. And an individual clock control means for controlling the supply of the operation clock signal supplied from the central processing unit to its own peripheral hardware according to the output signal of the operation designation storage means and the output signal of the detection means. Characteristic microcomputer.