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JPH0529197A - Method of forming resist pattern - Google Patents

Method of forming resist pattern

Info

Publication number
JPH0529197A
JPH0529197A JP3182653A JP18265391A JPH0529197A JP H0529197 A JPH0529197 A JP H0529197A JP 3182653 A JP3182653 A JP 3182653A JP 18265391 A JP18265391 A JP 18265391A JP H0529197 A JPH0529197 A JP H0529197A
Authority
JP
Japan
Prior art keywords
wavelength
resist
exposure
pattern
entire surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3182653A
Other languages
Japanese (ja)
Other versions
JP3130335B2 (en
Inventor
Tetsuya Maeda
哲也 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP03182653A priority Critical patent/JP3130335B2/en
Publication of JPH0529197A publication Critical patent/JPH0529197A/en
Application granted granted Critical
Publication of JP3130335B2 publication Critical patent/JP3130335B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

PURPOSE:To form a fine resist pattern by forming an uneven part on a surface of a resist, so forming a step of the resist surface that a phase of an exposure light wavelength is just deviated by a special wavelength, then exposing the entire surface with a parallel light ray by an exposure unit and developing it. CONSTITUTION:A desired base board 1 is coated with positive type photoresist 2, and a desired pattern is transferred from a mask 20 by a contraction exposure unit, etc. It is developed to form a step on the surface of the resist. Then, the entire surface is exposed with a parallel light ray having a wavelength lambda. In this case, the step of the resist surface is so set that the phase of the exposure wavelength is just deviated by 1/2 wavelength. Then, when it is developed, the resist so remains as to be disposed along a line of the step of the resist surface, and a very fine line pattern can be formed. Thus, a patterning of a finer width or space than the wavelength at the time of entire surface exposure, i.e., the wavelength of a single wavelength parallel beam which can be formed, can be performed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】フォトリソグラフィを用いたレジ
ストパターンの形成方法に関する。
TECHNICAL FIELD The present invention relates to a method for forming a resist pattern using photolithography.

【0002】[0002]

【従来の技術】従来のフォトリソグラフィ工程を以下に
示す。図4(a)のように、所望の下地の上に、例えば
ポジ型フォトレジスト2を塗布し、縮小露光装置等でマ
スク30上の所望のパターンを露光する。次に、現像を
行うことにより、図4(b)のようなレジストパターン
を得ることができる。このフォトレジストパターンをマ
スクにし、インプラ工程、またはエッチング工程等を行
うことにより、半導体装置を製造していた。
2. Description of the Related Art A conventional photolithography process is shown below. As shown in FIG. 4A, for example, a positive photoresist 2 is applied on a desired base, and a desired pattern on the mask 30 is exposed by a reduction exposure device or the like. Next, by developing, a resist pattern as shown in FIG. 4B can be obtained. A semiconductor device is manufactured by using the photoresist pattern as a mask and performing an implantation process, an etching process, or the like.

【0003】[0003]

【発明が解決しようとする課題】より細い線幅を解像し
ようとすると、より高NAの(開口数の大きな)露光機
を用いなければならなくなり、露光波長レベルのピッチ
の線幅は解像することができなかった。
In order to resolve a narrower line width, an exposure machine with a higher NA (large numerical aperture) must be used, and the line width of the exposure wavelength level pitch is resolved. I couldn't.

【0004】[0004]

【課題を解決するための手段】レジスト表面部に凹凸を
作る。なお、このときレジスト表面段差を、露光波長の
位相がちょうど1/2波長ずれるようにする。その後、
露光機で平行光線を全面露光し、現像するようにした。
[Means for Solving the Problem] Asperity is formed on a resist surface portion. At this time, the step of the resist surface is set so that the phase of the exposure wavelength is shifted by exactly 1/2 wavelength. afterwards,
A parallel light beam was exposed on the entire surface with an exposure machine and developed.

【0005】[0005]

【作用】上記のように製造すれば、凸部と凹部とで露光
時位相が変化する。従って、段差部で位相が異なった光
が干渉し、段差部の下には光が注入されない。この段差
部を中心としてある光強度分布が形成される。これを現
像すればマスクパターンよりさらに微細なレジストパタ
ーンを形成することができる。
When manufactured as described above, the phase at the time of exposure changes between the convex portion and the concave portion. Therefore, light having different phases interferes with each other at the step portion, and light is not injected below the step portion. A certain light intensity distribution is formed around this step. By developing this, a resist pattern finer than the mask pattern can be formed.

【0006】[0006]

【実施例】以下に、本発明の第1実施例を図面に基づい
て説明する。図1(a)のように所望の下地基板1の上
に、ポジ形フォトレジスト2を塗布し、縮小露光装置等
で所望のパターンをマスク20から転写する。そして、
現像を行い、図1(b)のようにレジスト表面に段差が
つく。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1A, a positive photoresist 2 is applied on a desired base substrate 1 and a desired pattern is transferred from a mask 20 by a reduction exposure device or the like. And
Development is performed to form a step on the resist surface as shown in FIG.

【0007】次に全面を波長λの平行光線で露光するわ
けであるが、このとき、段差上部を通過した光と、段差
下部を通過した光とでは、レジストと露光雰囲気(例え
ば大気等)の屈折率の差により、位相差が生じる。この
位相差はk′λ−kλで表される。(ここでkは、露光
雰囲気中における波数であり、k′はフォトレジスト膜
中の波数である。)この位相差をπとするため、 k′λ−kλ=k(αλ−λ)=(R+0.5)λ ……… (1) (R:任意の整数 α:フォトレジストの露光雰囲気に
対する屈折率)を満たすように、k=(R+0.5)/
(α−1)と設定する。すると、段差部上部と下部の膜
厚差Tは T=kλ={(R+0.5)/(α−1)}λ ……… (2) を満たすように、段差を形成すればよいことがわかる。
この段差量とするため、段差形成時の露光量及び、現像
液濃度、現像時間等を調整する。なお、最終的なレジス
ト形状をより精度良く形成するため、上記段差を形成す
るための露光量は、後に全面を波長λの平行光線で露光
するときの露光量にくらべ、少なく設定する。また、段
差上部と下部の膜厚差Tは、段差形成時の露光時及び、
後の全面の露光時の透過性及び、解像、焦点深度等の理
由により、薄い方が望ましい。また、一般的にフォトレ
ジストの屈折率αは、1<αであるため、R=0のと
き、上記膜厚差Tは最も薄くすることが可能であり、そ
の時の膜厚をT0 とすると、 T0 =λ/{2(α−1)}となる。
Next, the entire surface is exposed by parallel rays having a wavelength λ. At this time, the light passing through the upper part of the step and the light passing through the lower part of the step have a resist and an exposure atmosphere (for example, the atmosphere). A phase difference occurs due to the difference in refractive index. This phase difference is represented by k'λ-kλ. (Here, k is the wave number in the exposure atmosphere, and k ′ is the wave number in the photoresist film.) Since this phase difference is π, k′λ−kλ = k (αλ−λ) = ( R + 0.5) λ (1) (R: Arbitrary integer α: Refractive index of photoresist against exposure atmosphere) k = (R + 0.5) /
Set it to (α-1). Then, the film thickness difference T between the upper part and the lower part of the step portion may be formed so that the step difference is satisfied by T = kλ = {(R + 0.5) / (α-1)} λ (2) Recognize.
In order to obtain this step amount, the exposure amount, the developer concentration, the developing time, etc. when forming the step are adjusted. In order to more accurately form the final resist shape, the exposure amount for forming the step is set to be smaller than the exposure amount when the entire surface is exposed later with parallel rays of wavelength λ. Further, the film thickness difference T between the upper part and the lower part of the step is
It is preferable that the thickness is thin due to reasons such as the transparency at the time of exposure of the entire surface afterwards, resolution, and depth of focus. Further, since the refractive index α of the photoresist is generally 1 <α, the thickness difference T can be minimized when R = 0, and the thickness at that time is T 0. , T 0 = λ / {2 (α-1)}.

【0008】上記(2)式を満たすような膜厚、例えば
0 に膜厚差がなるように、段差を形成し、次に図1
(c)に示すように2度目の露光を波長λの平行光線を
用いて、全面に行う。すると、段差上部と下部とでは、
πだけ位相がずれるため、段差部の下には光が注入され
ない。従って、後に現像を行うと図1(d)に示すよう
にレジスト表面段差部分のラインにそうようにレジスト
が残り、非常に微細なラインパターンを形成することが
できる。
A step is formed so that there is a film thickness difference that satisfies the above expression (2), for example, T 0 , and then FIG.
As shown in (c), the second exposure is performed on the entire surface by using parallel rays having a wavelength λ. Then, at the top and bottom of the step,
Since the phase is shifted by π, light is not injected under the step. Therefore, when the development is performed later, the resist remains on the lines of the resist surface step portion as shown in FIG. 1D, and a very fine line pattern can be formed.

【0009】以下に、本発明の第2実施例を図面に基づ
いて説明する。図2(a)のように、所望の下地基板1
の上にネガ形フォトレジスト3を塗布し、縮小露光装置
等で第1実施例と同様に露光、現像する。このとき、図
2(b)のような形状となるが、このときの段差T1
ネガ形フォトレジストの屈折率をβとすると、 T1 =λ/{2(β−1)}となるように、一度目の露
光、現像条件を設定する。
A second embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 2A, a desired base substrate 1
A negative photoresist 3 is coated on the above, and exposed and developed in the same manner as in the first embodiment using a reduction exposure device or the like. At this time, the shape is as shown in FIG. 2B, but the step T 1 at this time is T 1 = λ / {2 (β-1)}, where β is the refractive index of the negative photoresist. In this way, the first exposure and development conditions are set.

【0010】次に、図2(c)に示すように、2度目の
露光を全面に行う。後に現像を行うと図2(d)に示す
ようにレジストが残り、非常に微細なスペースパターン
を形成することができる。次に、本発明の第3実施例を
図面に基づいて説明する。所望の下地の上にネガ形フォ
トレジストを塗布し、縮小露光装置等で図3(a)に示
したようなパターンを露光する。このとき、露光量は第
2実施例の一度目の露光量の1/2に設定する。
Next, as shown in FIG. 2C, a second exposure is performed on the entire surface. When development is performed later, the resist remains as shown in FIG. 2D, and a very fine space pattern can be formed. Next, a third embodiment of the present invention will be described with reference to the drawings. A negative photoresist is applied on a desired underlayer, and a pattern as shown in FIG. 3A is exposed by a reduction exposure device or the like. At this time, the exposure amount is set to 1/2 of the first exposure amount of the second embodiment.

【0011】次に、図3(b)に示したようなパターン
を露光する。このとき、露光量は第2実施例の一度目の
露光量の1/2に設定する。そして、第2実施例の一度
目の現像条件と同様の現像条件で、現像を行う。する
と、図3(c)に示すように格子状にレジスト段差が形
成され、その交点を囲むレジスト段差の最高部領域9
と、段差の最低部領域10の段差がλ/{2(β−
1)}となる。また、このとき、中段部領域11は、最
高部領域9及び最低部領域10と、十分に段差があるこ
とが必要であり、特に、最高部と最低部の高さの真中に
なっていると、より円形に近いパターンを形成しやす
い。
Next, the pattern as shown in FIG. 3B is exposed. At this time, the exposure amount is set to 1/2 of the first exposure amount of the second embodiment. Then, the development is performed under the same development conditions as the first development conditions of the second embodiment. Then, as shown in FIG. 3C, a resist step is formed in a grid pattern, and the highest step region 9 of the resist step surrounding the intersection is formed.
And the step of the lowest step region 10 is λ / {2 (β-
1)}. Further, at this time, the middle part region 11 needs to have a sufficient level difference with the highest part region 9 and the lowest part region 10, and in particular, it is in the middle of the heights of the highest part and the lowest part. , It is easy to form a more circular pattern.

【0012】次に、波長λの平行光線で全面を露光す
る。その後、現像を行うと、図3(d)に示すように、
ネガレジストにホールパターン12が開口し、非常に小
さなホールパターンを形成することができる。
Next, the entire surface is exposed with parallel rays of wavelength λ. After that, when development is performed, as shown in FIG.
The hole pattern 12 is opened in the negative resist, and a very small hole pattern can be formed.

【0013】[0013]

【発明の効果】この発明は、以上説明したように、所望
の下地の上に塗布されたレジストを用い位相をシフトさ
せ、露光するため、光の波長程度の非常に微細なパター
ンを形成することが可能である。そして、レジスト表面
に段差をつけるための露光では、レジスト表面のみで結
像すれば良いため、焦点深度が要求されず、また、全面
露光時は平行な短波長光線であれば、高NAのレンズを
介した光を使用しなくてもよい為、全体として段差部で
も非常に微細なパターンを形成することが可能である。
さらに、ネガレジスト、ポジレジストの使い分け、およ
び、表面段差を2段とすることなどにより、微細なスペ
ースパターンや、ホールパターンなど、複雑なパターン
を形成することができる。また、短波長紫外線に対して
透過率の高いレジストを用いることにより、高NAレン
ズが作成困難な波長帯でも平行光線さえ作成できれば光
波の干渉により、光強度のコントラストを作るため、波
長よりも細い線幅またはスペースのパターニングを行う
ことが可能であるという効果がある。
As described above, according to the present invention, a resist coated on a desired underlayer is used for phase shift and exposure, so that a very fine pattern having a wavelength of light is formed. Is possible. Further, in the exposure for forming a step on the resist surface, since it is sufficient to form an image only on the resist surface, a depth of focus is not required, and when the entire surface is exposed, if the parallel short-wavelength rays are used, a lens having a high NA is used. Since it is not necessary to use the light that has passed through, it is possible to form a very fine pattern even in the step portion as a whole.
Further, by using the negative resist and the positive resist properly, and by forming the surface step in two steps, it is possible to form a complicated pattern such as a fine space pattern or a hole pattern. Further, by using a resist having a high transmittance for short-wavelength ultraviolet rays, if a parallel NA ray can be created even in a wavelength band in which a high NA lens is difficult to create, interference of light waves creates a contrast of light intensity, which is smaller than the wavelength. There is an effect that it is possible to pattern the line width or the space.

【図面の簡単な説明】[Brief description of drawings]

【図1】(a)〜(d)は第1実施例の半導体装置の製
造方法を示す工程順断面図である。
1A to 1D are cross-sectional views in order of the processes, showing a method for manufacturing a semiconductor device according to a first embodiment.

【図2】(a)〜(d)は第2実施例の半導体装置の製
造方法を示す工程順断面図である。
2A to 2D are cross-sectional views in order of the steps, showing a method for manufacturing a semiconductor device according to a second embodiment.

【図3】(a)〜(d)は第3実施例の半導体装置の製
造方法を示す工程順平面図である。
3A to 3D are plan views in order of the steps, showing the method for manufacturing the semiconductor device according to the third embodiment.

【図4】(a),(b)は従来の半導体装置の製造方法
を示す工程順断面図である。
4A and 4B are cross-sectional views in order of the processes, showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 下地基板 2 ポジ形フォトレジスト 3,4 ネガ形フォトレジスト 5,7 露光領域 6,8 非常光領域 9 段差の最高部領域 10 段差の最低部領域 11 中段部領域 12 ホールパターン 1 Base Substrate 2 Positive Photoresist 3,4 Negative Photoresist 5,7 Exposure Area 6,8 Emergency Light Area 9 Highest Step Area 10 Lower Step Area 11 Middle Step Area 12 Hole Pattern

Claims (1)

【特許請求の範囲】 【請求項1】 半導体基板上に、ポジ形又はネジ形のフ
ォトレジストを塗布する工程と、前記フォトレジストを
露光現像し、フォトレジスト表面に所望の段差を形成す
る工程と、全面を単波長の平行光線で露光し、現像する
工程とからなり、前記段差部の上部と下部との膜厚差
は、前記単波長の平行光線での露光時、前記フォトレジ
ストのある部分とない部分とで、前記段差部下部面に入
射時の前記平行光線の位相が半波長の奇数倍ずれるよう
な厚みであることを特徴とするフォトリソグラフィを用
いたレジストパターンの形成方法。
Claim: What is claimed is: 1. A step of applying a positive or screw photoresist on a semiconductor substrate, and a step of exposing and developing the photoresist to form a desired step on the photoresist surface. The step of exposing the entire surface to a parallel light beam of a single wavelength and developing, the difference in film thickness between the upper part and the lower part of the step portion is caused by the parallel light beam of a single wavelength when exposed to the photoresist. A method of forming a resist pattern using photolithography, characterized in that the thickness of the parallel light beam when incident on the lower surface of the stepped portion is shifted by an odd multiple of a half wavelength at the non-existing portion.
JP03182653A 1991-07-23 1991-07-23 Method of forming resist pattern Expired - Lifetime JP3130335B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03182653A JP3130335B2 (en) 1991-07-23 1991-07-23 Method of forming resist pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03182653A JP3130335B2 (en) 1991-07-23 1991-07-23 Method of forming resist pattern

Publications (2)

Publication Number Publication Date
JPH0529197A true JPH0529197A (en) 1993-02-05
JP3130335B2 JP3130335B2 (en) 2001-01-31

Family

ID=16122081

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03182653A Expired - Lifetime JP3130335B2 (en) 1991-07-23 1991-07-23 Method of forming resist pattern

Country Status (1)

Country Link
JP (1) JP3130335B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6841732B2 (en) 2000-10-25 2005-01-11 Nec Lcd Technologies, Ltd. Protection structure of a circuit board and method for manufacturing the same
US11088083B2 (en) 2018-06-29 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure
US11139341B2 (en) 2018-06-18 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Protection of MRAM from external magnetic field using magnetic-field-shielding structure

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7959855B2 (en) 2006-10-19 2011-06-14 Heru Budihartono White precious metal alloy

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6841732B2 (en) 2000-10-25 2005-01-11 Nec Lcd Technologies, Ltd. Protection structure of a circuit board and method for manufacturing the same
US11139341B2 (en) 2018-06-18 2021-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Protection of MRAM from external magnetic field using magnetic-field-shielding structure
US11088083B2 (en) 2018-06-29 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure
US11715702B2 (en) 2018-06-29 2023-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure

Also Published As

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