JPH05291888A - Oscillator - Google Patents

Abstract

PURPOSE:To make the oscillating period and frequency stable and to attain the oscillator with small power consumption by providing a forcing means which forces a potential at connecting points among plural inverting means connected in a ring to a potential to stop the oscillation simultaneously in response to a control signal commanding the stop of the oscillation to the oscillator. CONSTITUTION:MOS transistors(TRs) 50, 60, 70 force a potential at nodes N1, N2, N3 respectively to be a high level, a low level and a high level in response to a trailing of a control signal Ton in the ring oscillator independently of an output potential of an inverter of a pre-stage of each node. Thus, each of the nodes N1-N3 is fixed momentarily to a position (initial potential) to be taken in the inoperation state of the ring oscillator. That is, all the nodes N1, N2, N3 are fixed to the initial potential almost simultaneously and momentarily in response to the trailing of the control signal Ton.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an oscillator, and more particularly to an oscillator having a structure in which a plurality of inverters are connected in a ring.

[0002]

2. Description of the Related Art A DRAM (Dynamic Random Access Memory) has a so-called self-refresh function of rewriting data in each memory cell at regular intervals in order to prevent the stored data in the memory cell from disappearing over time. In order to realize this function, the DRAM is provided with a ring oscillator as an oscillator that generates a signal whose level is switched in a certain basic cycle (several μs). Further, in many semiconductor integrated circuit devices including semiconductor memory devices such as DRAMs, a ring oscillator is used as one of the circuits forming a substrate bias circuit for biasing a semiconductor substrate to a predetermined potential. The substrate bias generation circuit is configured to operate the charge pump circuit with the output signal of the ring oscillator.

A ring oscillator is an inverter or a NAN.
It is a self-oscillation type oscillator that generates a signal whose level is inverted at a constant period by connecting a plurality of inverters such as D gates in a ring shape.

FIG. 7 is a circuit diagram showing a general structure of a conventional ring oscillator used in a semiconductor memory device or the like.

FIG. 8 is a timing chart for explaining the operation of the ring oscillator of FIG.

The structure and operation of the conventional ring oscillator will be described below with reference to FIGS. 7 and 8.

FIG. 7 illustrates a ring oscillator composed of three inverters. As shown in FIG. 7, the conventional ring oscillator includes a plurality of inverters 1
It includes 0, 20 and a 2-input NAND gate 30. The plurality of inverters 10 and 20 are connected in series with each other, and the output signal of the final stage inverter 20 is supplied to one input terminal of the NAND gate 30. NAND gate 3
The other input terminal of 0 is supplied with a control signal Ton for instructing whether the ring oscillator is in an operating state or a non-operating state. The output signal of the NAND gate 30 is supplied to the input terminal of the first-stage inverter 10.

The signal appearing at any of the connection points N1 to N3 between these inverters 10, 20, 30 is used as the output signal of this ring oscillator.

The control signal Ton is at a high level during the period in which the ring oscillator should oscillate, that is, during the period in which the level of the output signal from the ring oscillator should be inverted at a constant cycle, and the period during which the ring oscillator should not oscillate, That is, it is supplied from the outside of this ring oscillator so that the level of the output signal of this ring oscillator is at a low level during the period when it should be kept constant.

Control signal Ton is, for example, in a semiconductor memory device such as a DRAM, generated by a timing generator or the like for controlling the operation timing of the main circuits (memory cell array, address buffer, address decoder, etc.) of the semiconductor memory device. It

When the ring oscillator is oscillating,
This ring oscillator is said to be in operation, and when the ring oscillator is not oscillating, this ring oscillator is in operation.

If the control signal Ton (FIG. 8A) is at low level, the output potential of the NAND gate 30 (node N
The potential of 1 becomes high level regardless of the potential of the node N3 (output potential of the inverter 20). Therefore,
Period T1 during which the control signal Ton is fixed at low level
, The potential of the node N1, the potential of the node N2, and the potential of the node N3 are fixed at high level, low level, and high level, respectively, as shown in FIGS. 8 (b), (c), and (d). To be done. That is, this ring oscillator does not oscillate.

On the contrary, when the control signal Ton is at the high level, the NAND gate 30 operates as an inverter, so that the potential of the logic level opposite to the logic level of the potential of the node N3 appears at the node N1. Therefore, when the control signal Ton switches from the low level to the high level as shown in FIG. 8A, first, the potential of the node N1 is delayed from the rising of the control signal Ton by the signal delay time of the NAND gate 30. Fall to low level.

The potential of the node N2 rises to a high level by the inverting operation of the inverter 10 with a delay of the signal delay time in the inverter 10 from the fall of the potential of the node N1.

The potential of the node N3 is higher than that of the potential of the node N2 due to the inverting operation of the inverter 20.
Further, it falls to the low level with a delay of the signal delay time in inverter 20.

When the potential of the node N3 is switched to the low level, the inverting operation of the NAND gate 30 causes the node N3.
The potential of 1 switches to high level. That is, the node N1
Is higher than the fall of the potential of the node N3.
It goes high after a delay of the signal delay time in the ND gate 30.

The change in the potential of node N1 causes the potentials of nodes N2 and N3 to be changed again by inverters 10 and 20.

In this way, the change of the potential of each of the nodes N1 to N3 receives the potential as an input, and the inverters 10 to 3 are received.
The circuit operation in which the signal is transmitted to the node at the next stage with a delay of the signal delay time at 0 is repeated. As a result, the logic levels of the potentials of the nodes N1 to N3 are set to the control signal Ton.
In the period T2 in which the signal is at the high level, the signal is inverted at every time corresponding to the sum of the signal delay time in the NAND gate 10, the signal delay time in the inverter 20, and the signal delay time in the NAND gate 30. That is,
This ring oscillator oscillates.

The longer the signal delay time of each inverter 10 to 30, the more the logic levels of the potentials of the nodes N1 to N3 are switched at each longer time period. That is, the oscillation cycle of the ring oscillator becomes longer as a circuit having a longer signal delay time is used as the inverter.

When the control signal Ton is fixed to the low level again (falling of the control signal Ton shown by the solid line in FIG. 8), the output potential of the NAND gate 30 becomes the node N.
The low-level potential is output regardless of the potential change of 3. Therefore, in the period T3 in which the control signal Ton is fixed to the low level again, the potential of the node N1 is no longer in the low level in response to the rising RISE of the potential of the node N3, but is fixed to the high level. Therefore, the potential of the node N2 and the potential of the node N3 are fixed to the low level and the high level in the period T3, respectively. That is, the oscillation of this ring oscillator is stopped.

When the control signal Ton falls, the node N1
When the potential of the control signal T is low level (indicated by the broken line in FIG. 8), the potential of the node N1 is fixed to the high level in response to the fall of the control signal Ton.
When on is set to the high level for a certain period and then fixed to the low level, the potentials of the nodes N1 and N3 are fixed to the high level, the potential of the node N2 is fixed to the low level, and the oscillation of this ring oscillator is stopped. To be done.

[0022]

As described above, in the conventional ring oscillator, the switching from the operating state to the non-operating state and the switching from the non-operating state to the operating state are performed among the inverters forming the ring oscillator. One with 2 inputs NA
Like an ND gate, it operates as an inverter that inverts the potential of the other input terminal only when the potential of the one input terminal is at a certain logic level, and otherwise, regardless of the potential of the other input terminal. This is realized by configuring the logic gate that operates so as to output a constant potential and forcing the output potential of one inverter to a constant logic level, or by releasing this force.

Therefore, the conventional ring oscillator has the following problems. FIG. 9 shows the potential inversion of the output signal of the ring oscillator when the potential changes of the nodes N1 to N3 when the ring oscillator of FIG. 7 is brought into the operating state again immediately after being switched from the operating state to the non-operating state. It is a timing chart figure shown about the case where a cycle (oscillation cycle) is short.

Referring to FIGS. 7 and 9, control signal To
n is fixed to the low level for a long period of time, whereby the control signal Ton is switched to the high level while the potentials of the nodes N1, N2, and N3 are at the high level, the low level, and the high level, respectively. When the ring oscillator enters the operating state (the first rise in FIG. 9A), the node N is activated by the circuit operation as described above.
The potentials of 1, N2, and N3 are shown in FIG.
As shown in (c) and (d), a constant period (1 /
Level inversion starts at f ₀ ).

Next, the control signal Ton (FIG. 9A) is changed to
-The ring oscillator has stopped operating after
The oscillation cycle of this ring oscillator (1
/ F ₀) Is sufficiently shorter than
Then the control signal Ton rises to the high level again and
Suppose the Ning Oscillator is brought back into operation.

In response to the fall of the control signal Ton, the potentials of the nodes N1, N2 and N3 are forced to the high level, the low level and the high level, respectively, as shown by the arrows in FIG.

When the oscillation frequency (f ₀ ) of this ring oscillator is high, that is, each inverter 10, 20, 30
If the signal delay time at the node is short, the period τ1 from the time when the control signal Ton becomes low level until the potential of the node N1 is fixed at high level, and the time when the control signal Ton becomes low level, the potential of the node N2 becomes low. Of the control signal Ton from the low level of the control signal Ton until the potential of the node N3 is fixed to the high level. Is equal to or less than the length of the period τ4 from when the signal becomes low level until it becomes high level again. Therefore, when the control signal Ton rises (indicated by a broken line in the figure), the potentials of the nodes N1, N2, and N3 are high and low, which are logical levels that the ring oscillator should be in when it is inactive. , And fixed to high level.

Therefore, in response to the second rise of the control signal Ton in FIG. 9, the potentials of the nodes N1, N2, and N3 respectively have the same cycle () as in the first operation period T4 of this ring oscillator. The level inversion starts at 1 / f ₀ ).

As described above, when the oscillation period of the ring oscillator is sufficiently short, even if the ring oscillator is returned from the operating state to the non-operating state and then returned to the operating state again, the oscillation period and frequency of the ring oscillator are also reduced. Is the original oscillation period (1 / f ₀ ) and frequency f ₀ , where
The “original oscillation cycle / frequency” means the oscillation cycle (1 / f ₀ ) / frequency f ₀ of the ring oscillator when it is put into the operating state after being left in the non-operating state for a long time.

FIG. 10 shows changes in the potentials of the nodes N1 to N3 when the ring oscillator shown in FIG. 7 is returned to the operating state immediately after being brought from the operating state to the non-operating state. It is a timing chart figure shown about the case where is low.

Referring to FIGS. 7 and 10, control signal T
When on (FIG. 10 (a)) is fixed to the low level for a long time and then started up, the potentials of the nodes N1, N2, and N3 are changed to those of FIGS. 10 (b), (c), and (d), respectively. As shown, the level inversion starts at a constant period longer than that shown in FIG.

Next, when the control signal Ton goes high again immediately after the control signal Ton goes low once to deactivate the ring oscillator, the ring oscillator is returned to the working state. Assume

When the control signal Ton becomes low level, as described above, the potential of the node N1 is first forced to high level, and in response thereto, the potential of the node N2 is forced to low level and further responds to this. Thus, the potential of the node N3 is forced to the high level.

However, since the oscillation frequency of this ring oscillator is low, that is, each of the inverters 10, 20,
Since the signal delay time at 30 is long, the control signal Ton
From the low level until the potential of the node N1 is fixed to the high level in response to this, the length of the period τ1,
The length of the period τ2 from when the signal Ton becomes low level until the potential of the node N2 is fixed at low level in response to this, and when the control signal Ton becomes low level in response to this. The length of the period τ3 until the potential of the node N3 is set to the high level by the control signal To
The period is τ4 or more from the time when n becomes low level to the time when it becomes high level again. Therefore, when the control signal Ton becomes the high level again, the potentials of the nodes N1, N2, and N3 are the high level, the low level, and the logic level which should be the non-operating state of the ring oscillator, respectively. Not necessarily fixed at a high level. Therefore, in the period T6 when the ring oscillator is in the operating state again, the potential of the node N1 changes to the node N1.
It changes in response to both the potential of 3 and the potential of the control signal Ton, and as a result, the oscillation cycle / frequency of the ring oscillator becomes shorter / higher than the original cycle / frequency. Next, this phenomenon will be described.

As shown in FIG. 10D, when the control signal Ton becomes high level again, as shown in FIG. 10D, the potential of the node N1 in the period T5 before the ring oscillator becomes inoperative. Node N if not already switched to low level in response to the last fall
The potential of 1 changes in response to the rising RISE of the control signal Ton and the falling DROP of the potential of the node N3.

More specifically, in the period T6,
The NAND gate 30 has a rising edge RI of the control signal Ton.
In response to SE, the potential (high level) of the node N3 at this time is inverted and a low level potential is output, so that the potential of the node N1 rises RI of the control signal Ton.
It falls to a low level with a delay from SE by the signal delay time of the NAND gate 30 (see FIG. 10B). But,
Immediately thereafter, the potential of the node N3 falls in response to the last fall of the potential of the node N1 in the period T5. Therefore, the NAND gate 30 is connected to this node N3.
A high-level potential is output in response to the falling DROP of the potential. Therefore, the potential of the node N1 changes from the fall DROP of the potential of the node N3 to the NAND gate 30.
The signal is switched to the high level with a delay of the signal delay time of.

Thus, during the period T6, the node N
The potential of 1 temporarily becomes low level in response to the rising RISE of the control signal Ton, but immediately thereafter rises to high level in response to the falling DROP of the potential of the node N3.

Thereafter, as long as the control signal Ton is at the high level, the fall and rise of the potential of the node N1 cause the rise and fall of the potential of the node N2 by the inverting operation of the inverter 10, respectively. The rising and falling of the potential of the node N2 cause the falling and rising of the potential of the node N3 by the inverting operation of the inverter 20, and the falling and the rising of the potential of the node N3 are NAND. The inverting operation of gate 30 causes the potential of node N1 to rise and fall.

Since such circuit operation is repeated,
In the period T6, the potentials of the nodes N1, N2, and N3 are shorter than those in the period T5 (1/1), as shown in FIGS. 10B, 10C, and 10D, respectively.
The level is inverted in f).

As described above, when the ring oscillator having a low original oscillation frequency is brought into the operating state again immediately after being brought from the operating state to the non-operating state, the oscillation frequency f of the ring oscillator when the operating state is brought into the operating state again becomes the original. Oscillation frequency f ₀
Will be higher than.

Now, the ring oscillator is used on the assumption that its oscillation frequency is a constant value determined by the sum of the signal delay times of the inverters forming the ring oscillator. That is, the circuit that operates in response to the output of the ring oscillator is configured to realize a predetermined function based on the original oscillation frequency of the ring oscillator. Therefore, fluctuations in the oscillation frequency of the ring oscillator may cause a malfunction of the circuit that operates by receiving the output of the ring oscillator. Therefore, the fluctuation of the oscillation frequency of the ring oscillator as described above has been a problem to be solved.

On the other hand, in response to the recent demand for lower power consumption of the semiconductor integrated circuit device, the oscillation frequency of the ring oscillator formed in the semiconductor integrated circuit device is being set low. Therefore, in the ring oscillator used for the semiconductor integrated circuit device, it is desirable to solve the above problems.

Therefore, an object of the present invention is to solve the above problems, and to maintain a constant cycle / frequency regardless of the preset oscillation cycle / frequency and the length of the period of non-operation. To provide an oscillating device that oscillates at.

[0044]

In order to achieve the above object, an oscillator according to the present invention is applied to an oscillator which receives a control signal for instructing a stop of an oscillation operation from the outside, and is connected in a ring shape. A plurality of inversion means and a forcing means controlled by the control signal.

The forcing means simultaneously forces the outputs of the plurality of inverting means to a predetermined potential in response to the control signal.

[0046]

As described above, the oscillator according to the present invention responds to the control signal instructing to stop the oscillation operation by simultaneously oscillating the potentials at the connection points between the plurality of inversion means connected in a ring. It includes a forcing means for forcing the potential to be stopped.
Therefore, in response to the instruction to stop the oscillating operation by the control signal, immediately in response to this, the potential at the input end of each inverting means does not depend on the output of the inverting means in the previous stage, and the oscillator is inoperative. Sometimes it is fixed at the level that it should be.

[0047]

1 is a circuit diagram showing the structure of a ring oscillator according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the ring oscillator shown in FIG.

The configuration and operation of the ring oscillator of this embodiment will be described below with reference to FIGS. 1 and 2.

This ring oscillator has, in addition to the structure of the conventional ring oscillator shown in FIG. 7, a P channel MOS transistor 50 connected between a power supply Vcc supplying a potential corresponding to a high level and a node N1. And a P channel M connected between the power supply Vcc and the node N3.
The N connected between the OS transistor 60 and the node N2 and the ground GND that supplies the potential corresponding to the low level.
It includes a channel MOS transistor 70 and an inverter 40.

The inverter 40 inverts the control signal Ton and supplies it to the gate of the transistor 70. The control signal Ton is directly applied to the gates of the transistors 50 and 60.

Also in the present embodiment, as in the case of this ring oscillator, the signal Ton is set to the low level in order to bring the ring oscillator into the non-operating state, and the control signal Ton is brought into the operating state in order to bring the ring oscillator into the operating state. High level.

Also in this embodiment, the signal appearing at any one of the nodes N1 to N3 is used as the output signal of this ring oscillator.

When the control signal Ton is at the low level, the transistors 50 and 60 are in the ON state, and
Since the output potential of the inverter 40 is high level, the transistor 70 is also in the ON state. On the other hand, N
The AND gate 30 outputs a high level potential regardless of the potential of the node N3.

Therefore, node N1 is supplied with a high level potential from both NAND gate 30 and transistor 50. The inverter 10 is connected to the node N2.
A low level potential is supplied by both the transistor 70 and the transistor 70. A high level potential is supplied to the node N3 by both the inverter 20 and the transistor 60.

Therefore, in the non-operating state, the node N
The potentials of 1, N2, and N3 are forced to high level, low level, and high level, respectively, as in the conventional case.

If the control signal Ton is at the high level, on the contrary, all the transistors 40, 50 and 60 are OF.
It becomes the F state. Therefore, the potential of the logic level opposite to the potential of the node N3 appears at the node N1 due to the inverting operation of the NAND gate 30, and the inverter 1 at the node N2.
The inverting operation of 0 causes a potential of a logic level opposite to that of the node N1 to appear, and the inverting operation of the inverter 20 causes a potential of a logic level opposite to that of the node N2 to appear at the node N3. In other words, this ring oscillator is
The ring oscillator operates exactly as if it were active.

Therefore, the control signal Ton (FIG. 2 (a))
Is in the high level during the periods T7 and T9, the node N
The potentials of 1, N2 and N3 are respectively as shown in FIG.
As shown in (c) and (d), the level is inverted at a constant cycle. The length of this cycle depends on the signal delay time of the inverter 10, the signal delay time of the inverter 20, and the NA
This corresponds to the sum of the signal delay time of the ND gate 30.

When the control signal Ton switches to the low level at time t1, the transistors 50, 60 and 7 are turned on.
0 switches from the OFF state to the ON state all at once. Therefore, the potential of the node N1 does not have to wait for the output potential of the NAND gate 30 to switch to the high level in response to the switching of the control signal Ton to the low level, and to wait for the power supply Vcc.
Immediately rises due to the current supplied by the transistor 50 to the node N1. Similarly, the potential of the node N2 is pulled out from the node N2 to the ground GND by the transistor 70 without waiting for the switching of the output potential of the inverter 10 to the low level in response to the switching of the potential of the node N1 to the high level. Immediately reduced by current. Similarly, the potential of the node N3 changes in response to the switching of the potential of the node N2 to the low level.
Without waiting for the switching of the output potential of to the high level,
The transistor 60 immediately fixes the high level by the current supplied from the power supply Vcc to the node N3.

As a result, the control signal To at time t1
In response to the switching of n to the low level, the potential of the node N1 becomes the high level more quickly than before, and the node N2
Potential of the node N becomes low level more quickly than before, and the node N
The potential of 3 is fixed to the high level more quickly than before.

As described above, according to this ring oscillator, MOS transistors 50, 60, and 70 are respectively connected to node N in response to the fall of control signal Ton.
The potentials of 1, N2, and N3 are set to high level, low level, regardless of the output potential of the inverter in the preceding stage of the node.
And the nodes N1 to N3 instantaneously operate so as to be forced to a high level (hereinafter, referred to as an initial potential) in the non-operating state of this ring oscillator.
Fixed to. That is, in this embodiment, as in the conventional case,
Nodes N1 and N in response to the fall of the control signal Ton
Instead of being reset to the initial potential in the order of 2, N3,
All the nodes N in response to the fall of the control signal Ton
1, N2, and N3 are almost instantaneously fixed to the initial potential.

Therefore, when the control signal Ton rises again immediately after it falls, that is, this ring oscillator has a period T11 sufficiently shorter than its original oscillation period.
Even when the ring oscillator is returned to the operating state after being made non-operating state, the ring oscillator oscillates in the same oscillation period as the oscillation period (original oscillation period) in the periods T7 and T9.

Specifically, when the control signal Ton becomes low level at time t2, in response to this, the potentials of the nodes N1, N2, and N3 are instantly changed to high level, low level, and And fixed at high level. That is, within the period T10, each node N1, N
2, and N3 are reset to the initial potential. Therefore, at time t3 when the control signal Ton becomes high level, the nodes N1 to N3 are at the initial potential, regardless of the original oscillation cycle length of the ring oscillator. Therefore, in the period T11, as in the case of the period T6 in FIG. 10, first, the potential of the node N3 is changed to the period T6.
The phenomenon of falling in response to the falling of the potential of the node N1 at the end of 9 does not occur. For this reason, the potentials of the nodes N1 to N3 are equal to the signal delay time of the inverter 10 and the inverter 20 as in the case of the period T9 after the ring oscillator is in the operating state for a long time (period T8).
The level inversion is performed in a cycle having a length corresponding to the sum of the signal delay time of 1 and the signal delay time of the NAND gate 30.

In FIG. 2, when the signal delay time of each inverter 10, 20, 30 is long, that is, when the oscillation cycle of this ring oscillator is long, the control signal Ton and each node N1, N2, N3 are applied. The relationship with the appearing potential waveform is shown.

FIG. 3 shows the potential changes of the nodes N1 to N3 when the signal delay time of each inverter 10, 20, 30 is short, that is, when the oscillation period of this ring oscillator is short.

Referring to FIG. 3, the control signal Ton is shown in FIG.
As shown in (a), consider a case where the high level is switched to the low level and then immediately the high level is switched again.

In such a case, the oscillation cycle of the conventional ring oscillator shown in FIG.
If on is shorter than the length of the period T13 in which the level is low, the potentials of the nodes N1 to N3 are inverted in the original period in the period T14 in which the ring oscillator is in the operating state again (see FIG. 9).

However, according to the present embodiment, when the control signal Ton becomes low level, the potentials of the nodes N1, N2 and N3 respectively respond to this, as shown in FIG.
As shown in (b), (c), and (d), the initial potential is forced more quickly and simultaneously than in the past.

In the above-described embodiment, one MOS transistor is provided at each node in order to reset the nodes between the plurality of inverters connected in a ring to the initial potential all at once in response to the fall of the control signal Ton. By using a logic gate that receives the control signal Ton or its inverted signal and the output signal of the preceding-stage inverter for each of the plurality of inverters that are connected, but connected in a loop, The nodes may be forced to the initial potential all at once. FIG. 4 is a circuit diagram showing a ring oscillator in which the initialization of each node is realized by such a method, and shows another embodiment of the present invention.

Referring to FIG. 4, this ring oscillator has two input NAND gates 100 and 3 connected in a ring shape.
00 and a 2-input NOR gate 200, and an inverter 400. NAND gates 100 and 300, and N
The OR gates 200 are alternately connected.

The NAND gate 100 has a control signal Ton.
And an output signal of NAND gate 300. NAN
D gate 300 receives the output signal of NOR gate 200 and control signal Ton. NOR gate 200 is NA
It receives the output signal of ND gate 100 and the output signal of inverter 400. The inverter 400 has a control signal Ton
Invert.

Also in this embodiment, the control signal Ton is set to the high level to bring the ring oscillator into the operating state, and the control signal Ton is set to the low level to bring the ring oscillator into the non-operating state. To do. A signal at any one of connection points N4 to N6 between the logic gates 100, 200, 300 connected in a ring is used as an output signal of this ring oscillator.

If the control signal Ton is at low level, N
The AND gate 100 outputs a high-level potential regardless of the potential of the node N4, and the NOR gate 200 receives the high-level potential from the inverter 400, and the NOR gate 200 receives the high-level potential.
Output a low level potential regardless of the
The D gate 300 outputs a high-level potential regardless of the potential of the node N6. Therefore, while the ring oscillator is in the inactive state, the nodes N4, N
The potentials of 5 and N6 are fixed at high level, high level, and low level, respectively.

On the other hand, if the control signal Ton is at high level, the NAND gates 200 and 300 and NOR are
Each of the gates 400 receives a high-level potential and a low-level potential at its one input terminal, and thus operates as an inverter. That is, each logic gate 200, 30
0 and 400 operate to invert the output potential of the logic gate of the previous stage and supply it to the logic gate of the next stage. Therefore, in operation, this ring oscillator is
It operates similarly to the conventional ring oscillator shown in FIG.

FIG. 5 is a timing chart showing changes in the potentials of the nodes N4 to N5 in the ring oscillator of this embodiment in response to changes in the control signal Ton. The operation of the ring oscillator according to the present embodiment will be described in more detail below with reference to FIGS. 4 and 5.

When the control signal Ton (FIG. 5A) is switched from the low level to the high level, each logic gate 200,
Since 300 and 400 simultaneously start operating as an inverter, the NAND gate 200 operates as the node N4 until then.
Of the node N5 and outputs the low level potential, the NOR gate 400 inverts the potential (high level) of the node N5 up to that point and outputs the low level potential, and the NAND gate 300 outputs the node N5. The potential (low level) of N6 up to that point is inverted and a high level potential is output. Therefore, in response to the switching of the control signal Ton from the low level to the high level, only the potential (FIG. 5C) of the node N5 among the nodes N4 to N6 changes. This potential change of the node N5 causes the NAND gate 300 to change the potential of the node N4.

As a result, as shown in FIG. 5, the potential of the node N5 is higher than that of the control signal Ton by NAND.
Switching to the low level after a delay of the signal delay time in the gate 200, the potential of the node N6 (FIG. 5B) is
NO rather than switching the potential of the node N5 to low level
Switching to the high level after a delay of the signal delay time in the R gate 400, the potential of the node N4 (FIG. 5B).
Switches to the low level with a delay of the signal delay time in the NAND gate 300 from the switching of the potential of the node N6 to the high level. After that, such transmission of the potential change of each of the nodes N4 to N6 to the next-stage node is repeated. As a result, during the period when the control signal Ton is at the high level, the potentials of the nodes N4 to N6 are the signal delay time in the NAND gate 200, the signal delay time in the NOR gate 400, and the signal delay time in the NAND gate 300. The level inversion is repeated in a cycle having a length corresponding to the sum.

When the control signal Ton switches from the high level to the low level (time t4), each logic gate 200, 3
00 and 400 output a high-level potential, a low-level potential, and a high-level potential all at once, regardless of the output potential of the preceding logic gate. Therefore, the potentials of nodes N4, N5, and N6 are immediately fixed to the high level, the high level, and the low level in response to the fall of control signal Ton.

Therefore, at time t5, the control signal To
Even if n is raised to the high level again at t6 immediately after n is switched from the high level to the low level, this control signal Ton
Since the nodes N4 to N6 have already been reset to the initial potential when the control signal Ton is restarted, the potentials of the nodes N4 to N6 begin to repeat level inversion in the original cycle in response to the restart of the control signal Ton. ..

As described above, also in this embodiment, the potential at the connection point between the inverters 200, 300 and 400 forming the ring oscillator is instantly initialized in response to the switching of the ring oscillator to the non-operating state. Therefore, the oscillation frequency of this ring oscillator does not change.

When a ring oscillator is incorporated in a MOS semiconductor integrated circuit device, each inverter forming the ring oscillator is composed of a P channel MOS transistor and an N channel MOS transistor. FIG. 6 is a circuit diagram showing a circuit configuration of an inverter forming a ring oscillator in the case where the ring oscillator is incorporated in a CMOS semiconductor integrated circuit device.

Referring to FIG. 6, in such a case, each inverter is generally connected in series between power supply Vcc and ground GND, and P-channel MOS transistor 1000 and N-channel MOS transistor 2000 are connected in series.
including. The gates of the transistors 1000 and 2000 are supplied with the output of the inverter in the preceding stage,
The potential at the connection point of 000 and 2000 is supplied to the inverter of the next stage as the output of this inverter.

Therefore, for example, in the ring oscillator of FIG. 1, when the potentials of the nodes N1 to N3 slowly change from low level to high level or from high level to low level, an inverter receiving the potential of this node as an input. The through current flowing inside increases.

For example, assume that the inverter 10 shown in FIG. 1 is configured as shown in FIG. In such a case, the potential of the node N1 is set to the transistors 1000 and 2000
Applied to the gates of transistors 1000 and 20
The potential of the connection point of 00 becomes the potential of the node N2. Therefore, when the potential of the node N1 slowly changes to the high level as in the conventional case in response to the fall of the control signal Ton, the transistors 1000 and 2 are changed during this change period.
An intermediate potential range in which the gate potential of 000 is neither a high level nor a low level (when the potential corresponding to the high level and the potential corresponding to the low level are represented by VH and VL, respectively, it is usually around (VH + VL) / 2). )
The period of time becomes longer. P-channel MOS transistor 1000 and M-channel MOS transistor 2000
Both of them are in a shallow ON state when the gate potential is in such an intermediate range. Therefore, in such a period, the transistor 1 included in the inverter 10
Since both 000 and 2000 are turned on, a current flowing from the power supply Vcc to the ground GND, that is, a through current is generated. Therefore, the longer this period is,
The through current increases.

However, according to this embodiment, each node N1
The potentials of N3 to N3 are forced to the initial potential faster than before in response to the fall of the control signal Ton, so that the P-channel transistor and the N-channel transistor forming each of the inverters 10, 20, 30 are both connected. The period in which it is in the ON state is shortened compared to the conventional case. Therefore, the control signal Ton
The shoot-through current generated in each inverter in response to the switching is reduced, and the power consumption of the ring oscillator is reduced.

[0086]

As described above, according to the present invention, the oscillation cycle / frequency of the oscillator does not fluctuate depending on the operation timing of the oscillator, and at the time of switching from the operating state to the non-operating state of the oscillator. The shoot-through current generated in the oscillator is reduced. As a result, an oscillator with a stable oscillation cycle and frequency and low power consumption is realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a ring oscillator according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the ring oscillator shown in FIG. 1 when the oscillation cycle is long.

FIG. 3 is a timing chart showing the operation of the ring oscillator shown in FIG. 1 when the oscillation cycle is short.

FIG. 4 is a circuit diagram showing a configuration of a ring oscillator according to another embodiment of the present invention.

5 is a timing chart diagram for explaining the operation of the ring oscillator of FIG. 4. FIG.

FIG. 6 is a circuit diagram of an inverter having a CMOS configuration.

FIG. 7 is a circuit diagram showing a configuration of a conventional ring oscillator.

8 is a timing chart diagram for explaining a basic operation of the ring oscillator of FIG.

9 is a timing chart showing the operation of the ring oscillator shown in FIG. 7 when the oscillation cycle is short.

10 is a timing chart showing the operation of the ring oscillator shown in FIG. 7 when the oscillation cycle is long.

[Explanation of symbols]

 10, 20, 40, 100 Inverter 30, 200, 300 2-input NAND gate 50, 60, 1000 P-channel MOS transistor 70, 2000 N-channel MOS transistor 400 2-input NOR gate In the drawings, the same reference numerals are the same or corresponding parts. Indicates.

Claims (1)

[Claims] 1. An oscillating device that receives a control signal from outside for instructing to stop an oscillating operation, and a plurality of inverting means connected in a ring, and outputs of the plurality of inverting means in response to the control signal. And an oscillating device for forcibly energizing all of them to a predetermined potential.