JPH0528753A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent destruction of data caused when an input output line is connected to a bit line at a data read-out time and to attain read-out or write-in without a signal of read-out of the data or write-in of the data. CONSTITUTION:Gates are connected to bit lines B1, BL2 between the bit lines BL1, BL2 constituting a bit line pair and the input/output lines IO1, IO2 constituting the input/output line pair and drains are connected to data read-out N channel MOS transistors NR1, NR2 and the gates are connected to the input/ output lines IO1, IO2. Data write-in P channel MOS transistors PW1, PW2 in which the drains are connected to bit lines BL1, BL2, are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device capable of reading and writing data through a data input / output line.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a connection relationship between a bit line pair and an input / output line pair in a conventional static column operation mode DRAM, in which BL ₁ and BL ₂ are bits forming a bit line pair. Lines, IO ₁ and IO _2, are data input / output lines forming an input / output line pair, and BLTG is a bit line transfer gate control signal line. One end of each of the bit lines BL ₁ and BL ₂ is connected to a memory cell in a memory cell array (not shown), and an N-channel MOS transistor TG ₁ whose gate is connected to a bit line transfer gate control signal line BLTG in the middle , TG ₂ , TG ₃ , TG ₄ are inserted.

A sense amplifier 10 is connected between the transistors TG ₁ and TG ₃ and TG ₂ and TG _{4 to} both bit lines BL ₁ and BL _2, and a node where amplification is performed by the sense amplifier 10, So-called sense nodes SN ₁ and SN ₂ are column selection N-channel MOS transistors NC ₁ and NC _{2, respectively.}
Are connected to input / output lines IO ₁ and IO ₂ . The gates of the column selection N-channel MOS transistors NC ₁ and NC ₂ are connected to the column selection signal line YS, one of the source and the drain thereof is the sense nodes SN ₁ and SN ₂ , and the other is the input / output lines IO ₁ and IO _2. It is connected to the.

Next, the operation of such a semiconductor memory device will be described. First, in the data read operation, the input / output line IO
_{While 1} and IO ₂ are precharged, a high level signal “H” is applied to the bit line transfer gate control signal line BLTG to make the selected bit lines BL ₁ and BL ₂ conductive. As a result, weak data from a memory cell (not shown) is guided to the sense nodes SN ₁ and SN ₂ and amplified by the sense amplifier 10.

In the amplification by the sense amplifier 10, for example, when the data signal of the sense node SN ₁ is amplified to the high level "H" side, the data signal of the sense node SN ₂ is amplified to the corresponding low level "L" side. It is supposed to do.
Input a high level "H" signal to the column selection signal line YS to select both column selection N-channel MOS transistors NC ₁ ,
Turn on NC ₂ . This makes sense node SN ₁
Is the input / output line IO _1, and the sense node SN ₂ is the input / output line IO
₂ will be connected respectively, and data will be read. Data write operation provides a signal of high level "H" to the column selection signal line YS, the respective column selecting N-channel MOS transistor NC _1, NC ₂ turned on. This connects the input and output lines IO _1, IO ₂ to the bit lines BL _1, BL _2, data is written to the memory cell via the input and output lines IO _1, IO _2, the bit lines BL _1, BL _2.

By the way, in such a conventional device,
When reading data, the input / output lines IO ₁ and IO ₂ are both precharged, and a high level “H” signal is applied to the column selection signal line YS to turn on the column selection N-channel MOS transistors NC ₁ and NC ₂ . I / O line I when turned on
The high level “H” charges of O ₁ and IO ₂ are applied to the sense node SN.
₁ and flows back into SN ₂ .

When the data of the sense nodes SN ₁ and SN ₂ is amplified by the sense amplifier 10 to a sufficiently large potential difference, the data is less likely to be destroyed, but the operation of the sense amplifier 10 does not occur during the amplification. It may become unstable and destroy data. Therefore, the column selection signal line YS
The high level “H” signal is set to the sense amplifier
The data signal must be amplified by 10 at a time when it has been sufficiently amplified, and a waiting time is required for that purpose, which makes it difficult to read quickly.

FIG. 5 is a circuit diagram showing a connection relationship between a bit line and a read data line and a write data line in another conventional semiconductor memory device. In this semiconductor memory device, a pair of read data lines RD are used instead of the input / output lines.
_1, RD _2, the write data line WD _1, WD ₂ and provided with a write start signal line WE, read N-channel MOS transistor NR _1, NR ₂ between these and the bit lines BL _1, BL _2,
N-channel MOS transistor for column selection NC ₁ , NC ₂ ,
NC ₃ and write N-channel MOS transistors NW ₁ and NW ₂
Is intervened.

Read N-channel MOS transistor N
R ₁ and NR ₂ have their gates connected to sense nodes SN ₁ and SN _{2, respectively.}
, The drain is connected to the read data lines RD ₁ and RD ₂ , and the source is grounded via the column selecting N-channel MOS transistor NC ₁ . The column selection N-channel MOS transistor NC ₁ has its gate grounded to the column selection signal line YS and its source grounded. Column selection N-channel MOS transistors NC ₂ and NC ₃ have their gates connected to column selection signal lines.
The data line WD ₁ ,
WD ₂ and the other N-channel MOS transistor for writing
Connected to NW ₁ and NW ₂ .

Write N-channel MOS transistor N
The gates of W ₁ and NW ₂ are respectively connected to the write start signal line WE,
Further, one of the source and the drain is connected to the column selecting N channel MOS transistors NC ₂ and NC ₃ , and the other is connected to the sense nodes SN ₁ and SN ₂ . Other configurations are the same as those of the conventional device shown in FIG. 4, and corresponding parts are designated by the same reference numerals.

Next, the operation of such a semiconductor memory device will be described. Data read operation is read data line
RD ₁ and RD ₂ are precharged and set to a high level “H”, and the bit line transfer gate control signal line BLTG is set to a high level “H” to make the bit lines BL ₁ and BL ₂ conductive. Data from a predetermined memory cell is led to the sense nodes SN ₁ and SN ₂ and amplified by the sense amplifier 10. When the column selection signal line YS is set to the high level “H” and the column selection N-channel MOS transistor NC ₁ is turned on, when the data signal is amplified by the sense amplifier 10 to a level exceeding the threshold value, , For reading N
Channel MOS transistors NR ₁ and NR ₂ are turned on, the precharged read data lines RD ₁ and RD ₂ are discharged, and data is read.

Data is written in the column selection signal line YS.
When the write start signal line WE and the write start signal line WE are set to the high level "H" respectively, the column selection N-channel MOS transistor N
C ₂ , NC ₃ and write N-channel MOS transistor NW
Both ₁ and NW ₂ are turned on and write data line WD
₁ and WD ₂ are connected to the bit lines BL ₁ and BL ₂ , and the data is written in a predetermined memory cell.

[0013]

In the conventional semiconductor memory device as shown in FIG. 5, the read data lines RD ₁ and RD ₂ and the bit line BL ₁ , as in the conventional device shown in FIG.
Since it is not directly connected to BL ₂ , data destruction at the time of reading does not occur and the input timing of the column selection signal can be set earlier, which speeds up the reading operation, while reading and writing Separate read data line RD
₁ , RD ₂ , write data lines WD ₁ , WD ₂ ,
Moreover, since the write start signal line WE is also required, the required line length becomes long, the number of elements such as MOS transistors is large, and the pattern area increases. The present invention has been made in view of the above circumstances, and an object thereof is a semiconductor memory in which data is not destroyed at the time of reading data, a wiring length can be short, and the number of elements such as transistors is not increased. To provide the equipment.

[0014]

A semiconductor memory device according to the present invention is a memory cell selected by controlling a MOS transistor provided between a bit line connected to a memory cell and a data input / output line. In the semiconductor memory device configured to read or write the data of the above, in the MOS transistor, the gate is connected to the bit line and the drain is connected to the input / output line. It consists of a write MOS transistor connected to the output line and the drain connected to the bit line.
Further, it is characterized by comprising a circuit for activating a circuit including the read MOS transistor and the write MOS transistor.

[0015]

According to the present invention, a read MOS transistor having a gate connected to the bit line and a drain connected to the input / output line, and a gate connected to the input / output line are provided between the bit line and the data input / output line. Since the writing MOS transistor is connected and the drain is connected to the bit line, the input / output line is not directly connected to the bit line and the data is not destroyed.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. (Embodiment 1) FIG. 1 is a circuit diagram showing a connection relationship between bit lines and input / output lines in a semiconductor memory device according to the present invention, in which BL ₁ and BL ₂ are bit lines forming a bit line pair,
IO ₁ and IO ₂ are input / output lines that form a data input / output line pair,
BLTG represents a bit line transfer gate control signal line. One end of each bit line BL ₁ and BL ₂ is connected to a memory cell (not shown), and a gate is provided in the middle of the bit line transfer gate control signal line BL.
Transistors TG _{1 to} TG ₄ connected to TG are interposed, and bit lines BL ₁ and BL ₂ connected to the selected memory cell array are selected by setting the bit line transfer gate control signal line BLTG to high level “H”. Will be done.

A sense amplifier 10 is connected between the MOS transistors TG ₁ , TG ₃ and TG ₂ , TG _{4 in} each bit line BL ₁ , BL ₂ . The sense amplifier 10 has a pair of N-channel MOS transistors connected in series, and a pair of P-channel MOS transistors also connected in series to the bit lines BL ₁ and BL ₂ in parallel, and the source of the N-channel MOS transistor. Is connected to the common source line V _SN , the source of the P-channel MOS transistor is connected to the common source line V _SP , and the gates of the corresponding N-channel MOS transistor and P-channel MOS transistor are connected to the bit lines BL ₁ and BL ₂ , respectively. Connected and configured.

The bit lines BL ₁ and BL ₂ and the input / output line I
O ₁ and IO ₂ are read N-channel MOS transistor N
R ₁ , NR ₂ and write P channel MOS transistor PW
₁ , PW ₂ is installed.

Read N-channel MOS transistor N
The gates of R ₁ and NR ₂ are respectively connected to the sense nodes SN ₁ and SN ₂ in the bit lines BL ₁ and BL ₂ , the drains are input / output lines IO ₁ and IO ₂ , and the sources are N-channel MOS for column selection.
Connected to the drain of transistor NC ₁ . The column selection N-channel MOS transistor NC ₁ has its gate connected to the column selection signal line YS ₁ and its source grounded.

On the other hand, the write P-channel MOS transistors PW ₁ and PW ₂ have their gates connected to the input / output lines IO ₁ and IO ₂ , respectively, and their drains to the sense nodes SN ₁ and SN on the bit lines BL ₁ and BL ₂ , respectively. ₂ and the source thereof is connected to the drain of the column selecting P-channel MOS transistor PC ₁ , respectively. P-channel MOS transistor for column selection
PC ₁ has its gate connected to the column selection signal line YS ₂ and its source connected to the power supply V _CC .

Next, the operation of such a semiconductor memory device will be described. First, the data read operation is performed with the input / output lines IO ₁ , IO ₂
Is precharged and a high level signal is set to the bit line transfer gate control signal line BLTG to bring the bit lines BL ₁ and BL ₂ into a conductive state. As a result, the data is led to the sense nodes SN ₁ and SN ₂ , and the sense amplifier 1
Amplified at 0. When one of the read N-channel MOS transistors NR ₁ and NR ₂ is turned on and the other is turned off, the column selection signal line YS _{1 is set} to high level “H” and the column selection signal line YS _{2 is set} to low. Set to level “L”.

As a result, either _{one of the} read N-channel MOS transistor NR ₁ or NR ₂ and the column select N-channel MOS transistor NC ₁ is turned on, and the charge of the precharged input / output line IO ₁ or IO ₂ is reduced. After being discharged, data is read out through the input / output line IO ₁ or IO ₂ .

The precharged charges of the input / output lines IO ₁ and IO ₂ are directly transferred to the sense nodes SN ₁ and SN of the bit lines BL ₁ and BL _2.
Since it is discharged without passing through ₂ , the sense node SN ₁ ,
The data of SN ₂ is not destroyed, and the column selection signal line YS ₁ is a read N-channel MOS transistor N.
The high level is set when _{one of} R ₁ and NR ₂ is in the on state and the other is in the off state, so that it is possible to set it at an earlier time compared to the conventional device and speed up the data read. Can be achieved.

When the data reading progresses and the potential of the input / output line IO ₁ or IO ₂ becomes equal to or lower than V _CC -V _tP (threshold of the write N-channel MOS transistors PW ₁ and PW ₂ ), this occurs. P channel for writing with gate connected
The MOS transistor PW ₁ or PW ₂ is turned on, while the column selection signal line YS ₂ has already been given a low level “L” signal, so the column selection P-channel MOS transistor PC ₁ is turned on. The voltage of the power supply V _CC is applied to the sense node SN ₁ or SN ₂ of the bit line BL ₁ or BL ₂ via the column selection P-channel MOS transistor PC ₁ and the write P-channel MOS transistor PW ₁ or PW _2. , Without disturbing the operation at the time of reading,
Rather, it operates to facilitate the read operation.

On the other hand, in the data write operation, when the bit line transfer gate control signal line BLTG is set to the high level "H" and then the data signal is applied to the input / output lines IO ₁ and IO ₂ , the low level signal is applied. N channel MO for writing, whose gate is connected to input / output line IO ₁ or IO ₂
S transistor PW ₁ or PW ₂ is turned on and power supply V
The voltage of _CC passes through the write N-channel MOS transistor PW ₁ or PW ₂ and the sense node SN _{1 of the} bit line BL ₁ or BL _2.
Alternatively, the data is written by being added to SN ₂ , and the data is written in priority to the read operation.

(Embodiment 2) FIG. 2 is a circuit diagram showing a connection relationship between bit lines and input / output lines in another embodiment of the present invention. In this embodiment, the sense amplifier 10 in the first embodiment is divided into an N-channel sense amplifier 11 and a P-channel sense amplifier 12, and a common source line V _SN of the N-channel sense amplifier 11 has a column selection N-channel MOS transistor. The source of the transistor NC ₁ is connected, while the common source line V _SP of the P-channel sense amplifier 12 is connected to the P-channel MOS for column selection.
The source of transistor PC ₁ is connected. The other structure is substantially the same as that of the first embodiment, and the corresponding parts are denoted by the same reference numerals and the description thereof is omitted.

The operation of the second embodiment will be described. In the data read operation, a high level “H” signal is set to the bit line transfer gate control signal line BLTG,
Data is derived to the sense nodes SN ₁ and SN ₂ of both bit lines BL ₁ and BL ₂ , and the N-channel sense amplifier 11 and the P-channel sense amplifier 12 have, for example, a high level of the sense node SN _{1 and} the sense node SN _{1. Assuming that} the level of ₂ is amplified so that it becomes lower, the N channel sense amplifier
The 11 common source lines V _SN are pulled _toward the zero V side. Along with this, the column selection N-channel MOS transistor NC ₁ whose source is connected to this is stepped down to the zero V side having the same potential as the common source line V _SN .

[0028] By setting the column selection signal line YS in this process to the high level "H" column selecting N-channel MOS transistor NC ₁ is turned on, the drain side, N-channel readout other words MOS transistor NR ₁ , NR
The source-side potential of ₂ is lowered, and at the same time the potential difference of the sense node SN ₁ or SN ₂ exceeds the threshold value of the read N-channel MOS transistor NR ₁ or NR ₂ , it is turned on and the input / output line IO ₁ or IO ₂ The precharge potential of is reduced and data is read.

Next, the write operation will be described. During the previous read operation, the potential of the common source line V _SP is changed to the power source V by the amplifying action on the high level side of the P-channel sense amplifier 12.
_The source of the write P-channel MOS transistor PC _{1 having} its source connected to the voltage side of _CC has been raised to the potential of the common source line V _SP .

On the other hand, the column selection signal line YS ₂ is set to the low level “L” signal at the same time as the high level “H” signal is set to the column selection signal line YS ₁ at the time of data reading. Therefore, the column selection P-channel MOS transistor PC ₁ is in the ON state, and the drain side thereof is also raised to the potential of the common source V _SP .

Write P-channel MOS transistor P
Since the precharge voltage of the input / output lines IO ₁ and IO ₂ is applied to the gates of W ₁ and PW ₂ , they are kept in the off state during the data read operation. Now, when the data read operation as described above progresses and the precharge potential of the input / output line IO ₁ or IO ₂ is lowered, it is stepped down to V _CC -V _tP (write P channel MOS transistor threshold) or less. The write P-channel MOS transistor PW ₁ and / or PW ₂ is turned on, and the sense node S of the bit lines BL ₁ and BL ₂
N ₁ and SN ₂ are filled with the charges of the common source line V _SP , and data writing is performed.

In the second embodiment, the read N-channel MOS transistor may be set at any timing to set the high level "H" signal to the column selection signal lines YS ₁ and YS ₂ from the viewpoint of increasing the read speed. Since the NR ₁ and NR ₂ are not turned on unless the potentials of the sense nodes SN ₁ and SN ₂ exceed these thresholds, the column selection signal line Y
The high level setting timing of S ₁ and YS ₂ can be set regardless of the circumstances of the read N-channel MOS transistors NR ₁ and NR ₂ , and the read speed can be further increased.

(Embodiment 3) FIG. 3 is a circuit diagram showing a connection relationship between a bit line and an input / output line in still another embodiment of the present invention. Sense node SN _{1 of} bit lines BL ₁ and BL ₂ ,
P channel MOS transistors PR ₁ and PR ₂ for reading and N channel for writing between SN ₂ and the input / output lines IO ₁ and IO _2.
MOS transistors NW ₁ and NW ₂ are interposed.

Read P-channel MOS transistor P
The gates of R ₁ and PR ₂ are connected to the sense nodes SN ₁ and SN ₂ , respectively, the source is connected to the N-channel MOS transistor NC ₁ for column selection, and the drain is connected to each of the input / output lines IO ₁ and IO _2. There is. The column selection N-channel MOS transistor NC ₁ has its gate connected to the column selection signal line YS and its source connected to the power supply V _CC .

On the other hand, in the write N-channel MOS transistors NW ₁ and NW ₂ , the gates are connected to the input / output lines IO ₁ and IO ₂ , respectively, the drains are the sense nodes SN ₁ and SN ₂ , and the source is the column selecting N-channel. Each is connected to the MOS transistor NC ₂ . The column selection N-channel MOS transistor NC ₂ has a gate connected to the column selection signal line YS and a source grounded.

Next, the operation of such a semiconductor memory device will be described. The data read operation is substantially the same as that of the first embodiment, the input / output lines IO ₁ and IO ₂ are precharged, and the bit line transfer gate control signal line BLTG is set to the high level to set the memory cell data. To the sense nodes SN ₁ and SN ₂ and amplified by the sense amplifier 10.

Thus, the read P-channel MOS transistor PR ₁ or PR ₂ whose gate is connected to the sense node SN ₁ or SN ₂ whose data is amplified to the low level side
Is turned on, and the column selection signal line YS is set to the high level “H” at a predetermined timing, the column selection N-channel MOS transistor NC ₁ is turned on and the voltage of the power supply V _CC is changed to the input / output line IO ₁ Therefore, IO ₂ is filled and read.

In the process of reading data, the input / output line IO ₁ or IO
_When the voltage of the power supply V _CC is applied to ₂ , the write N-channel MOS transistor NW ₁ or NW ₂ whose gate is connected to the high-voltage input / output line IO ₁ or IO ₂ is turned on, and column selection is performed. The signal line YS is already set to the high level "H" and the column selection N-channel MOS transistor NC
₂ is on, so write N channel MO
S-transistor NW ₁ or NW ₂ is grounded and the sense node
SN ₁ or SN ₂ is connected to zero potential. The data writing operation is also substantially the same as that of the first embodiment, and the description thereof will be omitted.

[0039]

As described above, in the device of the present invention, a read MOS transistor in which the gate is connected to the bit line and the drain is connected to the input / output line between the bit line and the data input / output line, Since the write MOS transistor with the gate connected to the I / O line and the drain connected to the bit line is interposed, the I / O line and the bit line are not directly connected when reading data, and data destruction is guaranteed. Is prevented by
Moreover, the circuit itself for that purpose is not particularly complicated, and the present invention has excellent effects such as speeding up of data reading.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a connection relationship between a bit line and an input / output line in a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a connection relationship between bit lines and input / output lines according to another embodiment of the present invention.

FIG. 3 is a circuit diagram showing a connection relationship between bit lines and input / output lines according to still another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a connection relationship between bit lines and input / output lines in a conventional device.

FIG. 5 is a circuit diagram showing a connection relationship between bit lines and input / output lines in another conventional device.

[Explanation of symbols]

10 Sense amplifier 11 N-channel sense amplifier 12 P-channel sense amplifier BL ₁ , BL ₂ Bit line IO ₁ , IO _{2 I} / O line SN ₁ , SN ₂ Sense node NR ₁ , NR ₂ Read N-channel MOS transistor PW ₁ , PW ₂ P channel MOS transistor for writing NC ₁ N channel MOS transistor for column selection PC ₁ P channel MOS transistor for column selection

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display location 7323-5L G11C 11/34 305

Claims (1)

Claim: What is claimed is: 1. A MOS transistor provided between a bit line connected to a memory cell and a data input / output line is controlled to read data from a selected memory cell, or In a semiconductor memory device adapted to write data to a MOS transistor, the MOS transistor has a gate connected to a bit line and a drain connected to an input / output line, and a read MOS transistor connected to the input / output line and a drain. And a circuit for activating a circuit including the read MOS transistor and the write MOS transistor, the semiconductor memory device comprising: