JPH05268058A - Gate circuit and semiconductor device including the same - Google Patents

Abstract

PURPOSE:To obtain the gate circuit sufficiently ensuring a gate breakdown voltage even when a power supply voltage is increased more than a hot carrier breakdown voltage and a drain-source breakdown voltage of a MOSFET. CONSTITUTION:The gate circuit consists of a 1st element 1 connected between a power supply terminal 8 and an output terminal 7, a 2nd element 2 connected between the output terminal 7 and a ground terminal 7, 9, an output stage driving a load connecting to the output terminal and a drive stage comprising series connection among a drive MOSFET 3, a constant voltage drop element 5 and a charge extract MOSFET 4 and connecting to an input electrode of the 1st element 1 and/or 2nd element extract MOSFET 4 are made complementary to each other and the thickness of a gate oxide film of the drive MOSFET 3 is made thicker than the thickness of the gate oxide film of the charge extraction MOSFET 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate circuit and a semiconductor device including the same, and in particular, a high speed operation is possible even when an insulated gate FET (hereinafter referred to as MOSFET) having a low breakdown voltage is used. The present invention relates to a possible gate circuit and a semiconductor device including the same.

[0002]

2. Description of the Related Art Conventionally, in the field of logic circuits, an n-channel MOSFET (hereinafter referred to as nMOSFET) and a p-channel MOSFET (hereinafter referred to as pMOS) are used.
CFET logic circuit composed of CMOSFETs, which are complementary-coupled with FET), bipolar transistor logic circuit composed of bipolar transistors, CMOSF
A BiCMOS logic circuit in which ET and a bipolar transistor are combined in the circuit is known.

Among these logic circuits, CMOSFET logic circuits are widely used because they can be highly integrated and operate with low power consumption. Although the bipolar transistor logic circuit consumes a relatively large amount of power, it can operate at high speed. The BiCMOS logic circuit has both the high integration characteristic and low power consumption characteristic of the CMOSFET logic circuit, and the high speed operation characteristic of the bipolar transistor logic circuit.

However, in recent years, when a large-scale integrated circuit (LSI) is constructed, the M arranged in it is arranged.
Advances in the miniaturization technology for OSFETs and bipolar transistors have enabled high integration of LSIs, and also improved performance of elements such as MOSFETs and bipolar transistors to enable high-speed operation of LSIs themselves. Is coming. On the other hand, in the MOSFET device, the electric field inside the device increases with the miniaturization of the device, and the long-term reliability of the device is impaired due to the so-called hot carrier effect. In order to eliminate this adverse effect, the power supply voltage supplied to the MOSFET element may be selected low and the electric field inside the element may be lowered. However, in the BiCMOS logic circuit, due to the presence of the forward voltage Vbe between the base and emitter of the bipolar transistor, the amplitude of the output voltage and the amplitude of the input voltage become smaller than the power supply voltage by about 2 Vbe, and as a result, The BiCMOS logic circuit is greatly affected by the low power supply voltage, which causes a new problem that it cannot operate at high speed.

In order to eliminate this new harmful effect, BiCM
In the OS logic circuit, a means for applying only a voltage lower than the power supply voltage to the MOSFET is provided, and the power supply voltage is applied to the other elements, and the power supply voltage of the BiCMOS logic circuit is set. MOSFET
Withstand voltage determined by the reliability of
Several methods have already been proposed for increasing the ET breakdown voltage).

By the way, as one of the methods proposed above,
The method disclosed in JP-A-1-126824 and JP-A-3-185920, that is, a method in which a voltage corresponding to the voltage Vbe is biased in advance to the base of a bipolar transistor which constitutes an output stage of a BiCMOS logic circuit Method (hereinafter referred to as the base bias method)
Is. In this base bias method, a MOS for extracting a base charge that is usually connected to a ground point is used.
The voltage Vbe or the voltage 2Vbe that is twice the voltage Vbe is applied to the source of the FET, and the voltage applied between the drain and source of all the MOSFETs is lower than the power supply voltage Vcc by the voltage Vbe or 2Vbe. is doing. By adopting this configuration, the power supply voltage supplied to the BiCMOS circuit can be selected to be higher than the withstand voltage of the MOSFET by at least the voltage Vbe,
This enables the BiCMOS circuit to operate at high speed.

[0007]

However, the base bias method has the advantage that the voltage applied between the drain and the source of all MOSFETs is lower than the power supply voltage Vcc by the voltage Vbe or 2Vbe. Regarding the driving MOSFET for driving the output stage bipolar transistor of the BiCMOS logic circuit,
A voltage higher than the voltage applied between the drain and the source by the voltage Vbe is applied between the gate and the source (substrate). That is, in the base bias method, as described above, the power supply voltage supplied to the BiCMOS logic circuit is higher than the withstand voltage of the MOSFET by the voltage Vbe to 2V.
However, if the power supply voltage is set based on the breakdown voltage between the drain and the source of the MOSFET, the voltage between the gate and the source (substrate) of the driving MOSFET is higher than the breakdown voltage. A voltage higher by Vbe is applied. Further, in the case of configuring MOSFETs used in various logic circuits including BiCMOS logic circuits, according to the conventional method, the gate oxide film is configured to have the same thickness for all MOSFETs. is doing.

Here, if the thickness of the gate oxide film of the driving MOSFET is determined based on the breakdown voltage between the gate and the source, M other than the driving MOSFET is determined.
The current flowing through the OSFET becomes small, and even if the power supply voltage supplied to the various logic circuits is increased, the various logic circuits cannot operate at high speed. On the contrary, the thickness of the gate oxide film of the MOSFET other than the driving MOSFET is
If it is determined based on the breakdown voltage between the sources, the driving M
There is a problem that the gate oxide film causes dielectric breakdown due to the high voltage applied between the gate and source (substrate) of the OSFET.

As described above, conventionally, since the breakdown voltage of each element constituted by the LSI has not been sufficiently taken into consideration, it is difficult to realize a logic circuit having an LSI configuration which actually operates at high speed. there were.

The present invention eliminates the above-mentioned various problems, and an object thereof is to make the gate withstand voltage sufficient even if the power supply voltage is higher than the hot carrier withstand voltage of MOSFET and the withstand voltage between drain and source. Another object of the present invention is to provide a gate circuit which can be ensured and a semiconductor device including the same.

[0011]

To achieve the above object, the present invention provides a first element connected between one power supply terminal and an output terminal and a first element connected between the output terminal and the other power supply terminal. And an output stage for driving a load connected to the output terminal, and a series connection body of at least a driving insulated gate FET and a constant voltage drop element and an insulated gate FET for charge extraction. In a gate circuit having a driving stage connected to the input electrodes of the first element and / or the second element, the conductivity type of the driving insulated gate FET and the insulating gate type for charge extraction FE
The conductivity type of T is complementary to each other, and the thickness of the gate oxide film of the driving insulated gate FET is different from the thickness of the gate oxide film of the charge extracting insulated gate FET. It is equipped with means.

In order to achieve the above object, the present invention provides a first element connected between one power supply terminal and an output terminal and a second element connected between the output terminal and the other power supply terminal. An output stage which is composed of an element and drives a load connected to the output terminal, at least a driving insulated gate FET and a constant voltage drop element, and an electric charge extraction insulated gate FET
In a gate circuit having a driving stage connected to the input electrodes of the first element and / or the second element, the conductive type of the driving insulated gate FET and the charge. The conductivity type of the extraction insulated gate FET is complementary to each other, and the material of the gate oxide film of the driving insulated gate FET and the material of the gate oxide film of the charge extraction insulated gate FET. Are different from each other.

Further, in order to achieve the above object, the present invention has n and p well regions arranged adjacent to each other,
The p-well region and a pair of high-impurity-concentration n + source and drain regions provided above the p-well region;
A first insulated gate FET composed of a gate electrode disposed on the surface of the p well region between the n + source and drain regions via a first insulating layer; and the n well region, A pair of high impurity concentration p + source and drain regions provided on the upper side of the n well region, and a gate electrode disposed on the surface of the n well region between the p + source and drain regions via a second insulating layer. And a second insulated gate FET, the first and second insulated gate FETs having complementary conductivity types and forming a drive stage of a gate circuit. The thickness of the first insulating layer and the second
Or the thickness of the insulation layer of
It comprises a third means configured such that the material of the first insulating layer and the material of the second insulating layer are different.

[0014]

According to the first means, the thickness of the gate oxide film of the driving MOSFET for driving the first element and / or the second element forming the output stage of the gate circuit is set to Since the gate oxide film is thicker than the MOSFET other than the MOSFET, the driving MOS is
The gate breakdown voltage and TDDB breakdown voltage of the FET are the gate breakdown voltage and TD of the MOSFET other than the driving MOSFET.
It becomes higher than the DB withstand voltage, and the power supply voltage supplied to the gate circuit can be made higher than the drain-source withstand voltage and the hot carrier withstand voltage of the driving MOSFET, thereby operating the gate circuit at high speed. It will be possible.

According to the second means, the dielectric constant of the gate oxide film of the driving MOSFET for driving the first element and / or the second element forming the output stage of the gate circuit Since it is made of a material that has a larger dielectric constant than the gate oxide film of MOSFETs other than
The gate withstand voltage and the TDDB withstand voltage of the driving MOSFET are higher than the gate withstand voltage and the TDDB withstand voltage of MOSFETs other than the driving MOSFET, and are higher than the drain-source withstand voltage and the hot carrier withstand voltage of the driving MOSFET. It is possible to increase the power supply voltage supplied to the gate circuit, which allows the gate circuit to operate at high speed.

According to the third means, in the case where MOSFETs of the same conductivity type which form the drive stage of the gate circuit are arranged and formed in the semiconductor device, the gate oxide film of the MOSFET of one conductivity type is formed. Is thicker than the thickness of the gate oxide film of the MOSFET of the other conductivity type, or the dielectric constant of the gate oxide film of the MOSFET of one conductivity type is set to the gate oxide film of the MOSFET of the other conductivity type. , The gate breakdown voltage and TDDB breakdown voltage of the one conductivity type MOSFET are higher than the gate breakdown voltage and TDDB breakdown voltage of the other conductivity type MOSFET. M
The power supply voltage supplied to the gate circuit can be made higher than the drain-source withstand voltage and the hot carrier withstand voltage of the OSFET, whereby the gate circuit formed in this semiconductor device can be operated at high speed. It will be possible.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first gate circuit according to the present invention.
2 is a circuit configuration diagram showing an embodiment of FIG.

In FIG. 1, 1 is an npn bipolar transistor, 2 is an nMOSFET, 3 is a driving pMOSFET for driving the npn transistor 1, 4 is an nMOSFET for extracting a charge for extracting a base charge of the npn transistor 1, 5 Is a diode constituting a constant voltage drop element, 6 is a signal input terminal, 7 is a signal output terminal, 8 is a first power supply terminal, and 9 is a second power supply terminal (ground terminal).

The circuit portion consisting of the npn transistor 1 connected between the first power supply terminal 8 and the output terminal 7 and the nMOSFET 2 connected to the output terminal 7 and the second power supply terminal 9 is the output stage. And the part is BiNMOS
It constitutes a gate circuit. Also, a driving pMOSFET 3 connected between the first power supply terminal 8 and the base of the npn transistor 1, a diode 5 connected between the base of the npn transistor 1 and the ground terminal 9, and an nMOSFET 4 for extracting electric charge are connected in series. The circuit portion including the body is a driving stage, and the portion is a pull-up side np of the output stage.
The base bias method is applied to the n-transistor 1. In this case, nMOSFET2
Has a drain connected to the output terminal 7 and a source connected to the second power supply terminal 9, and the driving pMOSFET 3 is
The source is connected to the first power supply terminal 8 and the drain is connected to the base. In addition, nMOS for charge extraction
The FET 4 has a drain connected to the cathode of the diode 5 and a source connected to the ground terminal 9. further,
Although not particularly shown, the gate oxide film of the driving pMOSFET 3 has a thickness equal to that of the nMOSFET 4 for extracting charges.
Thicker than the thickness of the gate oxide film of
Only the gate oxide film of the driving pMOSFET 3 is made of a material having a high dielectric constant such as tantalum oxide instead of the silicon oxide film.

Here, nMOSFE for charge extraction
When T4 is turned on, the base charge of the npn transistor 20 is extracted and transmitted to the ground terminal 9, thereby making n
The pn transistor 1 is surely turned off, and the through current of the npn transistor 1 in the transient state is suppressed. Further, the diode 5 is driven by the forward voltage Vbe generated at both ends of the diode 5 to drive the pMOSF.
Drain of ET3 and nMOSFET4 for charge extraction
The applied voltage between the sources is set to the above-mentioned voltage V rather than the power supply voltage Vcc.
The amount is reduced by be.

In the following drawings, the well (substrate) of the pMOSFET is connected to the first power supply terminal side, and the well (substrate) of the nMOSFET is connected to the second power supply terminal side (ground) unless otherwise specified. It is connected to the voltage side).

The gate circuit of this embodiment operates as described below.

The input terminal 6 has a voltage (Vc) whose positive level is lower than the supply voltage Vcc of the power supply terminal 8 by the voltage Vbe.
c-Vbe), an input signal whose negative level is the ground voltage is supplied. First, during the positive level period of the input signal, nMO
The SFET 2 is turned on, the voltage drop between the source and the drain becomes almost 0, the voltage of the output terminal 7 drops to the ground voltage, and the output signal becomes the ground voltage (negative level). At this time, the driving pMOSFET 3 is turned off, and the npn transistor 1 is also turned off accordingly, but the charge extracting nMOSFET 4 and the diode 5 are turned on, and the base charge of the npn transistor 1 is extracted to the ground point. And the voltage at point A is set to the voltage Vbe by the constant voltage Vbe generated across the diode 5.

Next, in the negative level period of the input signal, the driving pMOSFET 3 is turned on, the voltage drop between its source and drain becomes almost 0, and the voltage at the point A becomes the power supply voltage Vcc. Equal to npn
The transistor 1 is turned on, and the voltage of the output terminal 7 is the power supply voltage Vcc minus the base-emitter voltage Vbe of the npn transistor 1 (Vcc-Vb).
e) and the output signal is the voltage (Vcc-Vbe).
(Positive level). At this time, both the nMOSFET 2 and the nMOSFET 4 for extracting charges are turned off, so that the voltage at the point A and the output voltage of the output terminal 7 are not affected at all.

As described above, in this embodiment, both the input signal and the output signal are voltage (V
cc-Vbe), which is the ground voltage when the level is negative, the output signal has the same level as the input signal and only the polarity thereof is inverted. Also,
The point A rises to the power supply voltage Vcc at a positive level by the action of the diode 5 which generates a constant voltage Vbe at both ends when the point A is turned on, while the voltage Vbecomes at a negative level.
Since the voltage of the output terminal 7 rises to the above voltage (Vcc-Vbe) at the positive level and drops to the ground voltage at the negative level, the nMOSFET 2,
The maximum voltage (Vcc-Vb) is applied between the drain and source of the pMOSFET 3 and the nMOSFET 4.
Only the voltage e) is applied, no more voltage is applied, and the voltage applied between the collector and the emitter of the npn transistor 1 is lower than the power supply voltage Vcc (maximum). Vcc-Vbe)
Is.

Here, in this embodiment, between the collector and the emitter of the npn transistor 1 and each MOSFE.
The applied voltage between the drain and the source of T2, 3, 4 can be suppressed to the above-mentioned voltage (Vcc-Vbe) at the maximum, but the pull-down side of the output stage is composed of the nMOSFET 2 and, as described above, The negative level of the output voltage of the terminal 7 drops to the ground potential. Therefore, a power supply voltage Vcc higher than the voltage (Vcc-Vbe) is directly applied between the gate and source (substrate) of the driving pMOSFET 3, and the gate oxide film of the driving pMOSFET 3 is caused by this high power supply voltage Vcc. Dielectric breakdown may occur.

Therefore, in this embodiment, means for preventing the dielectric breakdown is provided, and the first means is to change the thickness of the gate oxide film of the driving pMOSFET 3 to the other values. MOSFET, or nMOSFET
The gate oxide film is thicker than the second and fourth gate oxide films, and the second means is a pMO for driving.
The material of the gate oxide film of the SFET 3 is changed from a silicon oxide film to a material having a high dielectric constant such as tantalum oxide so that the gate breakdown voltage of the driving pMOSFET 3 is increased. By taking such means, even if the high power supply voltage Vcc is directly applied between the gate and source (substrate) of the driving pMOSFET 3, the gate oxide film of the driving pMOSFET 3 does not cause dielectric breakdown. ..

Therefore, according to this embodiment, the nMOSFE
In T2, pMOSFET3, nMOSFET4,
The applied voltage between the drain and the source, between the gate and the source, and between the gate and the drain is a voltage (Vcc-Vbe) lower than the power supply voltage Vcc at the maximum except for the applied voltage between the gate and the source of the pMOSFET 3. Therefore, the power supply voltage Vcc is set to nMOSFET2, pMOS
It is possible to select a voltage higher than the withstand voltage (withstand voltage of the MOSFET) determined by the reliability of the FET 3 and the nMOSFET 4 by the voltage Vbe, and a BiN capable of high-speed operation.
A MOS logic circuit can be obtained. Further, in this case, even if the high power supply voltage Vcc is directly applied between the gate and the source (substrate) of the driving pMOSFET 3, by adopting the above means, the driving pMOSFE can be obtained.
Since the gate oxide film of T3 does not cause dielectric breakdown, the gate circuit having high reliability can be obtained.

FIG. 2 is a circuit configuration diagram showing a second embodiment of the gate circuit according to the present invention.

In FIG. 2, 10 is a second npn bipolar transistor, 11 is the npn transistor 10
For driving a second nMOSFET for driving, 12 is a pMOSFET for drawing a second charge for drawing a base charge of the npn transistor 10, and 13 is a third power supply terminal for supplying an arbitrary voltage Va, and The same components as those shown in FIG. 1 are designated by the same reference numerals.

The output stage comprises a first npn transistor 1 and a second npn transistor 10 connected between the output terminal 7 and the second power supply terminal 9, which are totem pole type BiCMOS gates. It constitutes a circuit. Further, in the drive stage, the circuit portion related to the pull-up side of the output stage has a first drive pMOSFET 3 and a diode 5 constituting a constant voltage drop element and a first charge extraction nMOSFET 4 connected in series. Consists of the body,
Similarly, the circuit part related to the pull-down side is the output terminal 7
And a second nPN transistor 10 for driving connected between the bases of the second npn transistor 10 and a second pM for extracting electric charge connected to the base and the third power supply terminal 13.
It is composed of the OSFET 12, and the drive stage has a configuration in which the base bias method is applied to both the pull-up side and the pull-down side of the output stage. In this case, the source of the first nMOSFET 4 for extracting charges is the third power supply terminal 13
The second driving nMOSFET 11 has a drain connected to the output terminal 7 and a source connected to the base of the second npn transistor 10. In the second pMOSFET 12 for extracting charges, the source is connected to the base, the drain is connected to the second power supply terminal 9, and the gate is connected to the output terminal 7. In addition to this, as in the above-described embodiment, although not particularly shown, the first drive pMO is used.
The gate oxide film of SFET3 has the same thickness as that of other MOSF.
ET, that is, the first nMOSFET 4 for extracting charge, the second nMOSFET 11 for driving, and the second pMOSFET 12 for extracting charge, which are thicker than the gate oxide films, or for the first driving Only the gate oxide film of the pMOSFET 3 is replaced with a silicon oxide film and made of a material having a high dielectric constant such as tantalum oxide.

The gate circuit of this embodiment operates as described below.

At the input terminal 6, a positive level is the power supply voltage Vc.
A voltage (Vcc-Vb) lower than the voltage Vbe by the voltage Vbe.
e), an input signal whose negative level is the voltage Vbe is supplied. First, during the positive level period of the input signal, the second driving nMOS is provided in the pull-down side portion of the output stage.
The FET 11 and the second npn transistor 10 are both turned on, the voltage at the output terminal 7 drops to the base-emitter voltage Vbe of the second npn transistor 10, and the output signal becomes the voltage Vbe (negative level). At this time, in the part on the pull-up side of the output stage, the first driving pMOSFET 3 and the second charge extracting pMOS 3
Although both the FETs 12 are turned off, both the first nMOSFET 4 for extracting charges and the diode 5 are turned on, and the voltage at the point A is set to the sum voltage (Vbe + Va) of the voltage Vbe and an arbitrary voltage Va. (However, Vbe ≧ Va).

Next, in the negative level period of the input signal, the first drive pMOSFET 3 is turned on in the pull-up side portion, and the voltage at the point A rises to the power supply voltage Vcc. , The first npn transistor 1 is turned on, and the voltage of the output terminal 7 is the power supply voltage V
The voltage rises to a voltage (Vcc-Vbe) obtained by subtracting the base-emitter voltage Vbe of the first npn transistor 1 from cc, and the output signal becomes a voltage (Vcc-Vbe) (positive level). At this time, in the portion on the pull-up side, both the first nMOSFET 4 and the diode 5 for extracting electric charge are turned off, and there is no influence on the voltage at the point A and the voltage at the output terminal 7. , In the part on the pull-down side, the nMO for the second drive
Both the SFET 11 and the second npn transistor 10 are turned off, and the pMOSFET for the second charge extraction is formed.
12 is turned on, and the voltage at the point B is the voltage Vbe
Is set to a sum voltage (Vbe + Va) of the voltage Va and the voltage Va.

As described above, in this embodiment, the positive level of both the input signal and the output signal is the voltage (Vcc-
Vbe), the negative level is the voltage Vbe, and the output signal has the same level as the input signal and the polarity is inverted. The point A is the power supply voltage V at the positive level.
cc, and at the time of a negative level, the sum voltage (Vbe + V
p) 3 for the first drive because it falls to a).
And between the drain and the source of the first nMOSFET 4 for extracting charges, a voltage of at most {Vcc- (Vbe + V
a)} is only applied. In addition, since the point B rises to the voltage (Vcc-Vbe) at the positive level and drops to the sum voltage (Vbe + Va) at the negative level,
Also between the drain and source of the second nMOSFET 11 for driving and the pMOSFET 12 for second charge extraction,
The maximum voltage {Vcc- (Vbe + Va)} is only applied. Further, the applied voltage between the collector and the emitter of each npn transistor 1 and 10 also becomes a voltage (Vcc-Vbe) lower than the power supply voltage Vcc at the maximum.

In this case, also in this embodiment, each npn
The maximum applied voltage between the collector and the emitter of the transistors 1 and 10 is the above voltage (Vcc-Vbe).
The maximum applied voltage between the drain and source of the OSFETs 3, 4, 11, 12 is the voltage {Vcc- (Vbe + V
a)} and both nMOSFETs
The maximum applied voltage between the gates and sources (substrates) of the p-type MOSFETs 4 and 11 and the substrate (substrate) is the voltage {Vcc- (Vb
e + Va)}, but the applied voltage between the gate and source (substrate) of the first driving pMOSFET 3 is such that the negative level of the output terminal 7 decreases to the voltage Vbe when the second npn transistor 10 is turned on. Therefore, a voltage (Vcc-Vbe) higher than the voltage {Vcc- (Vbe + Va)} by a voltage Va is applied, and the first driving pMOSFET 3 is applied by the application of the high voltage (Vcc-Vbe). Gate oxide film may cause dielectric breakdown.

Therefore, also in this embodiment, as a means for preventing the dielectric breakdown, the first driving pMOSFET 3 is used.
The thickness of the gate oxide film of the other MOSFETs 4, 1
Means for making the gate oxide film thicker than 1 and 12 or the gate oxide film of the first pMOSFET 3 for driving is made of a material having a high dielectric constant such as tantalum oxide instead of the silicon oxide film. By adding a means, the gate breakdown voltage of the first driving pMOSFET 3 is made higher than the others. By adopting the above-mentioned means, even if the high voltage (Vcc-Vbe) is applied between the gate and the source (substrate) of the first driving pMOSFET 3,
The gate oxide film of the driving pMOSFET 3 does not cause dielectric breakdown.

Therefore, according to this embodiment, pMOSFE
T3, nMOSFET 4, nMOSFET 11, pMO
In the SFET 12, the applied voltage between the drain and source, between the gate and source (substrate), and between the gate and drain is the gate and source (substrate) of the pMOSFET 3.
Except for the applied voltage between them, at most the voltage {Vcc-
(Vbe + Va)}, the power supply voltage Vcc
Can be selected by a voltage (Vbe + Va) higher than the withstand voltage (MOSFET withstand voltage) determined by the reliability of each of the MOSFETs 3, 4, 11, and 12, and a BiCMOS gate circuit capable of high-speed operation can be obtained. Can be done. Also, in this case, the pM for the first drive
Even if the high power supply voltage (Vcc-Vbe) is directly applied between the gate and source (substrate) of the OSFET 3, the gate oxide film of the first pMOSFET 3 for driving does not cause dielectric breakdown by the means. The gate circuit having high reliability can be obtained.

FIG. 3 is a sectional view showing an embodiment of a semiconductor device including the transistor 1 on the pull-up side of the output stage and the driving stage thereof in the gate circuit of FIG.

In FIG. 3, 14 is an n-type well region, 1
5 is a p + high impurity concentration drain diffusion layer, 16 is a p + high impurity concentration source diffusion layer, 17 is a gate electrode, 18 is a gate oxide film, 19 is a p-type well region, and 20 is an n + high impurity concentration source diffusion layer. , 21 is a drain diffusion layer of n + high impurity concentration, 22 is a gate electrode, 23 is a gate oxide film, and 24 is a field oxide film. In addition, the same components as those shown in FIG. There is.

Then, a portion including the n-type well region 14, the p + high impurity concentration drain diffusion layer 15, the p + high impurity concentration source diffusion layer 16, the gate electrode 17, and the gate oxide film 18 is used for the first driving. The pMOSFET 3 is constituted, and the p-type well region 19, the n + high impurity concentration source diffusion layer 20, and the n + high impurity concentration drain diffusion layer 2 are formed.
The portion composed of 1, the gate electrode 22, and the gate oxide film 23 constitutes the first nMOSFET 4 for extracting charges. In this case, the thickness of the gate oxide film 18 on the side of the first driving pMOSFET 3 is set to the first nMOSFE for extraction.
The gate oxide film 23 is thicker than T4.

In the above structure, the power supply voltage Vcc supplied to the gate circuit is now set to the first driving pMOSF.
The first npn is higher than the withstand voltage (MOSFET withstand voltage) determined by the reliability of the ET3 and the first pull-out nMOSFET 4.
When the base bias of the transistor 1, that is, the voltage (Vbe + Va) is set high, the first charge extraction is performed between the gate and the source (substrate) of the first driving pMOSFET 3 for the reason described above. NMOSF
A voltage (Vc higher than the maximum voltage {Vcc- (Vbe + Va)} applied between the gate and source (substrate) of ET4.
c-Vbe) may be applied, but in the present embodiment, the thickness of the gate oxide film 18 of the first driving pMOSFET 3 is set to the first nMOSFET 4 for extracting charge.
Since the gate oxide film 23 is thicker than the gate oxide film 23, the gate withstand voltage and the TDDB withstand voltage of the first driving pMOSFET 3 can be sufficiently secured.
Therefore, the power supply voltage Vcc of the gate circuit is set to the MOSF.
It is possible to set the voltage higher than the withstand voltage of ET by the voltage (Vbe + Va), which allows the gate circuit to operate at high speed.

In the above case, the first drive pMOSFE is used.
The thickness of the gate oxide film 18 at T3 depends on the power supply voltage Vcc of 2
When set to about V, another MOSFET, that is, the first MOSFET
It is preferable to select about 1.5 times the thickness of the gate oxide film 23 of the nMOSFET 4 for extracting electric charges.

In general, if the gate oxide film of the MOSFET is made thicker, its gate capacitance becomes smaller and the drain current for the same input becomes smaller. However, in the case of this embodiment, the first driving pMOSFET 3 is used. Even if the thickness of the gate oxide film 18 is increased, the high voltage (Vcc-Vb) is applied between the gate and the source (substrate).
e) is applied, the first driving pMOSFET
The drain current flowing through 3 does not become small.

Here, the first driving pMOSF
The thickness of the gate oxide film 18 of ET3 is set to other MOSFE
T, that is, a means for increasing the thickness of the gate oxide film 23 of the first nMOSFET 4 for charge extraction, one means is, first, for all MOSFs.
A gate oxide film of the same thickness is formed for ET, and then another MO except for the first driving pMOSFET 3 is formed.
SFET, that is, nMOSFET 4 for first charge extraction
Of the gate oxide film 23 is covered with a nitride film, and then an oxide film is additionally formed in the region of the gate oxide film 18 of the first pMOSFET 3 for driving, and the other means is as follows. First driving pMOSFET 3 and first
Is a means for forming one of the nMOSFETs 4 for extracting electric charge, then covering the formed MOSFET with an insulator such as an oxide film, and then forming the other MOSFET, and various other means. The means of can be considered.

Further, the thickness of the gate oxide film 18 of the first driving pMOSFET 3 is set to be the same as the nMO for the first charge extraction.
Instead of making the thickness of the gate oxide film 23 of the SFET 4 different, the gate oxide film 18 of the first pMOSFET 3 for driving has a dielectric constant higher than that of the other MOSFET, that is, the gate oxide film 23 of the nMOSFET 4 for first charge extraction. Even if it is formed of a material having a high ratio, the same effect as the above effect can be obtained. The reason for this is that when a material having a high dielectric constant is used for the gate oxide film 18, the thickness of the gate oxide film 18 required to obtain the same gate capacitance becomes large, so that the gate oxidation of the first pMOSFET 3 for driving is increased. The thickness of the film 18 is set to be different from that of another MOSFET, that is, the first nMOSF for charge extraction.
Even if the gate oxide film 23 of the ET4 is thicker than the gate oxide film 23, its gate capacitance can be made approximately the same as the gate capacitance of the first nMOSFET 4 for charge extraction. Then, in this case, the drain current can be increased by the amount of the applied voltage between the gate and the source (substrate) of the first nMOSFET 4 for extracting charges, and the gate circuit can be operated at a higher speed. It will be possible.

Next, FIG. 4 is a circuit configuration diagram showing a third embodiment of the gate circuit according to the present invention.

In FIG. 4, 25 is a second pnp bipolar transistor, and 26 is a second driving nMOSFE.
T and 27 are pMOSFETs for pulling out a second charge, 28 is a diode which constitutes a second constant voltage drop element, 29 is a fourth power supply terminal, and is otherwise the same as the components shown in FIGS. 1 and 2. The components are given the same reference numerals.

The output stage is composed of the first npn transistor 1 and the second npn transistor 2 connected between the output terminal 7 and the ground terminal 9.
Pnp transistor 25 of the above, and these are CBiCMO using complementary bipolar transistors 1 and 25.
It constitutes an S gate circuit. In the drive stage, the pull-up side portion of the output stage is the first pMOSFE for drive.
T3 and diode 5 that constitutes a constant voltage drop element
And a first nMOSFET 4 for extracting charges, which is connected in series, and the same pull-down side portion is connected between the fourth power supply terminal 29 and the base of the second pnp transistor 25 for extracting second charges. It comprises a series connection of a pMOSFET 27 and a diode 28, and a second driving nMOSFET 26 connected between the base and the ground terminal 9, and the driving stage is on both the pull-up side and the pull-down side of the output stage. It has a configuration to which the base bias method is applied. In this case, the second pnp transistor 25
Has an emitter connected to the output terminal 7 and a collector connected to the ground terminal 9, and has a second driving nMOSFET 26.
Has a drain connected to the base and a source connected to the ground terminal 9. Second pMOSF for charge extraction
The ET 27 has a source connected to the fourth power supply terminal 29 and a drain connected to the anode of the diode 28.

Regarding the operation of this embodiment, the structure of the drive stage for driving the pull-up side portion of the output stage is the same as that of the second embodiment described above, so that the operation of the above-mentioned portion will be described. The description is omitted, and here, the operation of the drive stage that drives the pull-down side portion of the output stage will be described.

A positive level is applied to the input terminal 6 by the power supply voltage Vc.
A voltage (Vcc-Vb) lower than the voltage Vbe by the voltage Vbe.
e), an input signal whose negative level is the voltage Vbe is supplied. First, during the positive level period of the input signal, the second driving nMOSFET 26 is turned on and the voltage at the point B drops to the ground voltage, so that the second pnp transistor 25 is turned on and the output terminal The voltage of 7 is the second p
Base-emitter voltage Vbe of np transistor 25
And the output signal becomes the voltage Vbe (negative level). At this time, the second pMOSFET 27 for extracting charges
And the diode 28 are both off,
The voltage at the point is maintained at ground potential.

Next, in the negative level period of the input signal, the second driving nMOSFET 26 is turned off and the second pnp transistor 25 is also turned off accordingly. PMOSFET 27 for extraction
And the diode 28 are both turned on, and the voltage at the point B is the supply voltage (Vcc-V) of the fourth power supply terminal 29.
It is set to a voltage obtained by subtracting the voltage Vbe from a), that is, a voltage {Vcc- (Vbe + Va)} (however,
Again, Vbe ≧ Va).

As described above, also in this embodiment, the positive level of the input signal and the output signal is the voltage (Vcc-).
Vbe), the negative level is the voltage Vbe, and the output signal has the same level as the input signal and the polarity is inverted. As described in the second embodiment, the point A rises to the power supply voltage Vcc at the positive level,
Since it drops to the sum voltage (Vbe + Va) at the negative level, between the drain and source of the first driving pMOSFET 3 and the first charge extracting nMOSFET 4,
At most, the voltage {Vcc- (Vbe + Va)} is only applied. Further, the point B rises to the voltage {Vcc- (Vbe + Va)} at the positive level and drops to the ground voltage at the negative level, so that the nMO for the second drive is formed.
SFET 26 and second pMOSFET 2 for extracting charge
The maximum voltage between each drain and source of 7 is {Vcc
Only-(Vbe + Va)} is applied. In addition, the collectors of the first and second transistors 1 and 25
The maximum applied voltage between the emitters is also a voltage (Vcc-Vbe) lower than the power supply voltage Vcc.

In this case, also in the present embodiment, the applied voltage between the collector and the emitter of the first and second transistors 1 and 25 is the maximum voltage (Vcc-Vbe), and the MOSFETs 3, 4, and 26 are the same. , 27, the applied voltage between the drain and the source is at most the voltage {Vcc- (V
be + Va)}, and the maximum applied voltage between the gate and source (substrate) of the first and second MOSFETs 4 and 27 for charge extraction is (Vcc−).
(Vbe + Va)}.

However, the first driving pMOSFET
The voltage applied between the gate and the source (substrate) of No. 3 drops to the voltage Vbe when the output voltage of the output terminal 7 is at a negative level, and the voltage applied between the gate and the source (substrate) of the second driving nMOSFET 26 is The voltage (Vcc-Vbe) higher than the voltage {Vcc- (Vbe + Va)} by the voltage Va is applied to the voltage because the output voltage of the output terminal 7 rises to the voltage (Vcc-Vbe) at the positive level. Like Therefore, the high voltage (Vcc-Vb)
e) application of first and second driving MOSFETs
The gate oxide films 3 and 26 may cause dielectric breakdown.

Therefore, also in this embodiment, as means for preventing the dielectric breakdown, the first and second MOSFs for driving are used.
The gate oxide film of ET3, 26 has the same thickness as that of other MOS.
Means for configuring the FETs 4 and 27 to be thicker than the thickness of the gate oxide film, or the first and second driving MOSFs
First and second MOSFETs for driving are adopted by adopting a means of replacing the gate oxide film of ET3, 26 with a silicon oxide film and using a material having a high dielectric constant such as tantalum oxide.
Since the gate breakdown voltage of each of the transistors 3 and 26 is set higher than the others, the high voltage (Vcc-Vb) is applied between the gate and the source (substrate) of the first and second driving MOSFETs 3 and 26.
Even if e) is applied, those gate oxide films do not cause dielectric breakdown.

Therefore, also in this embodiment, the pMOSF
ET3, nMOSFET4, nMOSFET26, pM
In the OSFET 27, the applied voltages between the drain and source, between the gate and source (substrate), and between the gate and drain are pMOSFET 3 and nMOSFET 26.
Except for the applied voltage between the gate and source (substrate) of the above, the maximum voltage is only the voltage {Vcc- (Vbe + Va)}.
Withstand voltage (MOS
It is possible to select a voltage higher than the FET withstand voltage) by the above voltage (Vbe + Va), and CBiC capable of high-speed operation can be selected.
A MOS gate circuit can be obtained. Further, in this case, even if the high power supply voltage (Vcc-Vbe) is directly applied between the gate and the source (substrate) of the first driving pMOSFET 3 or the second driving nMOSFET 26, the first means can be used. Since the gate oxide film of the driving pMOSFET 3 or the second driving nMOSFET 26 does not cause dielectric breakdown, the gate circuit having high reliability can be obtained.

Next, FIG. 5 is a circuit configuration diagram showing a fourth embodiment of the gate circuit according to the present invention.

In FIG. 5, the same components as those shown in FIG. 4 are designated by the same reference numerals.

In this embodiment, the source of the first nMOSFET 4 for charge extraction is the third power supply terminal 13 in the third embodiment, and the source of the second pMOSFET 27 for charge extraction is the same as the third embodiment. Are connected to the output terminal 7 instead of being respectively connected to the fourth power supply terminal 29,
As in the third embodiment, the output stage is a CBiCMOS.
The gate circuit is configured, and the base bias method is applied to both the drive stages on the pull-up side and the pull-down side of the output stage.

The operation of this embodiment is the same as that of the above-described fourth embodiment except that the voltage Vbe obtained at the output terminal 7 is used instead of the voltage Va in the above-mentioned fourth embodiment. Since the operation is almost the same, further detailed description will be omitted.

Also in this embodiment, both the input signal and the output signal have the positive level of the voltage (Vcc-Vbe) and the negative level of the voltage Vbe, and the output signal has the same level as the input signal, and The polarity will be reversed. Since the point A rises to the power supply voltage Vcc at the positive level and drops to 2Vbe at the negative level, the drain-source between the first driving pMOSFET 3 and the first charge extracting nMOSFET 4 is increased. Is only applied with a voltage (Vcc-2Vbe) at maximum.
Further, the point B has the voltage (Vcc-2 at the positive level).
Since the voltage rises to Vbe) and drops to the ground voltage at a negative level, the maximum voltage (Vcc-2Vbe) is also applied between the drain and source of the second driving nMOSFET 26 and the second charge extracting pMOSFET 27. Is only applied. Furthermore, the first and second transistors 1,
The maximum applied voltage between the collector and the emitter of 25 is also a voltage (Vcc-Vbe) lower than the power supply voltage Vcc.

In this case, also in this embodiment, the applied voltage between the collector and the emitter of the first and second transistors 1 and 25 is the above voltage (Vcc-Vbe) at the maximum, and the MOSFETs 3, 4, and 26 are the same. The maximum voltage applied between the drain and source of
be), and the applied voltage between the gate and the source (substrate) of the first and second MOSFETs 4 and 27 for charge extraction is at most the voltage (Vcc-2Vb).
Although it can be suppressed to e), pM for the first drive
The applied voltage between the gate and the source (substrate) of the OSFET 3 drops to the voltage Vbe when the output voltage of the output terminal 7 is at the negative level, and the second driving nMOSFET 26
The voltage applied between the gate and source (substrate) of the
Rises to the voltage (Vcc-Vbe) at the positive level of the output voltage of each of the output voltages (Vcc-2Vbe).
A voltage (Vcc-Vbe) higher than the voltage Vbe is applied, and this higher voltage (Vcc-Vbe) is applied.
May cause dielectric breakdown in the gate oxide film of the first driving pMOSFET 3 or the second driving nMOSFET 26.

Therefore, also in this embodiment, as a means for preventing the dielectric breakdown, the first driving pMOSFET 3 is used.
And the gate oxide film of the second driving nMOSFET 26 has the same thickness as that of another MOSFET, that is, the first charge extracting nMOSFET 4 and the second charge extracting pMO.
A means for making the gate oxide film thicker than that of the SFET 27, or replacing the gate oxide films of the first driving pMOSFET 3 and the second driving nMOSFET 26 with a silicon oxide film, a high dielectric constant such as tantalum oxide is used. By adopting a means composed of a material that has, p for the first drive
MOSFET 3 and nMOSFET 26 for second driving
Gate withstand voltage is higher than others. By adopting the above means, even if the high voltage (Vcc-Vbe) is applied between the gate and the source (substrate) of the first driving pMOSFET 3 and the second driving nMOSFET 26, these gate oxide films are insulated. Does not cause destruction.

Therefore, according to this embodiment, pMOSFE
T3, nMOSFET4, nMOSFET26, pMO
In the SFET 27, the applied voltage between the drain and the source, between the gate and the source (substrate), and between the gate and the drain is the maximum voltage except the applied voltage between the gate and the source (substrate) of the pMOSFET 3 and the nMOSFET 26. Since it is only (Vcc-2Vbe), it is possible to select the power supply voltage Vcc higher than the withstand voltage (the MOSFET withstand voltage) determined by the reliability of each MOSFET 3, 4, 26, 27 by the voltage 2Vbe. A CBiCMOS gate circuit that can operate at high speed can be obtained. Further, in this case, the first driving pMOSFE
T3 and the gate of the nMOSFET 26 for the second drive
The high power supply voltage (Vcc-Vb) is applied between the sources (substrates).
Even if e) is directly applied, the gate oxide film does not cause dielectric breakdown by the means, so that the gate circuit having high reliability can be obtained.

Further, FIG. 6 is a circuit configuration diagram showing a fifth embodiment of the gate circuit according to the present invention.

In FIG. 6, 30 is the first nMOSFE.
T and 31 are nMOSFETs for extracting electric charge, 32 is an nMOSFET forming a constant voltage drop element, and
The same components as those shown in FIG. 1 are designated by the same reference numerals.

The output stage includes a first nMOSFET 30 connected between the first power supply terminal 8 and the output terminal 7,
The second n connected between the output terminal 7 and the second power supply terminal 9
It is composed of a MOSFET 2, and these constitute a MOS gate circuit. Further, in the driving stage, the circuit portion related to the pull-up side of the output stage is the pMOSFET for the first driving.
3 and nMOSFET forming a constant voltage drop element
32 and a nMOSFET 31 for extracting charges, which is connected in series, has a structure in which the base bias method is applied to the drive stage on the pull-up side of the output stage, as in the first embodiment. In this case, the first nMOSFET 30
Has a drain connected to the first power supply terminal 8 and a source connected to the output terminal 7. NM for the first charge extraction
The OSFET 31 has a drain connected to the source of the nMOSFET 32 and a source connected to the ground terminal 9,
The drain of the OSFET 32 is the first nMOSFET 30.
Connected to the gate.

In the operation of this embodiment, the voltage Vbe is generated by the nMOSFET 32 (where Vth is the threshold voltage of the nMOSFET) instead of the voltage Vbe generated by the diode 5 in the first embodiment. The operation is almost the same as that of the above-described first embodiment except that it is performed, and thus the detailed description thereof will be omitted.

In this embodiment, both the input signal and the output signal have a positive level of voltage (Vcc-Vth) and a negative level of the ground voltage, and the output signal has the same level as the input signal. , The polarity is reversed.
Then, the point A rises to the power supply voltage Vcc at the positive level and drops to the voltage Vth at the negative level, so that between the drain and source of the first driving pMOSFET 3 and the charge extracting nMOSFET 31. , The voltage (Vcc-Vth) is only applied at the maximum.
Further, the applied voltage between the drain and the source of the first and second nMOSFETs 30 and 2 is a voltage (Vcc-Vth) lower than the power supply voltage Vcc at the maximum.

In this case, also in this embodiment, the applied voltage between the drain and the source of the first and second nMOSFETs 30 and 2 is the above-mentioned voltage (Vcc-Vth) at the maximum, and the voltage applied to each of the MOSFETs 3, 31 and 32. The maximum voltage applied between the drain and source is the voltage (Vcc-Vth).
NMOSF for charge extraction
The applied voltage between the gate and the source (substrate) of the ET31 can be suppressed to the above voltage (Vcc-2Vth) at the maximum, but the gate of the first driving pMOSFET 3 is
Between the sources (substrates), the output voltage of the output terminal 7 drops to the ground voltage at the negative level, so that the voltage (V
The power supply voltage Vcc higher than cc-Vth) is applied as it is, and the application of this high voltage Vcc may cause dielectric breakdown of the gate oxide film of the first driving pMOSFET 3.

Therefore, also in this embodiment, as a means for preventing the dielectric breakdown, the first driving pMOSFET 3 is used.
The thickness of the gate oxide film of the other MOSFET is the same as that of other MOSFETs, that is, the nMOSFET 31 and nMOSFET for charge extraction.
32, a means for making the gate oxide film thicker than 32, or a means for replacing the gate oxide film of the first driving pMOSFET 3 with a silicon oxide film and using a material having a high dielectric constant such as tantalum oxide. However, the gate breakdown voltage of the first driving pMOSFET 3 is set higher than the others. By adopting the above means, the p for the first drive is
Even if the high voltage Vcc is applied between the gate and source (substrate) of the MOSFET 3, the gate oxide film does not cause dielectric breakdown.

Therefore, according to this embodiment, pMOSFE
In the T3 and the nMOSFETs 31 and 32, the applied voltage between the drain and the source, between the gate and the source (substrate), and between the gate and the drain is the maximum except for the applied voltage between the gate and the source (substrate) of the pMOSFET 3. Since it is only the voltage (Vcc-Vth), the power supply voltage V
It becomes possible to select cc higher than the breakdown voltage (breakdown voltage of MOSFET) determined by the reliability of each MOSFET 3, 31, 32 by the voltage Vth, and a MOS gate circuit capable of high-speed operation can be obtained. Further, in this case, even if the high power supply voltage Vcc is directly applied between the gate and the source (substrate) of the first driving pMOSFET 3, the gate oxide film does not cause dielectric breakdown by the means. The gate circuit having high reliability can be obtained.

By the way, in this embodiment, all the elements are MO
Although it is composed of SFET, such a structure will be developed in the future with the miniaturization technology of MOSFET,
When there is no difference in the driving force between the bipolar transistor and the MOSFET, forming the circuit with only the MOSFET does not impair the high speed operation, and the number of process steps in manufacturing is smaller than that using the bipolar transistor. It is excellent in that it can be reduced. Further, when the first nMOSFET 30 is used in the output stage, the input capacitance is kept small and the first nMOSFET 30 is used.
Since the size of can be increased, there is also an advantage that load dependency is improved.

The first nMOSFET 30 and nM
In both OSFETs 32, the well (substrate) is connected to the source, but this is due to the substrate bias effect.
This is to prevent the threshold voltage Vth from increasing.

In each of the above-described embodiments, nM is used instead of the first npn bipolar transistor 1 in the output stage.
The OSFET may be used, and the second p
Instead of np bipolar transistor 14, pMOS
You may make it use FET.

Further, in each of the above-mentioned embodiments, the example of the inverter circuit has been explained as the gate circuit. However, the present invention is not limited to the above-mentioned inverter circuit, and a multi-input NAND
It goes without saying that the same can be applied to the circuit and the multi-input NOR circuit.

[0079]

As described above, according to the present invention,
When the base bias method is applied to the drive stage of the gate circuit, the forward voltage between the base and emitter of the transistor is V
be, the threshold voltage of the MOSFET is Vth, and an arbitrary voltage is Va (Vbe ≧ Va), the power supply voltage Vcc of the gate circuit is higher than the withstand voltage (withstand voltage of the MOSFET) determined by the reliability of the MOSFET. , Vbe, V
Since either be + Va or Vth can be increased to some extent, there is an effect that a gate circuit capable of high-speed operation can be obtained even if a MOSFET having a breakdown voltage of 2 V or less is used.

According to the present invention, the M used when the base bias method is applied to the driving stage of the gate circuit.
Among the OSFFETs, particularly those in which a voltage higher than that of other MOSFFETs is applied between the gate and the source (substrate), are the gate oxide film thicknesses of the MOSFFETs made thicker than those of other MOSFFETs? Alternatively, since the gate oxide film of the MOSFFET is made of a material having a high dielectric constant such as tantalum oxide instead of the silicon oxide film, the gate
Even if the high voltage is applied between the sources (substrates), there is an effect that a highly reliable gate circuit can be obtained without dielectric breakdown of the oxide film.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of a gate circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing a second embodiment of the gate circuit according to the present invention.

FIG. 3 is a sectional configuration diagram showing an embodiment of a semiconductor device according to the present invention.

FIG. 4 is a circuit configuration diagram showing a third embodiment of the gate circuit according to the present invention.

FIG. 5 is a circuit configuration diagram showing a fourth embodiment of the gate circuit according to the present invention.

FIG. 6 is a circuit configuration diagram showing a fifth embodiment of the gate circuit according to the present invention.

[Explanation of symbols]

 1 first npn bipolar transistor 2 second nMOSFET 3 first driving pMOSFET 4, 31 first charge extracting nMOSFET 5 diode 1 constituting constant voltage drop element 6 signal input terminal 7 signal output Terminal 8 First power supply terminal 9 Second power supply terminal (ground terminal) 10 Second npn bipolar transistor 11, 26 nMOSFET for second driving 12 nMOSFET for second charge extraction 13 Third power supply terminal 14 n type well region 15 p + high impurity concentration drain diffusion layer 16 p + high impurity concentration source diffusion layer 17, 22 gate electrode 18, 23 gate oxide film 19 p type well region 20 n + high impurity concentration source diffusion layer 21 n + high Drain diffusion layer with impurity concentration 24 Field oxide film 25 Second pnp bipolar nMOSFET constituting the transistor 27 second pMOSFET 28 for charge extraction of the second constant voltage drop diode 29 fourth constituting the elements of the power supply terminal 30 first nMOSFET 32 constant voltage drop element

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Makoto Suzuki 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor, Atsio Watanabe 2362, Imai, Ome, Tokyo Hitachi, Ltd. Device Development In the Center (72) Inventor Takahiro Nagano 1-280, Higashi Koigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (14)

[Claims] 1. A load comprising a first element connected between one power supply terminal and an output terminal and a second element connected between the output terminal and the other power supply terminal, wherein a load connected to the output terminal is provided. An input stage of the first element and / or the second element, which comprises an output stage to be driven, and at least an insulating gate type FET for driving and a series connection body of a constant voltage drop element and an insulated gate type FET for charge extraction. In a gate circuit having a driving stage connected to an electrode, the conductivity type of the driving insulated gate type FET and the insulating gate type FE for extracting the charge
The conductivity types of T are complementary to each other, and the thickness of the gate insulating film of the driving insulated gate FET is different from the thickness of the gate oxide film of the charge extracting insulated gate FET. Characteristic gate circuit. 2. The gate circuit according to claim 1, wherein the first element is a bipolar transistor, and the second element is an insulated gate FET. 3. The gate circuit according to claim 1, wherein the first element and the second element are bipolar transistors of the same conductivity type. 4. The gate circuit according to claim 1, wherein the first element and the second element are complementary conductivity type bipolar transistors. 5. The gate circuit according to claim 1, wherein the first element and the second element are insulated gate FETs of the same conductivity type. 6. The thickness of the gate oxide film of the driving insulated gate FET is the same as that of the charge extraction insulated gate FET.
6. The gate circuit according to claim 1, wherein the gate circuit is thicker than the gate oxide film. 7. A load connected to the output terminal, comprising a first element connected between the one power supply terminal and the output terminal and a second element connected between the output terminal and the other power supply terminal. An input stage of the first element and / or the second element, which comprises an output stage to be driven, and at least an insulating gate type FET for driving In a gate circuit having a drive stage connected to an electrode, the conductivity type of the driving insulated gate FET and the insulated gate FE for extracting the charge
The conductivity type of T is complementary to each other, and the material of the gate oxide film of the driving insulated gate FET and the material of the gate oxide film of the charge extracting insulated gate FET are different. Characteristic gate circuit. 8. The gate circuit according to claim 7, wherein the first element is a bipolar transistor, and the second element is an insulated gate FET. 9. The gate circuit according to claim 7, wherein the first element and the second element are bipolar transistors of the same conductivity type. 10. The gate circuit according to claim 7, wherein the first element and the second element are complementary conductivity type bipolar transistors. 11. The gate circuit according to claim 7, wherein the first element and the second element are insulated gate FETs of the same conductivity type. 12. The dielectric constant of the material of the gate oxide film of the insulating gate type FET for driving is selected to be higher than the dielectric constant of the material of the gate oxide film of the insulating gate type FET for charge extraction. The gate circuit according to claim 7, wherein the gate circuit is a gate circuit. 13. An n and p well region disposed adjacent to each other, the p well region, a pair of high impurity concentration n + source and drain regions provided above the p well region, and the n + source. And a gate electrode disposed on the surface of the p-well region between the drain region and the first insulating layer via a first insulating gate type FE
T and the n well region, a pair of high impurity concentration p + source and drain regions provided above the n well region, and the n between the p + source and drain regions.
Second insulated gate FET composed of a gate electrode arranged on the surface of the well region with a second insulating layer interposed therebetween
And the first and second insulated gate FETs are
In a semiconductor device having mutually complementary conductivity types and forming a drive stage of a gate circuit, the first insulating layer and the second insulating layer have different thicknesses. Semiconductor device. 14. An n and p well region, which are arranged adjacent to each other, said p well region, a pair of high impurity concentration n + source and drain regions provided above said p well region, and said n + source. And a gate electrode disposed on the surface of the p-well region between the drain region and the first insulating layer via a first insulating gate type FE
T and the n well region, a pair of high impurity concentration p + source and drain regions provided above the n well region, and the n between the p + source and drain regions.
Second insulated gate FET composed of a gate electrode arranged on the surface of the well region with a second insulating layer interposed therebetween
And the first and second insulated gate FETs are
In a semiconductor device having conductivity types complementary to each other and forming a driving stage of a gate circuit, a material of the first insulating layer and a material of the second insulating layer are different from each other. Semiconductor device.