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JPH05251584A - Manufacture of ceramic chip carrier - Google Patents

Manufacture of ceramic chip carrier

Info

Publication number
JPH05251584A
JPH05251584A JP4853892A JP4853892A JPH05251584A JP H05251584 A JPH05251584 A JP H05251584A JP 4853892 A JP4853892 A JP 4853892A JP 4853892 A JP4853892 A JP 4853892A JP H05251584 A JPH05251584 A JP H05251584A
Authority
JP
Japan
Prior art keywords
hole
conductor
chip carrier
ceramic
cupric oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4853892A
Other languages
Japanese (ja)
Inventor
Yoshifumi Nakamura
嘉文 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4853892A priority Critical patent/JPH05251584A/en
Publication of JPH05251584A publication Critical patent/JPH05251584A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE:To prevent shortcircuit with ant adjacent through-hole and to divide a ceramic substrate without pulling a conductor to one side to cause breakage at a through-hole part or without generating cracks by applying cupric oxide paste of low viscosity whose volume is larger than that of copper to a through- hole which becomes a side electrode. CONSTITUTION:A green sheet wherein conductor print and via burying are carried out is thermo-compressed and laminated to form a through-hole. It is notched to connect each through-hole if necessary. Cupric oxide-based conductor paste is printed on the inner wall of a through-hole to form a conductor layer 35A. A lamination wherein print is performed is unbound and burnt in nitrogen atmosphere. A scribe line 41 is formed on a through-hole of the burnt substrate and the substrate is divided into pieces. Since cupric oxide paste applied to a through-hole is deoxidized and becomes a thin conductor film after burnt, a ceramic substrate can be divided into pieces without generating cracks, etc.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体LSI、チップ部
品などを搭載し、かつそれらを相互配線するためのセラ
ミックチップキャリアの製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a ceramic chip carrier for mounting semiconductor LSIs, chip parts and the like and interconnecting them.

【0002】[0002]

【従来の技術】配線基板上の実装密度を高めるために
も、フラケットパッケージタイプICに対してリードレ
スタイプにした図3の斜視図に示すようなセラミックチ
ップキャリヤタイプのパッケージICがある。図3にお
いて、31はサイド電極、32は配線基板、33は電極パッ
ド、34はチップキャリアである。これはパッケージIC
の裏面に半田付け可能な電極パッド33が引出されてお
り、これを配線基板32の導体面に直接半田付して接続す
るものである。
2. Description of the Related Art In order to increase the mounting density on a wiring board, there is a ceramic chip carrier type package IC as shown in the perspective view of FIG. In FIG. 3, 31 is a side electrode, 32 is a wiring substrate, 33 is an electrode pad, and 34 is a chip carrier. This is a packaged IC
An electrode pad 33 that can be soldered is drawn out on the back surface of the wiring board, and is directly connected to the conductor surface of the wiring board 32 by soldering.

【0003】このタイプのパッケージICは配線基板32
上の実装面積を従来の同数ピンのデップDIPの約1/
3以下にすることができ、フラットパッケージタイプの
ICより高密度の実装ができる。また、組み込みや交換
も容易であり、軽量でもある。チップキャリア34用とし
てセラミック基板が一般的である。
This type of packaged IC has a wiring board 32.
The mounting area above is about 1 / th that of the conventional DIP DIP with the same number of pins
The number can be set to 3 or less, and mounting can be performed at a higher density than that of a flat package type IC. It is also easy to install and replace, and is lightweight. A ceramic substrate is generally used for the chip carrier 34.

【0004】そこで配線基板32とチップキャリヤ34とを
接続するサイド電極31の製造方法の一例を述べる。先ず
焼成前の無機組成物よりなるグリーンシートの積層体上
で個片にするチップキャリヤ34のセラミック基板外形部
に沿ってスルーホール35を空け、穴の空いた積層体を作
製する。次にそのチップキャリヤ34のセラミック基板を
焼成する。チップチャリヤ34のセラミック基板のスルー
ホール35上に銅等の導体ペーストを下から吸引しながら
印刷しスルーホールの内壁に導体(スルーホール導体層)
を形成する。しかしこれではスルーホールの内壁が完全
に導体で塗れないので焼成した後、裏面からもスルーホ
ール内に導体ペーストを下から吸引しながら印刷し、ス
ルーホールの内壁を導体で完全に塗り焼成する。スルー
ホールの中央(スクライブライン)で分割することで側面
に導体(サイド電極31)を有するチップキャリヤ34のセラ
ミック基板を製造することができる。
Therefore, an example of a method of manufacturing the side electrode 31 for connecting the wiring board 32 and the chip carrier 34 will be described. First, a through hole 35 is formed along the outer shape of the ceramic substrate of the chip carrier 34 to be separated into individual pieces on the green sheet laminated body made of the inorganic composition before firing, to form a perforated laminated body. Next, the ceramic substrate of the chip carrier 34 is fired. Conductor is printed on the through hole 35 of the ceramic substrate of the chip carrier 34 while sucking a conductive paste such as copper from the bottom, and the conductor is formed on the inner wall of the through hole (through hole conductor layer)
To form. However, in this case, since the inner wall of the through hole cannot be completely coated with the conductor, the inner wall of the through hole is completely coated with the conductor after firing by firing while drawing the conductor paste into the through hole from the back side. The ceramic substrate of the chip carrier 34 having the conductor (side electrode 31) on the side surface can be manufactured by dividing the through hole at the center (scribe line).

【0005】[0005]

【発明が解決しようとする課題】上述した製造方法によ
ると次のような問題が明らかとなった。図4は上述した
従来のセラミックチップキャリヤタイプのサイド電極部
の破断面を示す斜視図であり、作製したチップキャリヤ
34のセラミック基板30をスクライブライン41に沿って個
片に分割し、図3に示すチップキャリヤ34とするとき、
スルーホール35の導体(スルーホール導体層35A)の厚み
が厚くなっているような所では、図4に示すようにスク
ライブライン41で破断されず、導体(スルーホール導体
層35A)が片方(図4では右方)に引っ張られ、セラミッ
ク部30Aは破断部30Bに示すような位置にて破断され半
円筒形のサイド電極31が形成されず、また、電極パッド
33が一方に残ったりセラミック基板30にクラックが入る
という問題があった。
According to the above-mentioned manufacturing method, the following problems have become clear. FIG. 4 is a perspective view showing a fracture surface of a side electrode portion of the above-mentioned conventional ceramic chip carrier type.
When the ceramic substrate 30 of 34 is divided into individual pieces along the scribe line 41 to form the chip carrier 34 shown in FIG. 3,
At a place where the conductor of the through hole 35 (through hole conductor layer 35A) is thick, one conductor (through hole conductor layer 35A) is not broken at the scribe line 41 as shown in FIG. 4 in the right direction), the ceramic portion 30A is fractured at the position shown by the fracture portion 30B, and the semi-cylindrical side electrode 31 is not formed.
There was a problem that 33 remained on one side and the ceramic substrate 30 was cracked.

【0006】また、焼成後分割を容易にするために焼成
前のセラミック基板にノッチをいれる工程を追加した場
合、ノッチをいれた焼成後のセラミック基板に導体ペー
ストを下から吸引しながら印刷したとき、ノッチの溝に
導体が流れショートを起こす。
In addition, when a step of adding a notch to the ceramic substrate before firing is added to facilitate the division after firing, when printing is performed while sucking the conductor paste from below onto the fired ceramic substrate with the notch. , Conductor flows into the notch groove, causing a short circuit.

【0007】本発明は上述した従来の問題を解決し、チ
ップキャリヤの多数個取りを目的としたセラミック基板
を個片に分割するとき、スルーホール部で導体が片方に
引っ張られ剥がれたり、クラックが入ることをなくし、
また焼成前のスルーホール部に酸化第二銅ペーストを印
刷するので導体がノッチ溝に流れ、隣のスルーホールと
ショートを起こすことをなくすことを目的とするもので
ある。
The present invention solves the above-mentioned conventional problems, and when a ceramic substrate for the purpose of obtaining a large number of chip carriers is divided into individual pieces, the conductor is pulled to one side at the through-hole portion and peeled or cracked. I wo n’t go in,
Further, since the cupric oxide paste is printed on the through holes before firing, the purpose is to prevent the conductor from flowing into the notch groove and causing a short circuit with the adjacent through hole.

【0008】[0008]

【課題を解決するための手段】本発明は、少なくとも酸
化第二銅を主成分とするペーストを印刷したグリーンシ
ートを所望枚数積層し、この後この積層体にスルーホー
ルを形成し、前記積層体の両面及び片面にある酸化第二
銅を主成分とするペーストを吸引しながら、配線パター
ン及びスルーホールの内壁に導体を印刷する。この印刷
済み積層体を脱バインディングし、還元熱処理を行い、
窒素雰囲気中で焼成し作ったセラミック基板とスルーホ
ールを分割するようにブレイクして製造する。
According to the present invention, a desired number of green sheets printed with a paste containing at least cupric oxide as a main component are laminated, and then a through hole is formed in the laminated body. A conductor is printed on the inner wall of the wiring pattern and the through hole while sucking the paste containing cupric oxide as the main component on both sides and one side. This printed laminated body is debound, subjected to reduction heat treatment,
It is manufactured by breaking so as to divide the ceramic substrate and the through hole, which are made by firing in a nitrogen atmosphere.

【0009】[0009]

【作用】本発明によるとサイド電極となるべきスルーホ
ールに粘度が低く銅より体積の大きい酸化第二銅ペース
トの状態で塗布するので、焼成後、還元されて体積の小
さい銅となり薄い導体膜ができる。そのため分割がしや
すくなる。
According to the present invention, the through-holes to be the side electrodes are applied in the form of cupric oxide paste having a low viscosity and a volume larger than that of copper. Therefore, after firing, it is reduced to copper having a small volume to form a thin conductor film. it can. Therefore, it becomes easy to divide.

【0010】[0010]

【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0011】基板組成セラミック粉を無機成分とし、有
機バインダとしてポリビニルブチラール、可塑剤として
ジ−n−ブチルフタレート、溶剤としてトルエンとイソ
プロピルアルコールの混合液(30対70重量比)を混合しス
ラリーとした。このスラリーをドクターブレード法で有
機フィルム上にグリーンシート成形した。この時、造膜
から乾燥、打ち抜きを行う各工程を連続的に行うシステ
ムを使用した。
The substrate composition ceramic powder was used as an inorganic component, polyvinyl butyral as an organic binder, di-n-butyl phthalate as a plasticizer, and a mixed solution of toluene and isopropyl alcohol (30:70 weight ratio) as a solvent was mixed to form a slurry. .. This slurry was formed into a green sheet on an organic film by the doctor blade method. At this time, a system was used in which each step of drying, punching, and forming the film is continuously performed.

【0012】このグリーンシートに導体印刷、ビア埋め
を行ったものを所望の枚数用意し、熱圧着して積層体を
形成した。ここで前記積層体上に複数のチップキャリヤ
個片とすべく各個片の外形に沿って所望の数のスルーホ
ールを形成した。このスルーホール径は400μmとした。
必要によっては各スルーホールをつなぐ形でノッチをい
れた。
A desired number of the green sheets on which conductor printing and via filling were performed were prepared and thermocompression bonded to form a laminate. Here, a desired number of through holes were formed along the outer shape of each chip carrier into a plurality of chip carrier pieces on the laminated body. The diameter of this through hole was 400 μm.
A notch was formed to connect each through hole if necessary.

【0013】次にスルーホールの内壁に導体層を形成す
べくスクリーン印刷法で導体ペーストをスルーホール上
に積層体の下から吸引しながら印刷した。導体ペースト
は、CuO粉末(平均粒径3μm)に接続強度を得るための
ガラスフリット(コーニング社製#7059ガラス粉末、平
均粒径3μm)を5wt%加えたものを無機成分とし、有機
バインダであるエチルセルロースをターピネオールに溶
かしたビヒクルを加えて、3段ロールにより適度な粘度
になるように混合したものを用いた。
Next, in order to form a conductor layer on the inner wall of the through hole, a conductor paste was printed on the through hole by suction from below the laminated body. The conductor paste is an organic binder containing 5 wt% of CuO powder (average particle size 3 μm) and glass frit (# 7059 glass powder manufactured by Corning, average particle size 3 μm) for obtaining connection strength as an inorganic component. A vehicle prepared by dissolving ethyl cellulose in terpineol was added and mixed with a three-stage roll so as to have an appropriate viscosity.

【0014】このようにした印刷の終った積層体を空気
中、600℃の温度で脱バインダを行なった。その後前記
積層体を水素ガス100%雰囲気中で300℃−5時間で還元
した。この時の銅層をX線回折により分析したところ10
0%銅であることを確認した。最後に純窒素中900℃のメ
ッシュベルト炉で焼成した。次に焼成した基板のスルー
ホール上にレーザーカッターでスクライブラインを入れ
個片に分割した。
The thus printed laminate was debindered in air at a temperature of 600 ° C. Then, the laminated body was reduced in an atmosphere of 100% hydrogen gas at 300 ° C. for 5 hours. When the copper layer at this time was analyzed by X-ray diffraction, it was 10
It was confirmed to be 0% copper. Finally, it was baked in pure nitrogen in a mesh belt furnace at 900 ° C. Next, a scribe line was put on the through hole of the fired substrate with a laser cutter to divide into individual pieces.

【0015】作製したチップチャリヤ34の破断面を観察
してみると図1の斜視図に示すようにスクライブライン
41を境にスルーホール導体層35A及びセラミック部30A
がきれいに破断され、図4に示すように導体が片方に引
っ張られ剥がれたり、クラックが入るということはなか
った。また酸化第二銅ペーストのスルーホールへの流れ
についても基板の反対側まで吸引されていることが確認
できた。
Observing the fracture surface of the produced chip carrier 34, as shown in the perspective view of FIG.
Through-hole conductor layer 35A and ceramic part 30A at 41
Was ruptured cleanly, and as shown in FIG. 4, the conductor was not pulled by one side to be peeled off or cracked. It was also confirmed that the flow of the cupric oxide paste into the through hole was sucked up to the opposite side of the substrate.

【0016】またノッチをいれた場合の酸化第二銅ペー
ストのノッチ溝への流れについてもその現象はほとんど
なくショートしている所はみられなかった。
The flow of the cupric oxide paste into the notch groove when the notch was inserted showed almost no such phenomenon, and no short circuit was observed.

【0017】内層に配線を持つチップキャリヤ型のセラ
ミック多層配線基板の一例を図2の斜視図に示す。図2
ではLSI等の部品を搭載している。21はLSI、22は
セラミック部、23は内部導体、24は表面導体、25はサイ
ド電極である。
An example of a chip carrier type ceramic multilayer wiring board having wiring in the inner layer is shown in the perspective view of FIG. Figure 2
In, parts such as LSI are mounted. Reference numeral 21 is an LSI, 22 is a ceramic portion, 23 is an internal conductor, 24 is a surface conductor, and 25 is a side electrode.

【0018】[0018]

【発明の効果】以上説明したように本発明のセラミック
チップキャリヤの製造方法は、チップキヤリヤの多数個
取りを目的とした基板を個片に分割するとき、スルーホ
ール部で導体が片方に引っ張られ剥がれたり、クラック
が入ることをなくすものである。また焼成前にスルーホ
ール部に酸化第二銅ペーストを印刷するので導体がノッ
チ溝に流れ、隣のスルーホールとショートを起こすこと
をなくすものである。
As described above, according to the method of manufacturing a ceramic chip carrier of the present invention, when a substrate for the purpose of taking a large number of chip carriers is divided into pieces, the conductor is pulled to one side at the through hole portion and peeled off. It also eliminates cracks. Further, since the cupric oxide paste is printed on the through hole portion before firing, the conductor does not flow into the notch groove and short-circuit with the adjacent through hole is prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の製造方法で作成したセラミックチップ
キャリヤ型のサイド電極部の破断面を示す図である。
FIG. 1 is a view showing a fracture surface of a side electrode portion of a ceramic chip carrier type produced by a manufacturing method of the present invention.

【図2】チップキャリヤ型のセラミック多層線基板の一
例を示す斜視図である。
FIG. 2 is a perspective view showing an example of a chip carrier type ceramic multilayer wire substrate.

【図3】従来のセラミックチップキャリヤタイプのパッ
ケージICの斜視図である。
FIG. 3 is a perspective view of a conventional ceramic chip carrier type package IC.

【図4】従来のセラミックチップキャリヤタイプのサイ
ド電極部の破断面を示す斜視図である。
FIG. 4 is a perspective view showing a fracture surface of a side electrode portion of a conventional ceramic chip carrier type.

【符号の説明】[Explanation of symbols]

21…LSI、 22…セラミック部、 23…内部導体、
24…表面導体、 25…サイド電極(スルーホール部)、
30…チップキャリヤ34のセラミック基板、 30A…セラ
ミック部、 30B…セラミック破断部、 31…サイド電
極(スルーホール導体層35A)、 32…配線基板、 33…
電極パッド、 34…チップキャリヤ、35…スルーホー
ル、 41…スクライブライン。
21 ... LSI, 22 ... Ceramic part, 23 ... Internal conductor,
24 ... Surface conductor, 25 ... Side electrode (through hole),
30 ... Ceramic substrate of chip carrier 34, 30A ... Ceramic part, 30B ... Ceramic breakage part, 31 ... Side electrode (through-hole conductor layer 35A), 32 ... Wiring board, 33 ...
Electrode pad, 34… Chip carrier, 35… Through hole, 41… Scribe line.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H05K 3/46 H 6921−4E ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI technical display location H05K 3/46 H 6921-4E

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 少なくとも酸化第二銅を主成分とするペ
ーストを印刷しグリーンシートを所望枚数積層し、その
後この積層体にスルーホールを形成し、前記積層体の両
面及び片面にある酸化第二銅を主成分とするペーストを
吸引しながら、配線パターン及びスルーホールの内壁に
導体を印刷する。この印刷済み積層体を脱バインディン
グし、還元熱処理を行い、窒素雰囲気中で焼成し作った
セラミック基板と、スルーホールを分割するようにブレ
イクすることを特徴とするセラミックチップキャリアの
製造方法。
1. A paste containing at least cupric oxide as a main component is printed to laminate a desired number of green sheets, and then through holes are formed in this laminate, and the second oxide on both sides and one side of the laminate is formed. A conductor is printed on the inner wall of the wiring pattern and the through hole while sucking the paste containing copper as a main component. A method of manufacturing a ceramic chip carrier, comprising debinding the printed laminated body, performing a reducing heat treatment, and breaking the ceramic substrate made by firing in a nitrogen atmosphere so as to divide a through hole.
【請求項2】 焼成後のセラミック基板のスルーホール
上にスクライブ線を入れることを特徴とする請求項1記
載のセラミックチップキャリアの製造方法。
2. The method of manufacturing a ceramic chip carrier according to claim 1, wherein a scribe line is provided on the through hole of the ceramic substrate after firing.
【請求項3】 積層体にスルーホールを形成した後、各
スルーホールをつなぐ形でノッチを入れることを特徴と
する請求項1記載のセラミックチップキャリアの製造方
法。
3. The method of manufacturing a ceramic chip carrier according to claim 1, wherein after forming through holes in the laminated body, notches are formed so as to connect the through holes.
JP4853892A 1992-03-05 1992-03-05 Manufacture of ceramic chip carrier Pending JPH05251584A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4853892A JPH05251584A (en) 1992-03-05 1992-03-05 Manufacture of ceramic chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4853892A JPH05251584A (en) 1992-03-05 1992-03-05 Manufacture of ceramic chip carrier

Publications (1)

Publication Number Publication Date
JPH05251584A true JPH05251584A (en) 1993-09-28

Family

ID=12806149

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4853892A Pending JPH05251584A (en) 1992-03-05 1992-03-05 Manufacture of ceramic chip carrier

Country Status (1)

Country Link
JP (1) JPH05251584A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012080085A (en) * 2010-09-10 2012-04-19 Nichia Chem Ind Ltd Support medium and light emitting device using the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012080085A (en) * 2010-09-10 2012-04-19 Nichia Chem Ind Ltd Support medium and light emitting device using the same
US9525116B2 (en) 2010-09-10 2016-12-20 Nichia Corporation Supporting member and light emitting device using the supporting member
US9847463B2 (en) 2010-09-10 2017-12-19 Nichia Corporation Method of manufacturing light emitting device including metal patterns and cut-out section
US10636945B2 (en) 2010-09-10 2020-04-28 Nichia Corporation Method of manufacturing light emitting device including metal patterns and cut-out section

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