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JPH05251497A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05251497A
JPH05251497A JP4050571A JP5057192A JPH05251497A JP H05251497 A JPH05251497 A JP H05251497A JP 4050571 A JP4050571 A JP 4050571A JP 5057192 A JP5057192 A JP 5057192A JP H05251497 A JPH05251497 A JP H05251497A
Authority
JP
Japan
Prior art keywords
insulating film
layer
film
metal
metal pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4050571A
Other languages
Japanese (ja)
Inventor
Kazumi Totani
和美 戸谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4050571A priority Critical patent/JPH05251497A/en
Publication of JPH05251497A publication Critical patent/JPH05251497A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To remove the nonconformity that a conventional metallic pad had, such as that cracks ware occurring in the interlayer film since the stress to a projection becomes large and it does not withstand the stress when bonding Au wires to a recess and the projection of the metallic pad at the second layer of a double structure of semiconductor device. CONSTITUTION:In a semiconductor device where the metallic pad 3 on the insulating film on a semiconductor substrate is made in the structure of two layers through an interlayer insulating film 2, the periphery of the metallic pad in the first layer is surrounded by the metallic oxide film in the first layer, and an interlayer insulating film and the metallic pad in the second layer are connected through the through hole in the interlayer insulating film, whereby cracks are prevented by occurring in the interlayer insulating film at bonding.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
半導体基板上の絶縁膜上金属パッドが層間絶縁膜を介し
て二層の構造で構成される半導体装置において、第一層
の金属パッドがその周囲を第一層の金属酸化膜で囲まれ
層間絶縁膜と層間絶縁膜開孔部を介して第二層の金属パ
ッドと接続される半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, in a semiconductor device in which a metal pad on an insulating film on a semiconductor substrate has a two-layer structure with an interlayer insulating film interposed, The present invention relates to a semiconductor device that is surrounded by a metal oxide film of a first layer and is connected to an interlayer insulating film and a metal pad of a second layer through an opening of the interlayer insulating film.

【０００２】[0002]

【従来の技術】従来、半導体基板上に構成された金属パ
ッドが二層構造の半導体装置においては図３に示すよう
に半導体基板上に形成された絶縁膜上に既知の方法を用
いて金属膜を形成し、前記金属膜を既知のＰＲ技術を用
いて所定の領域以外を選択的に除去することにより第一
層目の金属パッド３を形成する。前記第一の金属パッド
上に既知の方法を用いて層間膜としての絶縁膜２を形成
し、前記絶縁膜を既知のＰＲ技術を用いて所定の領域を
選択的に除去することにより、第一層目と第二層目の金
属配線の接続をとる。前記絶縁膜上に既知の方法を用い
て金属膜を形成し、前記金属膜を既知のＰＲ技術を用い
て所定の領域以外を選択的に除去することにより、第二
層目の金属パッド５を形成する。前記第二層目の金属パ
ッド上にはカバーとなる絶縁膜が形成されているが、金
属パッド上のみ除去している。2. Description of the Related Art Conventionally, in a semiconductor device having a two-layer structure of a metal pad formed on a semiconductor substrate, a metal film is formed on an insulating film formed on the semiconductor substrate by a known method as shown in FIG. And the metal film 3 is formed by selectively removing the metal film except for a predetermined region by using a known PR technique. By forming an insulating film 2 as an interlayer film on the first metal pad by a known method and selectively removing a predetermined region of the insulating film by a known PR technique, The connection of the metal wiring of the second layer and the second layer is made. A metal film is formed on the insulating film by a known method, and the metal film is selectively removed by a known PR technique except for a predetermined region, whereby the second-layer metal pad 5 is formed. Form. An insulating film serving as a cover is formed on the second-layer metal pad, but only the metal pad is removed.

【０００３】[0003]

【発明が解決しようとする課題】従来の金属パッドが二
層構造の半導体装置においては、ボンディングを実施す
る際に図３のように、第二層の金属パッドは第一層の金
属パッドとの段差のために凸凹となっているため、第二
層の金属パッドの凹部と凸部にＡｕ線をボンディングす
る際、凸部への応力が大となっていた。このことにより
第一層の金属パッドの周囲を第二層の金属パッドで覆う
ような構造では、図３のように層間膜が薄くなっている
こともありボンディング時の応力に耐えられず層間膜に
クラックがはいってしまう。In a conventional semiconductor device having a two-layer structure of metal pads, the second-layer metal pads are connected to the first-layer metal pads as shown in FIG. 3 when performing bonding. Because of the unevenness due to the step, when the Au wire is bonded to the concave portion and the convex portion of the second layer metal pad, the stress on the convex portion is large. As a result, in the structure in which the metal pad of the first layer is covered with the metal pad of the second layer, the interlayer film may be thin as shown in FIG. A crack is introduced into.

【０００４】また耐湿性に弱く第一層の金属パッドが腐
食する事があり、品質上の問題となっていた。Further, the moisture resistance is weak and the metal pad of the first layer may be corroded, which is a quality problem.

【０００５】本発明の目的は層間膜にクラックがはいる
ことなくしかも金属パッドが腐食することのない半導体
装置を提供することにある。It is an object of the present invention to provide a semiconductor device in which no crack is formed in the interlayer film and the metal pad is not corroded.

【０００６】[0006]

【課題を解決するための手段】本発明は、金属パッドが
二層構造の半導体装置において、第一層の金属パッドが
その周囲を第一層の金属酸化膜で囲まれ、層間絶縁膜と
層間絶縁膜開孔部を介して第二層の金属パッドと接続さ
れることを特徴としている。According to the present invention, in a semiconductor device having a two-layer structure of a metal pad, a first-layer metal pad is surrounded by a first-layer metal oxide film, and an interlayer insulating film and an interlayer insulating film are provided. It is characterized in that it is connected to the second-layer metal pad through the insulating film opening.

【０００７】[0007]

【実施例】本発明について図面を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

【０００８】図１は金属パッド部の断面図を示してい
る。FIG. 1 shows a sectional view of a metal pad portion.

【０００９】半導体基板上に酸化膜等の絶縁膜２を既知
の成長方法を用いて形成する。前記絶縁膜２上に既知の
スパッタ等の方法を用いてアルミ等の金属膜１．０μm
を形成する。前記金属膜を既知のＰＲ技術を用いて所定
の領域を選択的に露光し、更に既知の化成技術を用いて
化成を行い、第一層目の金属パッド３を形成する。形成
された金属パッドの周囲は化成されているため絶縁物４
となっているが、もとは金属膜として金属パッド部と共
に形成された部分であるため、金属パッドとの段差はな
く、平坦になっている。An insulating film 2 such as an oxide film is formed on a semiconductor substrate by a known growth method. A metal film such as aluminum having a thickness of 1.0 μm is formed on the insulating film 2 by a known method such as sputtering.
To form. A predetermined region of the metal film is selectively exposed by using a known PR technique, and further, formation is performed by using a known formation technique to form a first-layer metal pad 3. Insulator 4 is formed around the formed metal pad because it is chemically formed.
However, since it was originally formed as a metal film together with the metal pad portion, there was no step with the metal pad and it was flat.

【００１０】前記第一層目の金属パッド上に窒化膜等の
絶縁膜２、１．０μm を既知の方法により形成する。前
記絶縁膜２を既知のＰＲ技術を用いて所定の領域を選択
的に除去し、第一層目と第二層目の金属配線の接続をと
る。前記絶縁膜２及び４を再度既知のＰＲ技術を用いて
所定の領域を選択的に除去し、ｎ+ 領域と第二層目の金
属配線との接続をとる。An insulating film 2 such as a nitride film having a thickness of 1.0 μm is formed on the first-layer metal pad by a known method. A predetermined region of the insulating film 2 is selectively removed by using a known PR technique to connect the metal wirings of the first layer and the second layer. Predetermined regions are selectively removed from the insulating films 2 and 4 again by using a known PR technique to connect the n + regions to the second-layer metal wiring.

【００１１】前記絶縁膜２上に既知の方法を用いてアル
ミ等の金属膜１．８μm を形成する。前記金属膜を既知
のＰＲ技術を用いて所定の領域以外を選択的に除去する
ことにより第二層目の金属配線５及び金属パッド６を形
成する。A metal film 1.8 μm of aluminum or the like is formed on the insulating film 2 by a known method. The metal film 5 and the metal pad 6 of the second layer are formed by selectively removing the metal film except a predetermined region by using a known PR technique.

【００１２】次に図２に第２の実施例を示す。半導体基
板上に酸化膜等の絶縁膜を既知の方法にて形成し、前記
絶縁膜を既知のＰＲ技術を用いて、所定の領域を選択的
に除去しｎ+ 領域との接続がとれるようにした後、前記
絶縁膜上に既知のスパッタ等の技術を用いて金属膜を形
成する。以降は第１の実施例と同様に化成領域・絶縁膜
・第二層目の金属パッド等を形成する。Next, FIG. 2 shows a second embodiment. An insulating film such as an oxide film is formed on a semiconductor substrate by a known method, and the insulating film is selectively removed in a predetermined region by a known PR technique so that a connection with an n + region can be established. After that, a metal film is formed on the insulating film by using a known technique such as sputtering. After that, the formation region, the insulating film, the second-layer metal pad, and the like are formed as in the first embodiment.

【００１３】[0013]

【発明の効果】以上説明したように本発明は半導体基板
上の絶縁膜上金属パッドが層間絶縁膜を介して二層の構
造で形成される半導体装置において、第一層の金属パッ
ドがその周囲を第一層の金属酸化膜で囲まれ、層間絶縁
膜と層間絶縁膜開孔部を介して第二層の金属パッドと接
続される半導体装置であるので、ボンディング時に層間
絶縁膜にクラックの入ることを防ぐという効果がある。As described above, according to the present invention, in a semiconductor device in which a metal pad on an insulating film on a semiconductor substrate is formed in a two-layer structure with an interlayer insulating film interposed, the metal pad of the first layer surrounds it. Since the semiconductor device is surrounded by the first layer metal oxide film and connected to the second layer metal pad through the interlayer insulating film and the interlayer insulating film opening, the interlayer insulating film is cracked during bonding. The effect is to prevent this.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.

【図２】本発明の第２の実施例の断面図である。FIG. 2 is a sectional view of a second embodiment of the present invention.

【図３】従来例の断面図である。FIG. 3 is a sectional view of a conventional example.

【符号の説明】[Explanation of symbols]

１ ｎ+ 領域 ２ 絶縁膜 ３ １層目金属パッド ４ 化成領域 ５ ２層目金属配線（一部パッド） ６ ２層目金属パッド ７ ボンディングワイヤー1 n + region 2 insulating film 3 first layer metal pad 4 chemical formation region 5 second layer metal wiring (partial pad) 6 second layer metal pad 7 bonding wire

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体基板上の絶縁膜上金属パッドが層
間絶縁膜を介して二層の構造で形成される半導体装置に
おいて、第一層の金属パッドがその周囲を第一層の金属
酸化膜で囲まれ、層間絶縁膜と層間絶縁膜開孔部を介し
て第二層の金属パッドと接続されることを特徴とする半
導体装置。1. In a semiconductor device in which a metal pad on an insulating film on a semiconductor substrate is formed in a two-layer structure with an interlayer insulating film interposed, a first layer metal pad surrounds a first layer metal oxide film. A semiconductor device which is surrounded by and is connected to a second-layer metal pad through an interlayer insulating film and an opening of the interlayer insulating film.
JP4050571A 1992-03-09 1992-03-09 Semiconductor device Withdrawn JPH05251497A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4050571A JPH05251497A (en) 1992-03-09 1992-03-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4050571A JPH05251497A (en) 1992-03-09 1992-03-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05251497A true JPH05251497A (en) 1993-09-28

Family

ID=12862690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4050571A Withdrawn JPH05251497A (en) 1992-03-09 1992-03-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05251497A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084312A (en) * 1998-10-30 2000-07-04 Samsung Electronics Co., Ltd. Semiconductor devices having double pad structure
JP2017084944A (en) * 2015-10-27 2017-05-18 株式会社デンソー Semiconductor device
US20210384166A1 (en) * 2019-11-29 2021-12-09 Yangtze Memory Technologies Co., Ltd. Chip package structure and manufacturing method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084312A (en) * 1998-10-30 2000-07-04 Samsung Electronics Co., Ltd. Semiconductor devices having double pad structure
JP2017084944A (en) * 2015-10-27 2017-05-18 株式会社デンソー Semiconductor device
US20210384166A1 (en) * 2019-11-29 2021-12-09 Yangtze Memory Technologies Co., Ltd. Chip package structure and manufacturing method thereof
US11688721B2 (en) * 2019-11-29 2023-06-27 Yangtze Memory Technologies Co., Ltd. Chip package structure and manufacturing method thereof
US20230275070A1 (en) * 2019-11-29 2023-08-31 Yangtze Memory Technologies Co., Ltd. Chip package structure and manufacturing method thereof
US12125827B2 (en) 2019-11-29 2024-10-22 Yangtze Memory Technologies Co., Ltd Chip package structure and manufacturing method thereof

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