JPH05235194A - Microwave monolithic integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to make the optimum design of the heat resistance of a FET part and the line width of a microstrip line separately from each other by a method wherein an insulating film is partially formed on the rear of a semiconductor substrate, on which a microwave monolithic integrated circuit is formed, and the apparent thickness of the substrate is changed at the FET part, the periphery of a via hole and a wiring region. CONSTITUTION:An insulating film 4 consisting of (a silicon oxide film 6 and) a polyimide film is formed on the rear of a GaAs substrate la excluding the part, which corresponds to a FET part 2 on the substrate 1a, of the rear and a via hole 3 and thereafter, an Au plating 5 is applied to the whole rear. In such a way, the apparent thickness of the substrate is made thin at the FET part 2 to lessen the heat resistance of the FET part and is made thick at the place of a wiring 7 constituting a microstrip line to inhibit an increase in the characteristic impedance of the wiring.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microwave monolithic integrated circuit (hereinafter referred to as MMIC), and more particularly to an MMIC having a via hole PHS (Plated Heat Sink) structure.

[0002]

2. Description of the Related Art In a conventional MMIC, as shown in FIG. 2A, a front surface electrode is provided on a back surface Au of a semiconductor substrate 1 having a uniform thickness.
A via hole for connecting to the (gold) plating 5 is formed. Alternatively, as shown in FIG. 2B, there is a semiconductor substrate 1 in which a portion of the semiconductor substrate 1 is thinned and the Au plating 5 is thickened to improve the heat conduction of the FET portion 2.

In any case, the MMIC wiring 7 usually forms a microstrip line. In the MMIC in which the semiconductor substrate 1 is made of GaAs, the thickness of the semiconductor substrate 1 immediately below the wiring 7 is processed to about 100 μm.

[0004]

The characteristic impedance of the microstrip line used for the wiring of the MMIC is determined by the resistance of the wiring, the capacitance between the wirings, the inductance of the wiring, and the ground capacitance of the wiring.

Since the ground capacitance is determined by the dielectric constant and thickness of the semiconductor substrate, the thicker the semiconductor substrate, the smaller the ground capacitance and the transmission loss of the microstrip line.

For a power FET or the like which generates a large amount of heat, there is a method in which a part of the semiconductor substrate 1 is thinned and Au plating 5 having a large thermal conductivity is embedded as shown in FIG. 2B. As the semiconductor substrate 1 becomes thicker, the processing accuracy when forming the via hole 3 becomes worse. Since the inductance also increases in the via holes 3 as the semiconductor substrate 1 becomes thicker, there is a limit to making the semiconductor substrate 1 thicker.

Therefore, wiring loss, thermal resistance of the FET section,
It was necessary to optimize the thickness of the semiconductor substrate 1 in consideration of contradictory conditions such as via hole processing accuracy.

[0008]

In a microwave monolithic integrated circuit of the present invention, an insulating layer having a dielectric constant smaller than that of the semiconductor substrate is formed on a part of the back surface of the semiconductor substrate on which a plurality of individual elements and wirings thereof are formed. It was formed.

[0009]

EXAMPLE FIG. 1A shows a first example of the present invention.
Will be described.

On the surface of the GaAs substrate 1a, an electric circuit composed of a plurality of individual elements and their wirings is formed, and processed to have a thickness of 30 μm by polishing the back surface. Further, a via hole 3 for connecting the front surface electrode to the back surface Au plating 5
Are formed.

An insulating film 4 made of polyimide having a thickness of 50 μm is formed on the back surface of the GaAs substrate 1 except for the FET portion 2 and the periphery of the via hole 3. An Au plating 5 having a thickness of 20 μm is formed on the insulating film 4.

The FET portion 2 and the via hole 3 are formed on the GaAs substrate 1 having a thickness of 30 μm. The wiring 7 constituting the microstrip line and others are formed on the GaAs substrate 1a having a thickness of 30 μm and the insulating film 4 having a thickness of 20 μm. Since the insulating film 4 made of polyimide has a dielectric constant of about 3, which is smaller than the dielectric constant 12 of the GaAs substrate 1, the total thickness of the GaAs substrate 100 μ is 100 μm.
It is equivalent to m or more.

The insulating film 4 has a thickness of 30% on the GaAs substrate 1.
After back-polishing to μm, polyimide film 15
It is formed by thermocompression bonding at 0 to 300 ° C. and then selective etching.

Next, a second embodiment of the present invention will be described with reference to FIG.

In this embodiment, the back surface of the GaAs substrate 1 is polished to deposit a silicon oxide film 6 having a thickness of 1 μm,
It has a three-layer structure in which an insulating film 4 made of polyimide is formed. Surface contamination is further reduced as compared with the first embodiment, and the leak current can be reduced.

[0016]

By forming the insulating film on a part of the back surface of the semiconductor substrate, the apparent thickness can be locally thin around the FET portion and the via hole and thick at the wiring. As a result, the heat dissipation of the FET can be improved and the wiring width of the microstrip line can be optimized.

Further, since the semiconductor substrate is thinned in advance, the processing accuracy of the via hole is improved. It is possible to reduce the via hole size and improve the reliability of the MMIC.

[Brief description of drawings]

FIG. 1A is a sectional view showing a first embodiment of the present invention. (B) is a sectional view showing a second embodiment of the present invention.

FIG. 2 is a sectional view showing a conventional microwave monolithic integrated circuit.

[Explanation of symbols]

 1 Semiconductor Substrate 1a GaAs Substrate 2 FET Section 3 Via Hole 4 Insulating Film 5 Au Plating 6 Silicon Oxide Film 7 Wiring

Claims (1)

[Claims] 1. A microwave monolithic integrated circuit in which an insulating layer having a dielectric constant smaller than that of the semiconductor substrate is formed on a part of the back surface of the semiconductor substrate on which a plurality of individual elements and wirings thereof are formed.