JPH0522730A - Digital convergence correction device - Google Patents

Abstract

(57) [Abstract] [Purpose] When the convergence correction data stored in the memory is read and D / A converted, data for a plurality of channels is time-division processed by one D / A converter to reduce costs. In the digital convergence correction device,
The deterioration of the convergence correction accuracy at the left and right ends of the cathode ray tube screen due to the time division processing is improved. A process for making the correction data of the horizontal blanking period at the output of the sample hold circuit 6 the same as the correction data immediately before the period, and the correction data of the horizontal blanking period at the output of the sample hold circuit 7 are The CPU 17 is caused to execute a process of making the correction data the same as that immediately after the period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence correction device used for performing distortion correction and convergence correction on a cathode ray tube display screen of a television receiver or display device.

[0002]

2. Description of the Related Art In a cathode ray tube display screen of a raster scan system, each grid point formed when the screen is divided into a grid is used as a convergence adjustment point.
The required amount of convergence correction for each adjustment point is calculated in advance for each horizontal, vertical direction of the screen for each red, green, and blue beam (hereinafter sometimes referred to as channel), and stored in memory as convergence correction data. Then, this is read in synchronization with the raster scan on the screen, converted into an analog signal by the digital / analog converter (D / A converter), and the convergence yoke (CY) provided in the cathode ray tube is driven by this analog signal. A digital convergence correction device that performs convergence correction on a screen is already well known.

Convergence correction data stored in the memory are two channels for one channel in the horizontal direction and one channel in the vertical direction for the red beam, two channels for the green beam, and two channels for the blue beam. In the same way, data for 2 channels, that is, for 6 channels in total, is originally stored.

Then, when the convergence correction data is read from the memory and converted into an analog signal by the D / A converter, if the memory stores data for six channels, six D / A conversions are performed. If two units of data are stored for the red beam, or two channels of data for the red beam are required, two D / A converters are required.

However, since the D / A converter is expensive,
There is a demand to reduce the required number as much as possible.
Therefore, for example, by performing time-division multiplexing processing on the convergence correction data for two channels, one D / A
A technique of processing with a converter is proposed in Japanese Patent Laid-Open No. 1-280986. A conventional digital convergence correction device using such time division multiplexing processing will be described below.

FIG. 2 is a block diagram showing an example of the configuration of a conventional digital convergence correction device using time division multiplexing processing. In the figure, 1 is an input terminal for a horizontal retrace pulse in raster scanning, and 2 is an input terminal for a vertical retrace pulse. Reference numeral 3 is an address generator that generates an address signal synchronized with the raster scan with reference to the pulses input from the input terminals 1 and 2.

Reference numeral 4 is a memory for storing convergence correction data of two channels (which will be referred to as a first channel and a second channel). Reference numeral 5 denotes a D / A converter for converting the digital convergence correction data read from the memory 4 into an analog correction signal, which processes the data for two channels by the time division multiplexing process. And the convergence correction signal of the second channel are alternately output.

Further, 6 is a sample and hold circuit for sampling and holding the correction signal of the first channel among the multiplexed analog correction signals from the D / A converter 5, and 7 is the It is a sample and hold circuit that samples and holds the correction signals of the two channels. Reference numeral 8 denotes a sample hold pulse (S / H pulse) generation circuit that drives the sample hold circuits 6 and 7.

Reference numeral 9 is a low-pass filter (LPF) for interpolating and outputting the correction signal of the first channel, 11 is a CY amplifier for driving a CY (convergence yoke) 13 of the first channel, and 13 is a first This is a CY (convergence yoke) that generates a channel convergence correction magnetic field. Similarly, 10, 12, and 14 are the LPF, CY amplifier, and CY of the second channel, respectively.

Reference numeral 15 is an instruction device such as a keyboard used by an adjuster for writing convergence adjustment data in a memory to send an instruction for convergence adjustment to the CPU 16.
Reference numeral 16 denotes a processing device (CPU) for receiving the instruction from the instruction device 15 and obtaining the correction data to be written in the memory 4 by the arithmetic processing.

Next, FIG. 3 shows the CPU 16 in FIG.
6 is a flowchart showing a procedure for creating correction data by calculation processing. That is, since the correction data corresponding to the image display period on the screen excluding the horizontal blanking period directly corresponds to the convergence state on the screen, the correction data can be given from the instruction device 15 at the discretion of the adjuster.

On the other hand, since the correction data in the horizontal blanking period does not directly affect the convergence state on the screen, it cannot be given from the indicating device 15 at the discretion of the adjuster. Therefore, the correction data for the horizontal blanking period is the CPU
It is created by 16 arithmetic processes. The procedure shown in FIG. 3 shows the procedure for creating this correction data by arithmetic processing.

Therefore, as shown in FIG. 3, the CPU 16
Goes through step (a), then steps (b) and (c)
Then, as the correction data for the horizontal blanking period, the correction data immediately after each horizontal blanking period is written in the memory 4 for both the first channel and the second channel. As a result, during the horizontal blanking period, the convergence correction is performed using the same correction data as the correction data immediately after that. Needless to say, the convergence correction operation throughout the circuit of FIG.

[0014]

Generally, due to the raster scanning, the convergence correction signal also changes sharply during the horizontal retrace period in which the correction data at the right end of the cathode ray tube screen changes to the correction data at the left end in a short time. . Before and after this horizontal blanking period, there is a period during which a correction signal not suitable for convergence correction is output due to the waveform blunting action of the LPF. The period for outputting the correction signal suitable for the convergence correction excluding the period for outputting the correction signal not suitable for the convergence correction is hereinafter referred to as the convergence correction effective period.

In the above-mentioned conventional digital convergence correction apparatus using the time division multiplexing processing, the correction signals of a plurality of channels can be digital / analog converted by one D / A converter and output. It has the advantage of being economical because it can be done, but on the other hand, since convergence correction is performed by analog signals with different phases due to time division for each channel, convergence correction common to all channels is effective. There was a problem that the period was shortened.

The reason why the convergence correction effective period common to all channels is shortened will be described in detail below with reference to FIG. FIG. 4 is a waveform diagram showing waveforms of main signals of the circuit shown in FIG.

In FIG. 4, (a1) to (f1) show the waveforms at the same symbols as shown in FIG. Further, in the waveform of (c1), t2 indicates a period for outputting the correction data of the horizontal retrace line period of the first channel, and similarly, in the waveform of (d1), t5 indicates the horizontal retrace line of the second channel. The period during which the correction data of the period is output is shown.

Further, the correction data in the horizontal blanking period t2 of the first channel in (c1) is the CP shown in FIG.
It will be recognized that the processing of U (step (b)) makes it the same value as the correction data of t3 immediately thereafter. Similarly, the correction data in the horizontal blanking period t5 of the second channel in (d1) is C shown in FIG.
It will be recognized that the value of the correction data immediately after that is set to the same value as the correction data of t6 by the processing of the PU (step (C)).

The sample and hold circuits 6 and 7 are
When the sample and hold pulses (a1) and (b1) from the sample and hold pulse generating circuit 8 are "Hi", the output voltage follows the input voltage, and when it is "Lo", the output is held. Since the D / A converter 5 in the previous stage performs time division multiplexing processing and outputs a signal, the sample-hold pulses of (a1) and (b1) are pulses that become "Hi" alternately in terms of phase. It is a signal. Therefore, the outputs (c1) and (d1) of the sample and hold circuits 6 and 7 alternately change as seen in FIG.

Under the influence of this, the output of the LPF 10 (f
1) is compared with the output (e1) of the LPF 9, the period t
The output will be delayed by 8. Therefore, the convergence correction effective period of the first channel LPF output (e1) (the period not affected by the change in the correction data of the horizontal blanking period) t7 and the convergence of the second channel LPF output (f1). The correction effective period t9 is the period t
The phase is shifted by 8 and as a result, the convergence correction effective period t10 that is effective for both channels is the period t
It is shorter than 7 and t9 by the period t8.

Then, at the left and right edges of the screen of the cathode ray tube, the LP
Since the convergence correction is performed by using the correction signal in the period when it is not suitable for the convergence correction due to the waveform blunting action of F, there is a problem that the accuracy of the convergence correction deteriorates. If the number of output data in one horizontal period is increased, that is, if the sampling rate is increased, the LPF is increased.
Since the waveform blunting due to the interpolation operation of 1 is reduced, the above problem can be solved. However, the method of increasing the sampling rate is disadvantageous in that it requires a large memory capacity and high-speed operation of each unit, resulting in a large increase in cost.

The object of the present invention is to solve the above-mentioned problems of the prior art and to maintain the advantage of the time division multiplexing processing in which the correction signals of a plurality of channels are converted into digital / analog by one D / A converter. At the same time, it is possible to expand the effective period of convergence correction common to both channels by a low-cost means, and to provide a digital convergence correction device that can accurately perform convergence correction not only on the center of the cathode ray tube screen but also on the left and right ends. To do.

[0023]

In order to achieve the above object, the present invention uses means for changing the calculation processing method of the correction data in the horizontal blanking period depending on the channel. The above object can also be achieved by using a means for delaying the analog signal so that the data output timings of both channels match. In addition, LP during the horizontal retrace period
The above object can also be achieved by providing means for switching the delay time of F.

[0024]

[Function] When the correction data for the horizontal blanking period is increased or decreased, the LP
The phase of the convergence correction effective period changes due to the influence of the waveform blunting by F. For this reason, by changing the method of creating the correction data for the horizontal blanking period depending on the channel, the phase shift of the convergence correction effective period between the two channels is corrected after performing time division multiplexing processing, and as a result, common to all channels. The effective period of the convergence correction can be extended.

Further, the means for delaying the analog signal can also absorb the phase difference in the convergence correction effective period between the channels, so that the convergence correction effective period common to all the channels can be expanded. Further, by providing a means for switching the delay time of the LPF in the horizontal blanking period, the convergence correction effective period of each channel can be lengthened, and as a result, the convergence correction effective period common to all channels can be expanded.

[0026]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the first exemplary embodiment of the present invention. The configuration shown in the figure is the same as the configuration diagram of the conventional circuit shown in FIG. 2, but since there is a difference in the flow of the operation executed by the CPU, in order to express that,
In FIG. 1, the CPU is denoted by the reference numeral 17, which is different from the reference numeral 16 in FIG.

FIG. 5 is a flow chart showing the procedure by which the CPU 17 in FIG. 1 creates correction data. Figure 5
As can be seen from FIG. 3, the CPU 17 writes the correction data immediately before it in the memory as the correction data of the horizontal blanking period of the first channel in step S2 after step S1. It will be appreciated that the correction data immediately after that is written in the memory as the correction data for the horizontal blanking period of the channel.

Comparing step S2 of FIG. 5 according to the present invention with step (b) of FIG. 3 according to the prior art, one is "immediately before" and the other is "immediately after". It can be seen that there is a difference from the related art of.

FIG. 6 is a waveform diagram showing waveforms of main signals in the embodiment of the present invention shown in FIG. (A2) to (f2) in FIG. 6 respectively show waveforms at the same symbol portions shown in FIG.

Here, paying attention to the sample hold output (c2) of the first channel, the correction data of the horizontal retrace period t2 of the first channel is conventionally the same correction data (dotted line) as that of the period t3 immediately after that. ) Was
According to the present invention, since the same correction data (solid line) as that in the period t1 immediately before that is changed, the LF of the first channel is changed.
The convergence correction effective period of the waveform (e2) after passing through P is entirely delayed by the period t21 to become the period t22.

As a result, the portion overlapping the convergence correction valid period t9 of the second channel increases, and as a result, the convergence correction valid period t23 common to both channels.
Is longer than that of the conventional one (period t10 in FIG. 4). As described above, according to the present embodiment, it is possible to extend the convergence correction effective period common to both channels and improve the convergence correction accuracy at the left and right ends of the cathode ray tube screen only by changing the software of the CPU.

In this embodiment, the correction data for the horizontal blanking period is created by the method shown in FIG. 5, but as the correction data for the horizontal blanking period of the first channel, for example, the average value of the correction data before and after it is used. The same effect can be obtained by using other arithmetic processing such as using.

Next, a second embodiment of the present invention will be described. FIG. 7 is a block diagram showing the configuration of the second exemplary embodiment of the present invention. In this example, the LP of the first channel
An analog delay circuit 18 is provided between the F9 and the CY amplifier 11.
2 has the same configuration as that of the conventional digital convergence correction device shown in FIG.

FIG. 8 is a waveform diagram showing waveforms of main signals in the second embodiment of the present invention shown in FIG. Figure 8
(A3) to (f3) in the figure respectively show the waveforms at the same symbols shown in FIG. 7, and the periods t1 to t9 in FIG.
Corresponding to the same symbols in FIG.

Reference is now made to FIGS. 7 and 8. The output (g3) of the analog delay circuit 18 of the first channel is the second
The delay time of the analog delay circuit 18 is set to t31 so that it has the same phase as the output (f3) of the LPF 10 of the channel. Then, the phase of the period t32, which is the convergence correction effective range of the first channel, and the period t9, which is the convergence correction effective period of the second channel, are in phase, and the convergence correction effective period t common to both channels is t.
33 is longer than the conventional one (t10 in FIG. 4).

According to this embodiment, it is possible to extend the convergence correction effective period common to both channels and improve the accuracy of convergence correction at the left and right ends of the cathode ray tube screen. Further, since the output timings of the correction data of the first channel and the correction data of the second channel coincide with each other, there is an advantage that the convergence adjustment becomes easy.

Next, a third embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of the third exemplary embodiment of the present invention. In this embodiment, the LPF 9 of the first channel in the conventional configuration diagram (FIG. 2) is the LPF 1 having a long delay time.
The configuration is the same as that of the conventional digital convergence correction device except that it is replaced with 9.

Generally, the delay time can be lengthened by lowering the cutoff frequency of the LPF. Therefore, the output of the LPF 19 of the first channel is
When the delay time of the LPF 19 of the first channel is set so as to have the same phase as the output of the LPF 10 of the second channel, the phase of the convergence correction effective period of the first channel and the second channel are set as in the second embodiment. The phases of the convergence correction effective period of are coincident with each other, and the convergence correction effective period common to both channels becomes longer than the conventional one.
According to this embodiment, the same effect as that of the second embodiment can be obtained.
It can be obtained with a simpler configuration.

Next, a fourth embodiment of the present invention will be described. FIG. 10 is a block diagram showing the configuration of the fourth exemplary embodiment of the present invention. This figure shows L of the conventional configuration diagram (FIG. 2).
The configuration is the same as the conventional one except that the PFs 8 and 9 replace the LPFs 20 and 21 with delay time switching, and an LPF delay time switching pulse generation circuit 22 is added.

Next, the configuration of the LPF 20 with delay time switching will be described in detail. FIG. 11 is a circuit diagram showing a detailed configuration of the LPF 20 with delay time switching shown in FIG. Reference numeral 31 in FIG. 11 denotes an input terminal of the LPF 20 with delay time switching shown in FIG. 10, which is connected to the sample hold circuit 6.

Then, R1, C1, L1, C2, L2
C3 and R2 are components of a general LPF (having no delay time switching function), and 37 is an output terminal of the LPF 20 with delay time switching shown in FIG. 10, which is connected to the CY amplifier 11.

Further, R3 and R4 are division resistors for determining the LPF delay time switching voltage, 32 is a buffer amplifier, 33 to 35 are switch circuits for performing delay time switching operation, and 36 is switch circuits 33 to 35. This is a delay time switching pulse input terminal to be controlled, and the switch circuits 33 to 35 are in a conductive state when "Hi" and are in a disconnected state when "Lo". The delay time switching pulse input terminal 36
Is the LPF delay time switching pulse generation circuit 2 of FIG.
Connect with 2. Further, the LPF 21 with delay time switching of the second channel has the same configuration as that of FIG.

Next, the operation of the embodiment shown in FIG. 10 will be described with reference to the waveform diagram 12 showing the waveforms of the main signals of the circuit of FIG. FIG. 12 is a waveform diagram showing waveforms of main signals of the circuit shown in FIG. (C4) -in FIG.
(F4), (h4), and (i4) respectively show the waveforms at the same symbol portions shown in FIG. 10, and the period t in FIG.
1 to t9 correspond to the same symbol parts in FIG.

The delay time switching pulse generating circuit 22
As shown in (h4) and (i4), the delay time switching pulses t41 and t44 are set within the horizontal blanking period of each channel.
To occur. When the (h4) pulse becomes "Hi", the LPF 20 with delay time switching performs a delay time switching operation. Then, the LPF 20 with delay time switching
Outputs an output voltage corresponding to the input voltage without time delay. That is, when switching the delay time,
Since the switch circuits 33 to 35 of No. 1 conduct, k, l,
The potential at each point m is forcibly equalized to the output of the buffer amplifier 32.

Therefore, the LPF 2 with delay time switching
The output of 0 is as shown by the solid line in (e4) of FIG.
Compared with the case of using the conventional LPF that does not have the delay time switching function, eliminating the waveform blunting during the horizontal blanking period,
The convergence correction effective period is extended by the period t42 and becomes t43. Similarly, the convergence correction effective period of the output of the LPF 21 with delay time switching of the second channel is also increased by t45 to t46. As a result, the convergence correction effective period t47 common to both channels can be expanded as compared with the conventional case (t10 in FIG. 4).

According to the present embodiment, the valid period of the correction data of each channel can be extended, so that the accuracy of convergence correction at the left and right ends of the cathode ray tube screen can be improved even in a circuit system that does not use time division multiplexing processing. Can be made.

[0047]

According to the present invention, in a digital convergence correction apparatus, a time-division multiplex process for reducing the number of expensive D / A converters is used, and a simple and inexpensive structure is provided for a cathode ray tube screen. There is an advantage that the convergence correction accuracy at the left and right ends can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional digital convergence correction device.

FIG. 3 is a flowchart showing a method of creating correction data in a horizontal blanking period in a conventional digital convergence correction device.

4 is a waveform diagram showing waveforms of main signals in the circuit of FIG.

FIG. 5 is a flowchart showing a method of creating correction data for a horizontal blanking period in the first embodiment of the present invention.

FIG. 6 is a waveform diagram showing waveforms of main signals in the circuit of FIG.

FIG. 7 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

8 is a waveform diagram showing waveforms of main signals in the circuit of FIG.

FIG. 9 is a block diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a fourth exemplary embodiment of the present invention.

11 is a circuit diagram showing a detailed configuration of the LPF in FIG.

12 is a waveform diagram showing waveforms of main signals in the circuit of FIG.

[Explanation of symbols]

4 ... Memory, 5 ... D / A converter, 6, 7 ... Sample and hold circuit, 9, 10 ... LPF, 16 ... (Conventional) CP
U, 17 ... CPU (of the present invention), 18 ... Analog delay circuit, 19 ... LPF with long delay time, 20, 21 ... LPF with delay time switching.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuichiro Kimura             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Company Hitachi Media Media Research Center (72) Inventor Michitaka Osawa             292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Ceremony Company Hitachi Media Media Research Center

Claims (5)

[Claims] 1. In a cathode ray tube display screen by a raster scan method, each grid point formed when the screen is divided into a grid is used as a convergence adjustment point,
The required convergence correction amount for each adjustment point is calculated in advance for each horizontal, vertical direction (hereinafter referred to as channel) of the red, green, and blue beams, and is stored as convergence correction data and the image to be displayed. Convergence correction data in the horizontal blanking period of the signal, a memory for creating and storing by a separate arithmetic processing unit using an arithmetic processing unit, and a required adjustment point from the memory in synchronization with the raster scan in the cathode ray tube display. Address generation means for generating an address signal to be applied to the memory in order to read the convergence correction data in the memory, and a digital / digital converter for converting the convergence correction data read from the memory using the address signal into a digital signal and outputting the analog signal. An analog converter and the digitizer Digital-convergence composed of a low-pass filter for producing and interpolating correction data at the position between the adjustment points from the output corresponding to each adjustment point from the analog / analog converter, and outputting to the convergence correction means. In the correction device, the arithmetic processing means comprises means for producing different convergence processing for each channel when the convergence correction data in the horizontal blanking period of the video signal to be displayed is created by the arithmetic processing. Digital convergence correction device. 2. The digital convergence correction apparatus according to claim 1, wherein when the arithmetic processing unit creates the convergence correction data in the horizontal blanking period of the video signal to be displayed by the arithmetic processing, , The convergence correction data in the period immediately before the horizontal blanking period and the convergence correction data in the horizontal blanking period are made equal to each other, and for the other channel, the convergence in the period immediately after the horizontal blanking period is created. A digital convergence correction apparatus comprising means for creating correction data and convergence correction data in the horizontal blanking period so as to be equal to each other. 3. A cathode ray tube display screen by a raster scan method, wherein each grid point formed when the screen is divided into grids is a convergence adjustment point,
The required convergence correction amount for each adjustment point is calculated in advance for each horizontal, vertical direction (hereinafter referred to as channel) of the red, green, and blue beams, and is stored as convergence correction data and the image to be displayed. Convergence correction data in the horizontal blanking period of the signal, a memory for creating and storing by a separate arithmetic processing unit using an arithmetic processing unit, and a required adjustment point from the memory in synchronization with the raster scan in the cathode ray tube display. Address generation means for generating an address signal to be applied to the memory in order to read the convergence correction data in the memory, and a digital / digital converter for converting the convergence correction data read from the memory using the address signal into a digital signal and outputting the analog signal. An analog converter and the digitizer From the output corresponding to each adjustment point from the analog / analog converter, the correction data at the position between the adjustment points is created corresponding to each channel, interpolated, and output to the convergence correction means corresponding to each channel. In a digital convergence correction device including a low-pass filter corresponding to each channel, a delay means for delaying an output signal output from a low-pass filter corresponding to a specific channel as compared with that output from a low-pass filter corresponding to another channel. A digital convergence correction device characterized by being provided with. 4. In a cathode ray tube display screen by a raster scan system, each grid point formed when the screen is divided into a grid pattern is used as a convergence adjustment point,
The required convergence correction amount for each adjustment point is calculated in advance for each horizontal, vertical direction (hereinafter referred to as channel) of the red, green, and blue beams, and is stored as convergence correction data and the image to be displayed. Convergence correction data in the horizontal blanking period of the signal, a memory for creating and storing by a separate arithmetic processing unit using an arithmetic processing unit, and a required adjustment point from the memory in synchronization with the raster scan in the cathode ray tube display. Address generation means for generating an address signal to be applied to the memory in order to read the convergence correction data in the memory, and a digital / digital converter for converting the convergence correction data read from the memory using the address signal into a digital signal and outputting the analog signal. An analog converter and the digitizer From the output corresponding to each adjustment point from the analog / analog converter, the correction data at the position between the adjustment points is created corresponding to each channel, interpolated, and output to the convergence correction means corresponding to each channel. In a digital convergence correction device including a low-pass filter corresponding to each channel, the low-pass filter corresponding to each channel includes low-pass filters having different delay time characteristics as delay time characteristics of delaying and outputting an input signal. A digital convergence correction device characterized by the above. 5. A cathode ray tube display screen by a raster scan system, wherein each grid point formed when the screen is divided into a grid is used as a convergence adjustment point,
The required convergence correction amount for each adjustment point is calculated in advance for each horizontal, vertical direction (hereinafter referred to as channel) of the red, green, and blue beams, and is stored as convergence correction data and the image to be displayed. Convergence correction data in the horizontal blanking period of the signal, a memory for creating and storing by a separate arithmetic processing unit using an arithmetic processing unit, and a required adjustment point from the memory in synchronization with the raster scan in the cathode ray tube display. Address generation means for generating an address signal to be applied to the memory in order to read the convergence correction data in the memory, and a digital / digital converter for converting the convergence correction data read from the memory using the address signal into a digital signal and outputting the analog signal. An analog converter and the digitizer From the output corresponding to each adjustment point from the analog / analog converter, the correction data at the position between the adjustment points is created corresponding to each channel, interpolated, and output to the convergence correction means corresponding to each channel. In a digital convergence correction device comprising a low-pass filter corresponding to each channel, the low-pass filter corresponding to each channel, the delay time characteristic of delaying and outputting the input signal, in the horizontal blanking period of the video signal to be displayed Is a low-pass filter having means for switching to a characteristic different from that in other periods, and is a digital convergence correction apparatus.