JPH05211214A - Ic marking circuit - Google Patents

Abstract

PURPOSE:To provide a marking circuit conducting marking through an electrical method. CONSTITUTION:In the layout of a semiconductor integrated circuit, an IC marking circuit is constituted while having pads 101-112, a fuse circuit 114, a loaded part chip 115 and a substrate 116, the fuse 114 is connected directly to the pads 101, 102 and 103, and the fuse 114 is blown out by applying voltage to the pad 101 and the pad 102 or the pad 101 and the pad 103. When the fuse 114 is blown out by applying voltage, the fuse 114 is manufactured so that blown out fuse can be decided by appearance. Marking can be conducted through an electrical method by the blown out fuse, not by a mechanical method.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to an IC marking circuit.

[0002]

2. Description of the Related Art In conventional IC marking, a chip is scratched with a needle or a pen is used for marking, and marking is generally performed by a mechanical method. ..

FIG. 4 shows the conventional I
6 is a flowchart showing a procedure for testing an IC on a wafer by using a C tester and a prober. First, in the prober, a test is performed by fitting the chip to the probe card (step 401). Next, in the prober, the test result and the addresses of the ICs on the wafer are stored (step 402), it is judged whether or not the tests of all the ICs on the wafer are completed (step 403), and it is not completed. In this case, the procedure returns to step 401, and after all the ICs have been tested, the prober performs mechanical marking on the ICs using the test results and the IC addresses stored in the prober. (Step 404).

As described above, when mechanically marking an IC, it is necessary to first adjust the needle pressure and the pen pressure and the angle, and the IC chip size is different. In some cases, it may be necessary to adjust the marking. Further, in the case of such a conventional marking method, since only two kinds of good products and defective products can be selected, when grade selection is performed like frequency division, when selecting wafers, It is necessary to select with the specifications as the loosest condition, and to perform grade classification in the selection after assembling. However, in the selection after the assembly, the target grade IC is
There is a sufficient possibility that a large number of unnecessary grade ICs can be obtained without knowing whether the target quantity can be obtained.

[0005]

In the above-mentioned conventional IC marking method, only two types of IC good and defective ICs can be determined. Therefore, in order to perform grade selection such as classification by operating frequency. Has a drawback that it is necessary to select the frequency division and the like again after assembling the IC, and since it is mechanical marking, it is necessary to adjust the marking every time the chip size changes. There is a drawback that there is.

[0006]

SUMMARY OF THE INVENTION An IC marking circuit of the present invention includes a fuse capable of discriminating the presence / absence of disconnection in the inside of the IC and the fuse through a signal input from a predetermined external terminal. It is characterized in that the IC is marked by blowing the fuse by referring to a test result of the IC in a wafer state.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a layout of a semiconductor integrated circuit to which the first embodiment of the present invention is applied. As shown in FIG. 1, the semiconductor integrated circuit includes pads 101 to 101.
112, fuse circuits 113 and 114, a mounting component chip 115, and a substrate 116.

In FIG. 1, fuses 113 and 11
Reference numeral 4 is directly connected to the pads 101, 102 and 103, and the fuse 113 or the fuse 114 is blown by applying a voltage to the pad 101 and the pad 102 or the pad 101 and the pad 103. When the fuse 113 and the fuse 114 are blown by the application of a voltage, the fuse 113 and the fuse 114 are formed and arranged so that the blow can be judged from the appearance.

FIG. 2 shows, in this embodiment,
7 is a flowchart showing a procedure for testing an IC on a wafer using an IC tester and a prober. First, in the prober, a test is performed by fitting the chip to the probe card (step 201). Then, after the test is finished, a voltage is applied to the fuse by the tester according to the test result, and the fuse is blown to perform marking (step 202). Next, it is determined whether or not the tests of all the ICs on the wafer have been completed (step 203). If not completed, the process returns to step 201, and if completed, the marking is completed.

Next, a second embodiment of the present invention will be described. In the above-described first embodiment, the fuse and the pad are directly connected, and therefore the fuse pad is required. In the second embodiment, as shown in the partial circuit diagram around the fuse in FIG. 3, a normal input pin 304 is provided corresponding to the fuse 303.
Buffer 3 that operates only at high voltage input
01 is added. At the time of inputting the normal voltage to the input pin 304, only the buffer 302 operates, so the fuse 303 is not blown, and the pod for the fuse becomes unnecessary. In addition, when a high voltage is input to the input pin 304, the buffer 301 operates and the fuse 303 is blown, which can be used as marking. As described above, by using the two types of buffers, there is an advantage that the pad can be effectively used.

In the case of the second embodiment, the procedure for testing the IC on the wafer is the same as that of the flow chart in the first embodiment.

[0013]

As described above, according to the present invention, the test result can be marked by fusing the fuse arranged in the IC, and the marking is incorporated in the IC chip as a circuit. for,
Even if the chip size is different, there is an effect that it is not necessary to perform the adjustment, and marking can be performed even for a small chip.

[Brief description of drawings]

FIG. 1 is a diagram showing a layout of a semiconductor integrated circuit to which a first embodiment of the present invention is applied.

FIG. 2 is a flowchart showing a test procedure in the present invention.

FIG. 3 is a partial circuit diagram showing the periphery of a fuse in the second embodiment of the present invention.

[Figure 4]
/ It is a flowchart which shows the test procedure in a prior art example.

[Explanation of symbols]

 101 to 112 pads 113, 114, 303 fuses 115 mounted component chips 116 substrates 301, 302 buffers 304 input pins

Claims (1)

[Claims] 1. An IC is provided with a fuse capable of discriminating the presence / absence of a disconnection according to its appearance, and a circuit arrangement for fusing the fuse through a signal input from a predetermined external terminal. An IC marking circuit, wherein the IC is marked by blowing the fuse with reference to a test result in a wafer state of the IC.