JPH05218230A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05218230A JPH05218230A JP4014885A JP1488592A JPH05218230A JP H05218230 A JPH05218230 A JP H05218230A JP 4014885 A JP4014885 A JP 4014885A JP 1488592 A JP1488592 A JP 1488592A JP H05218230 A JPH05218230 A JP H05218230A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- resin
- substrate
- semiconductor element
- glass substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000011521 glass Substances 0.000 claims abstract description 22
- 229920005989 resin Polymers 0.000 claims abstract description 22
- 239000011347 resin Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000005540 biological transmission Effects 0.000 claims abstract description 3
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 239000005871 repellent Substances 0.000 abstract description 2
- 230000002940 repellent Effects 0.000 abstract 1
- 239000000919 ceramic Substances 0.000 description 7
- 238000002834 transmittance Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000003822 epoxy resin Substances 0.000 description 4
- 229920000647 polyepoxide Polymers 0.000 description 4
- 238000001444 catalytic combustion detection Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 238000004382 potting Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- RSWGJHLUYNHPMX-UHFFFAOYSA-N Abietic-Saeure Natural products C12CCC(C(C)C)=CC2=CCC2C1(C)CCCC2(C)C(O)=O RSWGJHLUYNHPMX-UHFFFAOYSA-N 0.000 description 1
- 244000025254 Cannabis sativa Species 0.000 description 1
- KHPCPRHQVVSZAH-HUOMCSJISA-N Rosin Natural products O(C/C=C/c1ccccc1)[C@H]1[C@H](O)[C@@H](O)[C@@H](O)[C@@H](CO)O1 KHPCPRHQVVSZAH-HUOMCSJISA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- KHPCPRHQVVSZAH-UHFFFAOYSA-N trans-cinnamyl beta-D-glucopyranoside Natural products OC1C(O)C(O)C(CO)OC1OCC=CC1=CC=CC=C1 KHPCPRHQVVSZAH-UHFFFAOYSA-N 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14618—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に関し、特に
ＣＣＤ等の固体撮像素子を搭載した半導体装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a solid-state image pickup device such as a CCD.
【０００２】[0002]
【従来の技術】従来の半導体装置は、図３に示すような
セラミックパッケージに搭載されているタイプと、図４
に示すような透光樹脂でトランスファー成形されている
クリアモールドタイプの２種が主たる構造である。2. Description of the Related Art A conventional semiconductor device is of a type mounted in a ceramic package as shown in FIG.
The main structures are two types of clear molds, which are transfer molded with a translucent resin as shown in (1).
【０００３】図３のセラミックパッケージ構造の半導体
装置は、低融点ガラス１３等により具備された外部リー
ド１９とボンディングワイヤ１８により電気接続された
半導体素子１は、セラミック基体１２に搭載され、ウイ
ンドウフレーム１４上の封着樹脂１５等でガラスキャッ
プ１７と封着されている。In the semiconductor device having the ceramic package structure shown in FIG. 3, the semiconductor element 1 electrically connected to the external lead 19 provided by the low melting point glass 13 and the like by the bonding wire 18 is mounted on the ceramic substrate 12, and the window frame 14 is provided. It is sealed to the glass cap 17 with the above sealing resin 15 or the like.
【０００４】また図４のクリアモールド構造の半導体装
置は、アイランド２０上に載置された半導体素子１が、
外部リード１９とボンディングワイヤ１８により接続さ
れ、透光樹脂からなる封入樹脂にてトランスファ成形さ
れている。なお、装置表面のガラス板２２は、半導体素
子１に入射する可視光が樹脂表面で乱反射し、フォトダ
イオードの電圧変動を防止するために取り付けてある。
前述したセラミックパッケージ構造とクリアモールド構
造の半導体装置の本体厚は、それぞれ約３〜６ｍｍ，２
〜３ｍｍ程度である。In the semiconductor device having the clear mold structure of FIG. 4, the semiconductor element 1 mounted on the island 20 is
The external leads 19 are connected to the bonding wires 18, and transfer molding is performed with an encapsulating resin made of a translucent resin. The glass plate 22 on the surface of the device is attached in order to prevent the visible light incident on the semiconductor element 1 from being diffusely reflected on the resin surface and to prevent the voltage fluctuation of the photodiode.
The body thickness of the semiconductor device having the above-mentioned ceramic package structure and the clear mold structure is about 3 to 6 mm and 2 respectively.
It is about 3 mm.
【０００５】[0005]
【発明が解決しようとする課題】ＣＣＤ等の半導体装置
は、コピー機やファックス，カメラ等の装置機器に使用
されているが、年々装置の小型，軽量化が進んでおり、
半導体装置には一層の軽薄短小化及び光高感度機能が要
求されている。Semiconductor devices such as CCDs are used in equipment such as copiers, fax machines, cameras, etc., and the size and weight of the devices are increasing year by year.
Semiconductor devices are required to be lighter, thinner, smaller, and highly sensitive to light.
【０００６】図３のような従来の半導体装置は、セラミ
ック，ガラスの多層構造であるため、重厚で大型を余儀
なくされた。そこで、図４のような半導体装置が出現し
ているが、軽量化の効果はあるものの、耐湿性，感度に
問題があった。封入樹脂のエポキシ樹脂は透光率を向上
させるために、熱膨張の低いシリカ等のフィラーを添加
できないため、半導体素子のシリコン（Ｓｉ），リード
の４２合金に比べ、熱膨張率が１０倍以上と大きく半導
体装置には熱膨張差から来る熱応力が発生し、樹脂クロ
ックや、界面割れ等を起こした。Since the conventional semiconductor device as shown in FIG. 3 has a multilayer structure of ceramic and glass, it is heavy and large in size. Therefore, although a semiconductor device as shown in FIG. 4 has appeared, there is a problem in humidity resistance and sensitivity although it has an effect of weight reduction. The epoxy resin as the encapsulating resin has a coefficient of thermal expansion of 10 times or more as compared with silicon (Si) of the semiconductor element and 42 alloy of the lead because a filler such as silica having a low coefficient of thermal expansion cannot be added in order to improve the light transmittance. As a result, thermal stress caused by the difference in thermal expansion occurred in the semiconductor device, causing resin clocks and interface cracks.
【０００７】また、樹脂の透光率の低下，感度の低下は
樹脂厚，樹脂の純度に比例して大きくなり、入射光の乱
反射防止に使用するガラス板等による補助でも不充分で
あった。Further, the decrease in the light transmittance of the resin and the decrease in the sensitivity increase in proportion to the resin thickness and the purity of the resin, and the assistance by a glass plate or the like used to prevent the diffuse reflection of incident light was not sufficient.
【０００８】本発明の目的は、前記問題点を解決し、小
型で、透光率をよくした半導体装置を提供することにあ
る。An object of the present invention is to solve the above problems and to provide a small-sized semiconductor device having an improved light transmittance.
【０００９】[0009]
【課題を解決するための手段】本発明の半導体装置の構
成は、絶縁基板上に半導体素子をはんだバンプにより接
続するフリップチップ構造の半導体装置において、前記
絶縁基板が光透過用ガラス基板から成り、少なくとも前
記半導体素子を樹脂により被覆することを特徴とする。The structure of a semiconductor device of the present invention is a semiconductor device having a flip chip structure in which semiconductor elements are connected to an insulating substrate by solder bumps, wherein the insulating substrate is a glass substrate for light transmission. At least the semiconductor element is coated with a resin.
【００１０】[0010]
【実施例】図１は本発明の一実施例の半導体装置を示す
断面図である。1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【００１１】図１において、本実施例は、ガラス基板２
の一主面にはんだバンプ３接合用のバンプ端子４が設け
られ、さらにビアホール５を介して、反対面の実装端子
６まで導出され、バンプ端子４の半導体素子１の電極と
はんだバンプ３にて接合する。In FIG. 1, a glass substrate 2 is used in this embodiment.
The bump terminals 4 for joining the solder bumps 3 are provided on one main surface, and further led out to the mounting terminals 6 on the opposite surface via the via holes 5, and the electrodes of the semiconductor element 1 of the bump terminals 4 and the solder bumps 3 are formed. To join.
【００１２】ガラス基板２は、板厚０．３〜０．８ｍｍ
のソルダーガラス、端子ビアホール５は、Ａｇ Ｃｕ
Ａｕ等を主とした厚膜印刷とし、はんだバンプ接合部に
はＴｉ，Ｃｕ，Ｃｒ等の蒸着膜を有し、はんだバンプ３
はＰｂ−５％Ｓｎを中心に設けた。The glass substrate 2 has a plate thickness of 0.3 to 0.8 mm.
The solder glass and the terminal via hole 5 are made of Ag Cu.
Thick film printing mainly made of Au or the like is used, and a solder bump bonding portion has a vapor deposition film of Ti, Cu, Cr or the like.
Was mainly provided with Pb-5% Sn.
【００１３】はんだバンプ３の接続には、あらかじめロ
ジン系のフラックスを薄く塗布したバンプ端子４上に、
半導体素子１上に設けたはんだバンプ３を位置決めし
て、軽く押しあて、赤外リフロー炉で加熱融着させた。
洗浄後、エポキシ樹脂を主成分とし、主フィラーにシリ
カを２０〜６０ｖｏｌ％含有した樹脂８をポッティング
により滴下し、１５０℃，２時間の条件で硬化させた。
樹脂８を高さは、０．４〜０．７ｍｍとなり、半導体装
置の全体厚は０．７〜１．５ｍｍとなった。To connect the solder bumps 3, the bump terminals 4 to which a rosin-based flux is thinly applied in advance are used.
The solder bumps 3 provided on the semiconductor element 1 were positioned, pressed lightly, and heated and fused in an infrared reflow furnace.
After washing, a resin 8 containing an epoxy resin as a main component and containing silica in an amount of 20 to 60 vol% as a main filler was dropped by potting and cured at 150 ° C. for 2 hours.
The height of the resin 8 was 0.4 to 0.7 mm, and the total thickness of the semiconductor device was 0.7 to 1.5 mm.
【００１４】なお、ガラス基板２上の半導体素子１周囲
に相当する箇所にあらかじめ溌油性のエポキシ樹脂を印
刷塗布し、１５０℃，１時間で硬化させ、ポッティング
樹脂の流れ停め１６を、高さ０．１〜０．２ｍｍで造っ
ておくと良い。An oil-repellent epoxy resin is preliminarily applied by printing onto a portion of the glass substrate 2 corresponding to the periphery of the semiconductor element 1 and cured at 150 ° C. for 1 hour to stop the flow of potting resin 16 at a height of 0. It is good to make it with 0.1 to 0.2 mm.
【００１５】図２は本発明の他の実施例の半導体装置を
示す断面図である。FIG. 2 is a sectional view showing a semiconductor device according to another embodiment of the present invention.
【００１６】図２において、本実施例は、ガラス基板２
上に設けるバンプ端子４をガラス基板２の端部まで引き
出し、外部リード接続端子９とし、外部リード１１をク
リップ１０でガラス基板２にはさみ、はんだ２４で電気
接続したものである。この場合、外部リード１１の形状
を自在にすることで、実装の自由度に対応することが可
能である。本実施例も、流れ停め１６があるとよい。In FIG. 2, the glass substrate 2 is used in this embodiment.
The bump terminals 4 provided on the glass substrate 2 are pulled out to the ends of the glass substrate 2 to form external lead connection terminals 9, the external leads 11 are sandwiched between the glass substrates 2 by the clips 10 and electrically connected by the solder 24. In this case, the flexibility of mounting can be accommodated by making the shape of the external lead 11 flexible. Also in this embodiment, the flow stop 16 may be provided.
【００１７】[0017]
【発明の効果】以上説明したように、本発明は、特にガ
ラス基板と半導体素子との間を中空にした樹脂被覆型の
ＣＯＧ（Ｃｈｉｐ Ｏｎ Ｇｒａｓｓ）構造とした場合
には、半導体装置の軽薄短小化を、従来のパッケージの
半分以下まで行うことが可能となる効果と、半導体素子
表面の樹脂被覆を行なわなくてすむことより、光の透過
率を低下させることなく、また樹脂表面の反射，内部の
不純物，ボイドによるフォトダイオードの受光量ばらつ
きを防止する効果とを兼ね備えている。As described above, according to the present invention, particularly in the case of the resin-coated COG (Chip On Grass) structure in which the space between the glass substrate and the semiconductor element is hollow, the semiconductor device is light, thin, short and small. Since it is possible to achieve up to half or less of the conventional package, and because it is not necessary to cover the surface of the semiconductor element with resin, the light transmittance is not reduced, and the reflection and internal reflection of the resin surface It also has the effect of preventing variations in the amount of light received by the photodiode due to the impurities and voids.
【００１８】また、本発明によれば、半導体装置の厚さ
を、１ｍｍ程度に薄く、また幅も１〜３ｍｍ程度とする
ことができることから、ハンディタイプの実装装置のセ
ンサー取付部を小型にすることが可能となり、集光レン
ズをガラス基板にダイレクト取り付けが可能で、取り付
け精度も向上する。Further, according to the present invention, the thickness of the semiconductor device can be reduced to about 1 mm and the width can be set to about 1 to 3 mm. Therefore, the sensor mounting portion of the handy type mounting device can be made compact. It is possible to directly attach the condenser lens to the glass substrate, and the attachment accuracy is improved.
【００１９】なお、本発明の実施例は、ＣＣＤを中心に
説明したが、紫外線消去型ＰＲＯＭの搭載も可能で、エ
ポキシ樹脂は紫外線の透過率が非常に低く、１０％以下
のため、本発明にもとずく中空樹脂被覆型ＣＯＧ構造の
半導体装置は軽薄短小ながら、カードなどの実装に機能
低下なく適用できる。Although the embodiments of the present invention have been described focusing on the CCD, it is possible to mount an ultraviolet erasable PROM, and the epoxy resin has a very low ultraviolet transmittance of 10% or less. The semiconductor device having a hollow resin-covered COG structure is basically light, thin, short, and small, but can be applied to a card or the like without functional deterioration.
【図１】本発明の一実施例の半導体装置を示す断面図で
ある。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
【図２】本発明の他の実施例の断面図である。FIG. 2 is a sectional view of another embodiment of the present invention.
【図３】従来のセラミックパッケージタイプの断面図で
ある。FIG. 3 is a sectional view of a conventional ceramic package type.
【図４】従来のクリアモールドタイプの断面図である。FIG. 4 is a sectional view of a conventional clear mold type.
１ 半導体素子 ２ ガラス基板 ３ はんだバンプ ４ バンプ端子 ５ ビアホール ６ 実装端子 ７ 中空 ８ 樹脂 ９ 外部リード接続端子 １０ リードクリップ １１ 外部リード １２ セラミック基体 １３ 低融点ガラス １４ ウィンドウフレーム １５ 封着樹脂 １６ 流れ停め １７ ガラクキャップ １８ ボンディングワイヤ １９ 外部リード ２０ アイランド ２１ 封入樹脂 ２２ ガラス板 1 Semiconductor Element 2 Glass Substrate 3 Solder Bump 4 Bump Terminal 5 Via Hole 6 Mounting Terminal 7 Hollow 8 Resin 9 External Lead Connection Terminal 10 Lead Clip 11 External Lead 12 Ceramic Substrate 13 Low Melting Glass 14 Window Frame 15 Sealing Resin 16 Flow Stop 17 Garacap 18 Bonding wire 19 External lead 20 Island 21 Encapsulation resin 22 Glass plate
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/14 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 27/14
Claims (2)
により接続するフリップチップ構造の半導体装置におい
て、前記絶縁基板が光透過用ガラス基板から成り、少な
くとも前記半導体素子を樹脂により被覆することを特徴
とする半導体装置。1. A semiconductor device having a flip chip structure in which a semiconductor element is connected to an insulating substrate by solder bumps, wherein the insulating substrate is a glass substrate for light transmission, and at least the semiconductor element is covered with a resin. Semiconductor device.
の間が、中空となっている請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a space between the glass substrate and the surface light receiving portion of the semiconductor element is hollow.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4014885A JPH05218230A (en) | 1992-01-30 | 1992-01-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4014885A JPH05218230A (en) | 1992-01-30 | 1992-01-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05218230A true JPH05218230A (en) | 1993-08-27 |
Family
ID=11873473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4014885A Withdrawn JPH05218230A (en) | 1992-01-30 | 1992-01-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05218230A (en) |
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| WO1997002596A1 (en) * | 1995-06-30 | 1997-01-23 | Kabushiki Kaisha Toshiba | Electronic component and method of production thereof |
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1992
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| Date | Code | Title | Description |
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| A300 | Withdrawal of application because of no request for examination |
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