JPH05206376A - Laminated multi-chip semiconductor device - Google Patents

Abstract

PURPOSE:To provide a space between a terminal and a lead and improve solder permeability by providing a spacer on the terminal of a connector frame. CONSTITUTION:A connector frame 2a is provided with a front plane terminal, a rear plane terminal 26a and a rear plane terminal 27a. A front plane spacer 30a and a rear plane spacer 31a are formed on the top plane of the frame 2a. The front plane terminal 26a and the rear plane terminal 27a are connected by an edge plane through hole 29a. A connector frame 2b has a same structure as the connector frame 2a. The outer lead 15a of a TCP 1a passes between the front plane terminal 26a and the rear plane terminal 27b being sandwiched between the front plane spacer frame 2a and a rear plane spacer 31b and reaches the edge of the connector frame. Solder 33a wets the through hole 29a, the front plane terminal 26a and the rear plane terminal 27b and fills the whole connecting part. Solder 5 can be filled in the space between a board 34, which faces a board spacer 35 and the rear plane spacer 31a of the connector frame 2a making contact and that holds a fixed space by the spacer, and the rear plane terminal of the connector frame 2a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device used in information equipment and the like, and more particularly to a laminated multi-chip semiconductor device which has a large capacity and can secure high reliability of a connecting portion.

[0002]

2. Description of the Related Art Semiconductor memories are used in large quantities in information devices such as large computers, workstations, personal computers, word processors, etc., and it is expected that these devices will have higher performance, more functions and more products in the future. Therefore, it is considered that the demand for the semiconductor memory used here will increase at an accelerating rate. In this case, in an apparatus that requires a large capacity memory, the mounting area occupied by the semiconductor memory in the device tends to increase more and more, which is the biggest factor inhibiting the miniaturization and weight reduction of the device.

As a method for solving this problem, a method of increasing the memory capacity per chip by increasing the integration of elements in the chip, which has been strongly promoted conventionally, or
A method for mounting a packaged memory module on a printed wiring board at high density, or Japanese Patent Laid-Open No. 59-180386.
As described in JP-A-61-101067 and JP-A-61-101067, there is a method of stacking a plurality of semiconductor chips in the thickness direction to increase the density.

Among these methods, the method of densifying the elements in a chip has reached a new stage that cannot be solved by extending the conventional technology, and it is necessary to develop new technology and new production equipment. As for the method of high-density mounting on a printed wiring board, miniaturization of the module, double-sided mounting on the printed wiring board, and the use of ZIP (zigzag in-line-package) components have been adopted. As far as the module with one package is used, it is difficult to further increase the density.

On the other hand, a method of stacking a plurality of IC chips in the thickness direction is extremely advantageous, and various proposals have been made so far.

[0006]

However, in the methods presented so far, including the disclosure in the above publication, the terminals of each layer are closely connected to each other, so that the reliability of the connection cannot be sufficiently ensured. There was a problem.

An object of the present invention is to solve the problems of the prior art and to provide a large-capacity multi-chip semiconductor device which ensures high reliability of the connection portion.

[0008]

The above object is to provide a laminated multi-layer structure in which a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape are laminated and connected through a connector frame having a connection terminal on at least one surface thereof. In the chip semiconductor device, a multi-chip semiconductor device in which at least one surface of the connector frame is formed with an insulating film thicker than the connection terminal thickness, or a projection is formed on a part of the terminal on at least one surface of the connector frame A multi-chip semiconductor device, or
In a laminated multi-chip semiconductor device in which a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape are laminated and connected via a connector frame having a wiring pattern on at least one surface thereof, one end of the connector frame is a connector frame end. To be a laminated multi-chip semiconductor device having a structure exposed at a portion, or a plurality of tape carrier packages in which semiconductor chips are electrically connected to a film carrier tape having a wiring pattern on at least one surface are laminated through a connector frame. In the connected multi-chip semiconductor device, a lead of the film carrier package has a tape carrier package which is exposed to the same end as or more than the end face of the connector frame terminal. Especially It can be achieved me.

[0009]

With the above structure, the thickness of the joint solder between the layers can be ensured to be a certain thickness or more, and sufficient solder can be supplied to the connecting portion, so that the connection of the connecting portion can be highly reliable. Can be secured.

[0010]

EXAMPLES The structure of the multi-chip semiconductor device of the present invention will be specifically described below with reference to examples.

An embodiment of the multi-chip semiconductor device of the present invention will be described with reference to FIGS. In each drawing, the same reference numerals indicate the same contents, and the tape carrier package
(Hereinafter, abbreviated as TCP) and in a diagram in which a plurality of connector frames are stacked, from the bottom to the top, after each code numeral
It was classified by adding symbols such as a, b, c, and d.

First, FIG. 1 is a view showing a cross section of a module in which TCP 1 and connector frame 2 are alternately stacked and electrically connected multi-chip semiconductor device 6 of the present invention is connected to mother board 4 by solder 5. is there. That is, the connector frames 2 and the TCPs 1 are alternately stacked in four stages, a lid is attached to the uppermost layer, and they are joined by solder to form a multi-chip semiconductor device 6. The multi-chip semiconductor device 6 is soldered on the motherboard 4. Indicates that they are connected to.

Next, FIG. 2 shows a plan view of the TCP 1, and FIG. 3 shows a cross section taken along the line A--A in FIG. In these figures, the bumps 11 are formed on the upper surface of the semiconductor chip 10.
The inner lead 13 formed on the film carrier tape 12 is connected to the film carrier tape 12
The support ring 14 formed of a part of the base material holds the leads, and also has a role of a wiring area for increasing the lead pitch from the inner leads 13 to the outer leads 15.

A protective coat resin 16 is applied to the surface of the semiconductor chip 10 and the support ring portion 14 including the inner lead bonding portion. The leads arranged in the short side direction include a chip selection lead 18 connected to the chip selection bump 17, a common lead 15 connected to other bumps 11, and a dummy lead 19 not connected to the bump. In addition, the temporary fixing lead 20 is provided on the support ring 14 in the long side direction.
Are arranged.

Next, FIG. 4 is a plan view of the connector frame, FIG. 5 is an enlarged plan view of a part of the connector frame, and FIG. 6 is a side view of FIG.
Figure 7 shows a cross-sectional view of section AA in Figure 5. 4 to 7, front and rear terminals 26 and 27 are formed on the front and rear surfaces of the base material 25, and the front and rear terminals are electrically connected by end face through holes 29 having front and rear lands 28. ing. Front side spacer 30 and back side spacer on the inner part of the terminal
31 is formed. Further, a temporary fixing terminal 32 is arranged on the surface of the base material 25 in the longitudinal direction.

FIG. 8 is a partially enlarged sectional view of the connecting portion. In this figure, surface terminals are provided on the first-stage connector frame 2a.
26a and a back surface terminal 27a are formed, and a surface spacer 30a and a back surface spacer 31a are formed on the upper surface of the terminal. The front surface terminal 26a and the back surface terminal 27a are connected by an end surface through hole 29a. The second-stage connector frame 2b is also the first
It has the same structure as that of the connector frame 2a at the stage. The outer lead 15a of the TCP 1a has a front surface spacer 30a and a rear surface spacer 31b.
It passes between the front-side terminal 26a and the back-side terminal 27b while reaching the end of the connector frame. Also, solder 33a
The end surface through hole 29a, the front surface terminal 26a, and the back surface terminal 27b are wet to fill the entire connecting portion.

A substrate terminal 34 is formed on the mother board 4, and a substrate spacer 35 is formed on the substrate terminal 34. The board spacer 35 and the back surface spacer 31a of the connector frame 2a face each other and are in contact with each other, and the solder 5 is placed between the board terminal 34 and the back surface terminal 27a of the connector frame 2a, which are held at a constant distance by these spacers. It is filled.

FIG. 9 is a circuit block diagram for explaining the operation of the multichip semiconductor device 6. In this figure, the semiconductor chips 10a, 10b, 10c, and 10d have address terminals 40, data input / output terminals 41, write enable terminals 42,
Out enable terminal 43, power supply terminal 44, ground terminal 4
5. Chip select terminals 46a, 46b, 46c, 46d are electrically connected. Of these terminals, chip select terminals 46a-4
6d is independently connected to each of the semiconductor chips 10a to 10d, but the other terminals are commonly connected to the semiconductor chips 10a to 10d. In FIG. 9, the address terminal 40
And the data input terminal 41 is shown by one line,
The actual wiring is composed of multiple wires. In contrast,
Write enable terminal 42, out enable terminal 43, power supply terminal 44, ground terminal 45, and chip selection terminals 46a to 46d
In many cases, there is one each for actual wiring.

In this circuit, first, when writing data to the semiconductor chip 10, necessary information is given to the address line and the data line as an electric signal, and the write enable signal line is set.
By turning on the chip select terminal of the chip whose information is to be stored after turning it on, predetermined information is stored at the desired address of the selected chip. Since the chip select terminals of the other three chips are kept off, there is no change in the information inside the chips. Similarly,
To read information from the chip, apply a signal indicating the address you want to retrieve information to the address line, turn on the data input / output enable terminal, and turn on the chip selection terminal from which you want to retrieve information. Information from the desired address of the selected chip is output to the data input / output terminal.

FIG. 10 is a perspective view of the chip selection terminal portion.
In this figure, the chip selection terminals are on the mother board 4.
50a to 50d are also chip selection terminals on the connector frame 2.
51a to 51d are formed. Further, on the TCP 1 side, chip selection bumps 17a to 17d are formed at the common positions of the semiconductor chips 10 of the respective stages, and these bumps 17a to 17d are formed.
And the chip selection leads 18a to 18d having different pattern shapes are formed in each step.
Of the chip selection terminal 51. Three dummy leads 19 that are not connected to the bumps on the chip are formed on the TCP 1 film, and these dummy leads 19 are connected to the terminals of the connector frame 2.

11 and 12 are enlarged cross-sectional views of the connection portion showing the connection state between the connector frame terminal, the TCP 1 lead and the multi-chip semiconductor device 6 and the mother board 4, and FIG. 11 is a common terminal portion (A- in FIG. 9). (Part A position), Fig. 12 shows the semiconductor 10d on the fourth level.
FIG. 11 is an enlarged cross-sectional view of a connection portion at a chip selection position where is connected to the motherboard (position BB in FIG. 9). In FIG. 11, board terminals 34 are formed on the surface of the mother board 4, and board spacers 35 are formed on the board terminals 34. The connector frame 2a and the connector frame 2b are connected to each other by solder while sandwiching the outer cord 15a of the TCP 1a.
Similarly, the connector frame 2b, the connector frame 2c, and the connector frame 2
c and connector frame 2d, connector frame 2d and lid 3
The outer lead 15 of TCP 1 is sandwiched and connected by solder 33. The connector frame 2a and the mother board 4 are connected by solder 5.

In FIG. 12, the chip selection bumps 17d are connected to the chip selection leads 18d, and the respective connector frames are connected by solders 33a to 33d with a dummy lead 19 interposed therebetween. Is electrically connected to the chip selection substrate terminal 50d arranged at.
On the other hand, the chip selection bumps 17a to 1
7c is not connected to the lead at this cross-sectional position.

The detailed structure of each part of the multi-chip semiconductor device according to the present invention having such a structure will be described below.

First, in FIG. 1, a mother board 4 is a printed wiring board having single-layer and multi-layer wirings, and other semiconductor components and general electric components are mounted on the surface thereof along with the multi-chip semiconductor device 6 shown in this figure. What I did
It is a part of an electronic device having functions such as input / output, calculation, storage and display (wiring and other parts are not shown).

2 and 3, the semiconductor chip 10 is made of silicon and has a memory element formed therein.
A dynamic random access memory having a storage capacity of bits. Gold bumps 11 and 17 formed by a plating method are arranged on the surface of the semiconductor chip 10 as terminals for inputting and outputting signals.

The film carrier tape 12 is obtained by fixing a copper foil to a polyimide film and patterning the copper foil to form a lead, and the lead surface after patterning is plated with gold using nickel as a base.

The inner leads 13 formed on the film carrier tape are aligned with the bumps 11 and 17 on the semiconductor chip 10, the heating block is pressed against the inner leads 13, and the connection is made by a gold-gold thermocompression bonding method. To do.

Here, the bumps 11 on the semiconductor chip 10 and
The formation of 17 is not particularly limited to the formation by a plating method, and a small piece of gold formed in a separate step in advance is fixed, or the gold wire is formed by using the principle of wire bonding. A method such as thermocompression bonding to the shape can also be applied. Further, the material is not limited to gold, and may be copper, nickel and alloys thereof.

Further, the surface treatment of the leads on the film carrier tape is not limited to gold plating, and tin plating, solder plating, etc. can be sufficiently applied. Further, the material of the lead is not limited to copper, and copper alloy, iron, iron alloy, etc. can be applied.

The protective coat protects the surface of the chip 10 and the inner lead 13 portion. In this embodiment, an epoxy resin is used. Although the bumps 11 and 17 on the chip are arranged on the short side in FIG. 2,
Of course, those arranged on the long side, those arranged on the four sides, and those arranged in the central portion of the chip are also included.

In FIG. 2, the temporary fixing lead formed on the long side is used for temporary connection when the TCP 1 and the connector frame 2 are aligned and fixed. That is,
In the process of connecting TCP1 and connector frame 2 in multiple layers, first, a set of TCP 1 and connector frame 2 is temporarily fixed to form a TCP with a connector frame (hereinafter abbreviated as TCP with a frame). , The connector frame 2 and TCP 1 are aligned using the alignment marks (not shown) provided on each, and the above-mentioned temporary fixing leads of TCP 1 are thermocompression bonded to the temporary fixing terminals of the connector frame. To do.

The connector frame 2 shown in FIG. 4 to FIG.
This is to connect the leads of each TCP1 when a plurality of TCPs are stacked and connected, and at the same time to keep the interval between TCPs constant.

In FIGS. 4 to 8, the connector frame 2 is a through-hole for connecting the front and back patterns by forming a pattern on the front and back using a double-sided copper-clad laminate of glass epoxy base material 25 to form a connection terminal. Is formed, and a resin layer to serve as a spacer is formed on a part of the connection terminal by a screen printing method, and then the outer shape is punched out by a mold into the shape shown in FIG. The front and back patterns and through holes are solder-plated on copper plating. In the above punching,
By designing the mold so as to cut along the center line of the through hole, the end face through hole 29 in which a part of the inner wall of the through hole is exposed is formed. The temporary fixing terminal is used for temporary connection with TCP 1, as described above.

In this embodiment, a double-sided copper-clad laminate of glass epoxy base material 25 was used for the connector frame 2, but the material of the connector frame 2 is not limited to this, and other organic resins or ceramics, etc. Inorganic materials can also be used.

The spacers 30 and 31 ensure the thickness of the solder connecting layer at the time of stacking connection, and the solder at the connecting portion is TCP 1
It is an epoxy resin that withstands the soldering temperature to prevent it from penetrating inside through the leads.However, this is not limited to epoxy resin, and other organic resins or ceramics can be used. Inorganic materials such as can be used. Further, when the front and back patterns are formed, it is also possible to form a part of the pattern at the spacer position shown in the figure by convex plating or plating. The surfaces of the front and back patterns other than the portions covered by the spacers are the connection terminals that contribute to the connection. Although the surface of the terminals on the connector frame is plated with solder, this is not limited to solder, and may be gold, tin, or copper when a through hole is formed.

In FIGS. 2 and 10, since the bump 17 for chip selection on the multi-chip semiconductor device 6 is arranged at a fixed position on the chip 10, the type of chip is not affected by the stacking step. One kind is enough. Also, the connector frame 2
As for each stage, the same pattern position may be used for each stage, and only one type may be used. On the other hand, since the film carrier tape 12 has different pattern shapes for each step, four types are prepared according to each pattern.
As shown in FIG. 12, the dummy lead 19 on the TCP 1 is for connecting between the connector frames 2 at the respective stages of the chip selection terminal portion.

The lid shown in FIGS. 1 and 10 protects the inside when the multi-chip semiconductor device 6 is mounted on the mother board 4 by using a printed wiring board having no hollow inside, and protects the terminals formed on the surface. By making the area large, it is possible to easily perform the electrical characteristic inspection when four layers are stacked.

Now, a method of stacking and connecting the TCP 1 and the connector frame 2 will be described. For stacking connection of TCP 1 and connector frame 2, first align TCP 1 and connector frame 2 of each stage and temporarily fix them to make TCP 1 with frame, then
Align TCP 1 in 4 steps, and then align the lid on the top layer and connect them in layers. Here, for temporary fixing of the TCP 1 with a frame, the temporary fixing terminal 32 of the connector frame 2 and the temporary fixing lead 20 of the TCP 1 are pressure-bonded by a pulse heat type thermocompression bonding method. In this case, since solder plating is used for the terminals of the connector frame 2 and gold plating is used for the TCP 1 paste, solder reflow connection is possible without the use of flux, and no cleaning is required after this step. There is an advantage. In addition, although the temporary fixing by thermocompression bonding is described in the present embodiment, a method such as fixing by an adhesive or fixing by mechanical clamping can be applied.

Further, for temporarily fixing the four TCP 1s with the frame and the lid of the uppermost layer, the positions were sequentially aligned from the first one by one, and the adhesives were temporarily fixed. In this case, the upper framed TCP 1 was pressed with a constant load when the adhesive was cured so that the thickness of each connection layer was constant. After aligning the four TCPs with a frame with the lid of the uppermost layer and temporarily fixing it, apply flux for soldering to the connection part and immerse the end through hole 29 part in the molten solder to solder the connection part. I added it.

The multi-chip semiconductor device 6 thus connected by soldering is aligned and arranged on the mother board 4 on which solder printing is performed, and soldered by vapor reflow soldering to obtain a multi-chip semiconductor module.

FIG. 11 is a cross-sectional view of the connecting portion of this multi-chip semiconductor module, which shows the mother board 4, the multi-chip semiconductor device 6, the terminals of the connector frame of each stage and the TCP.
It shows that the lead of 1 is completely connected by the solder.

Next, regarding an application example of this embodiment, FIG.
Explain by 14.

FIG. 13 is a sectional view of a connecting portion between the terminal of the connector frame 2 and the outer lead of TCP 1. In this figure, the outer lead 15a of the TCP 1 sandwiched between the front terminal 26a of the connector frame 2a and the rear terminal 27b of the connector frame 2b.
Is a structure in which L is extended from the end of the connector frame 2.

FIG. 14 is a plan view of the connecting portion shown in FIG. In this figure, the tip portion of the outer lead 15 is wider than the original portion, and is almost the same size as the land 28. Further, FIGS. 15 and 16 are enlarged views of a cross section of the connection portion after solder connection, FIG. 15 shows a connection portion with good solder wettability of leads, and FIG. 16 shows a state of a connection portion with poor wettability. Is.

The present embodiment provides a structure capable of surely performing the solder wettability test of the TCP 1 lead at the time of assembling the multi-chip semiconductor device and connecting the solder. That is, as shown in FIGS. 13 and 14, by extending the outer leads from the ends of the connector frame 2,
By making the width of the tip of the outer lead 15 equal to the width of the end face through hole 29, when the solder wettability is good, a good solder fillet 60 is formed as shown in FIG. 15, and when the wettability is bad. Since the solder fillet is not formed in the solder as shown in FIG. 16, the solder wettability can be easily inspected from the outside.

[0046]

As described above, by using a multi-chip semiconductor device as the device of the present invention, the problems of the prior art can be solved and a high reliability of the connecting portion can be secured. A multi-chip semiconductor device having a capacity can be provided.

That is, by providing the spacers on the terminals of the connector frame, it is possible to provide a constant space between the terminals and the leads. It was possible to greatly reduce the content ratio of gold, and it was possible to significantly improve the connection reliability. In addition, the end face through-hole structure exposes the connection part of the connector frame to the end face, and at the same time the end part of the TCP lead is also exposed. It has become possible to improve productivity and productivity. In addition, the soldering process by the molten solder method is possible, which simplifies the connection process, and the gold on the TCP lead surface diffuses into the molten solder, so that the gold content in the connection part can be suppressed to a very small amount. It was possible and the reliability of the connection could be improved significantly.

[Brief description of drawings]

FIG. 1 is a sectional view of a connecting portion of a multi-chip semiconductor device of the present invention.

FIG. 2 is a plan view of TCP.

FIG. 3 is a cross-sectional view taken along the line AA of FIG.

FIG. 4 is a plan view of a connector frame.

FIG. 5 is a partially enlarged plan view of a connector frame.

FIG. 6 is a side view of a connector frame.

FIG. 7 is a cross-sectional view of the AA portion of the connector frame.

FIG. 8 is a partially enlarged sectional view of a multi-chip semiconductor device.

FIG. 9 is a circuit block diagram of a multi-chip semiconductor device.

FIG. 10 is a perspective view of a chip selection terminal portion.

FIG. 11 is an enlarged cross-sectional view of a connection portion of a common terminal portion.

FIG. 12 is an enlarged cross-sectional view of a connection portion of a chip selection terminal portion.

FIG. 13 is a cross-sectional view of a connection portion between a connector frame terminal and a TCP outer lead.

14 is a plan view of the connection portion of FIG.

FIG. 15 is an enlarged cross-sectional view of a connection portion of a lead having good solder wetting.

FIG. 16 is an enlarged cross-sectional view of a connection portion of a lead having poor solder wetting.

[Explanation of symbols]

1 ... TCP (tape carrier package), 2 ... Connector frame, 4 ... Motherboard, 5, 33 ... Solder, 6 ... Multi-chip semiconductor device, 10 ... Semiconductor chip, 15 ... Outer lead, 18 ... Chip selection lead, 19 ... Dummy Reed,
26 ... front surface terminal, 27 ... rear surface terminal, 29 ... end through hole, 30 ... front surface spacer, 31 ... rear surface spacer, 50 ... chip selection board terminal, 51 ... chip selection terminal, 60 ... fillet.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hiroyuki Tanaka, Inventor Hiroyuki Tanaka, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside the Hitachi, Ltd. Institute of Industrial Science (72) Ichiro Miyano 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Address Company, Hitachi, Ltd., Production Engineering Laboratory (72) Inventor, Kazuo Yamazaki, 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo, Ltd., Hitachi, Ltd., Semiconductor Design and Development Center (72) Inventor, Munehiro Yamada, Kodaira, Tokyo 5-20-1 Joumizuhoncho, Ichi, Japan Semiconductor design and development center, Hitachi, Ltd.

Claims (22)

[Claims] 1. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages, each having a semiconductor chip electrically connected to a film carrier tape, are laminated and connected via a connector frame having a connection terminal on at least one surface thereof. A laminated multi-chip semiconductor device having an insulating film thicker than the thickness of the connection terminal on at least one surface thereof. 2. The laminated multi-chip semiconductor device according to claim 1, wherein the insulating film is formed on a base material of the connector frame. 3. The laminated multi-chip semiconductor device according to claim 1, wherein the insulating film is formed on the terminals of the connector frame. 4. The laminated multichip semiconductor device according to claim 1, wherein an organic resin is used for the insulating film. 5. The laminated multi-chip semiconductor device according to claim 1, wherein an inorganic insulating material is used for said insulating film. 6. The laminated multichip semiconductor device according to claim 1, wherein the insulating film is formed of a solder resist film. 7. The laminated multi-chip semiconductor device according to claim 1, wherein the insulating film is a ceramic insulating film. 8. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages, each of which has a semiconductor chip electrically connected to a film carrier tape, are laminated and connected via a connector frame having a connection terminal on at least one surface thereof. A multi-layered multi-chip semiconductor device having a protrusion formed on at least one surface of at least one of the terminals. 9. The stacked multi-chip semiconductor device according to claim 8, wherein the protrusion is made of the same material as the terminal. 10. The stacked multi-chip semiconductor device according to claim 8, wherein the protrusion is made of a material different from that of the terminal. 11. The stacked multi-chip semiconductor device according to claim 8, wherein the protrusions are formed by a plating method. 12. The laminated multi-chip semiconductor device according to claim 8, wherein the protrusions are formed by a printing method. 13. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages, each of which has a semiconductor chip electrically connected to a film carrier tape, are laminated and connected via a connector frame having a wiring pattern on at least one surface thereof. A laminated multi-chip semiconductor device having a structure in which one end of the upper pattern is exposed at an end of a connector frame. 14. The stacked multi-chip semiconductor device according to claim 13, wherein the pattern is a connection terminal. 15. The stacked multi-chip semiconductor device according to claim 13, wherein the connector frame is a connector frame having through holes penetrating the front and back sides. 16. The stacked multi-chip semiconductor device according to claim 13, wherein the through hole of the connector frame is a through hole. 17. A part of an inner wall of the through hole is exposed at an end of the connector frame.
16. A laminated multichip semiconductor device according to 16 above. 18. A laminated multi-chip semiconductor device according to claim 13, wherein the insulating film according to any one of claims 1 to 7 is added. 19. The laminated multi-chip semiconductor device according to claim 13, further comprising the protrusion formed in any one of claims 8 to 12. 20. A laminated multi-chip semiconductor device in which a plurality of tape carrier packages, each having a semiconductor chip electrically connected to a film carrier tape having a wiring pattern on at least one surface thereof, are laminated and connected via a connector frame. A multi-layer semiconductor device having a tape carrier package in which the lead of the above is exposed to the same or more than the end face of the connector frame terminal. 21. The laminated multi-chip semiconductor according to claim 20, wherein the lead width of the film carrier package located near the end of the connector frame is made wider than or equal to the terminal width of the connector frame. apparatus. 22. A stacked multi-chip semiconductor device according to claim 20, wherein a connector frame having at least one of the structures shown in claims 1 to 19 is used.