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JPH05205966A - Multilayer capacitor - Google Patents

Multilayer capacitor

Info

Publication number
JPH05205966A
JPH05205966A JP3418792A JP3418792A JPH05205966A JP H05205966 A JPH05205966 A JP H05205966A JP 3418792 A JP3418792 A JP 3418792A JP 3418792 A JP3418792 A JP 3418792A JP H05205966 A JPH05205966 A JP H05205966A
Authority
JP
Japan
Prior art keywords
electrodes
electrode
multilayer capacitor
holes
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3418792A
Other languages
Japanese (ja)
Inventor
Harufumi Bandai
治文 萬代
Giichi Kodo
義一 児堂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP3418792A priority Critical patent/JPH05205966A/en
Publication of JPH05205966A publication Critical patent/JPH05205966A/en
Pending legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Abstract

PURPOSE:To enable a multilayer capacitor to be increased in electric resonant frequency and decreased in equivalent series resistance by a method wherein two kinds of insulating sheets, where a region on which no electrode is located is provided inside electrodes, are superposed to form a multilayer body, and the same electrodes are connected to each other through a lead-out electrode which penetrates the region of the multilayer body where no electrode is located. CONSTITUTION:Two kinds of ceramic green sheets, where regions 13 and 14 on which no electrode is located are provided at different points inside electrodes 11 and 12, are alternately superposed as many as required and burned as pressed into a multilayer body 19. Through-holes 20 and 21 are provided to the laminate 19 vertically penetrating the regions 13 and 14 where no electrode is provided. The through-holes 20 and 21 connect the same electrodes 11 and 12 together to serve as the lead-out parts of them, but both the through- holes 20 and 21 are formed inside the electrodes 11 and 12, so that the electrodes 11 and 12 substantially have no lead-out part. Therefore, inductance and resistance accompanying lead-out electrodes are hardly generated, and by this setup, a multilayer capacitor can be increased in resonant frequency and decreased in equivalent series resistance.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、電気的共振周波数が
高く、かつ等価直列抵抗の低い積層コンデンサに関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor having a high electric resonance frequency and a low equivalent series resistance.

【0002】[0002]

【従来の技術】従来の積層コンデンサAは、図6に示す
ように表面に長方形の電極1を一方の端部に達するよう
に設けた複数枚のセラミックグリーンシート2を、電極
1の取出し側が逆になるよう交互に積み重ね、その上下
にセラミックグリーンシート3,4を重ねた状態で加圧
し、これを焼成すると共に、図7の如く両端部に外部電
極5,6を設け、両外部電極5,6を各電極1と交互に
接続した構造になっている。
2. Description of the Related Art In a conventional multilayer capacitor A, as shown in FIG. 6, a plurality of ceramic green sheets 2 each having a rectangular electrode 1 provided on one surface thereof so as to reach one end thereof are arranged on the opposite side from which the electrodes 1 are taken out. Alternately, the ceramic green sheets 3 and 4 are stacked one above the other and pressed to sinter them, and at the same time, external electrodes 5 and 6 are provided at both ends as shown in FIG. 6 has a structure in which electrodes 6 are alternately connected.

【0003】ところで、上記のような積層コンデンサA
は、図8に示すように電極1が対向する部分が実質的に
コンデンサを形成し、この対向する部分から距離が離れ
た位置で外部電極と電気的接続をとるため、電極1の対
向する部分から外部電極に達する部分の間が引出し電極
7となる。
By the way, the above multilayer capacitor A
As shown in FIG. 8, the portion where the electrodes 1 face each other substantially forms a capacitor, and the portion where the electrodes 1 face each other is electrically connected to the external electrode at a position away from the facing portion. The part between the part reaching from the external electrode to the external electrode is the extraction electrode 7.

【0004】[0004]

【発明が解決しようとする課題】上記のように、電極1
に引出し電極7が存在すると、図8の等価回路で示した
ように、この引出し電極7でインダクタンスや抵抗が発
生し、電気的共振周波数が低く、かつ等価直列抵抗(E
SR)が大きなコンデンサとなり、高周波帯での使用が
困難になるという問題がある。
As described above, the electrode 1
If the extraction electrode 7 exists in the lead electrode 7, as shown in the equivalent circuit of FIG. 8, inductance and resistance are generated in the extraction electrode 7, the electric resonance frequency is low, and the equivalent series resistance (E
There is a problem in that SR) becomes a large capacitor, making it difficult to use in a high frequency band.

【0005】そこで、この発明は、引出し電極を電極の
内部から取出すように構成し、電気的共振周波数が高
く、かつ等価直列抵抗を低くできる積層コンデンサを提
供することを目的とする。
Therefore, an object of the present invention is to provide a multilayer capacitor which is constructed so that the extraction electrode is taken out from the inside of the electrode and which has a high electric resonance frequency and a low equivalent series resistance.

【0006】[0006]

【課題を解決するための手段】上記のような課題を解決
するため、この発明は、表面に設けた電極の内側に電極
のない領域を異なった位置に形成した少なくとも二種類
の絶縁シートを積み重ねて積層体を形成し、前記積層体
に電極のない領域の部分を貫通するように設けたスルー
ホールもしくはビアホールの引出し電極で同一電極を互
に接続して積層体の外部に引出した構成を採用したもの
である。
In order to solve the above problems, the present invention stacks at least two kinds of insulating sheets in which regions without electrodes are formed at different positions inside electrodes provided on the surface. A laminated body is formed by using a structure in which the same electrodes are connected to each other with lead-out electrodes of through holes or via holes provided so as to penetrate through the area of the laminated body where there is no electrode, and the laminated body is drawn out of the laminated body. It was done.

【0007】[0007]

【作用】電極の内側で異なった位置に電極のない領域を
形成した少なくとも二種類の絶縁シートを積み重ねて積
層体を形成し、この積層体に電極のない領域部分を貫通
する引出し電極で同一電極を互に接続したので、引出し
電極を電極の中から取り出すことができ、実質的に電極
引出し部がほとんどない状態になり、電極引出し部がな
いので電気的共振周波数が高く、かつ等価直列抵抗の低
い積層コンデンサとなる。
[Operation] At least two kinds of insulating sheets in which regions without electrodes are formed at different positions inside the electrodes are stacked to form a laminated body, and the same electrode is formed by the extraction electrode penetrating the region without electrodes in the laminated body. Since they are connected to each other, the extraction electrode can be taken out from the electrode, and there is practically no electrode extraction part, and since there is no electrode extraction part, the electrical resonance frequency is high and the equivalent series resistance It is a low multilayer capacitor.

【0008】[0008]

【実施例】以下、この発明の実施例を添付図面の図1乃
至図5に基づいて説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS. 1 to 5 of the accompanying drawings.

【0009】図1に示すように、表面に設けた円形パタ
ーンの電極11,12の内側に電極のない領域13,1
4を異なった位置に形成した二種類のセラミックグリー
ンシート15と16を用意し、このセラミックグリーン
シート15と16を交互に所要枚数を積み重ね、その上
下にセラミックグリーンシート17,18を重ねた状態
で加圧焼成して積層体19を形成する。
As shown in FIG. 1, there are no electrodes 13 and 1 inside the circular patterns of electrodes 11 and 12 provided on the surface.
Prepare two kinds of ceramic green sheets 15 and 16 in which 4 is formed at different positions, stack the required number of these ceramic green sheets 15 and 16 alternately, and stack the ceramic green sheets 17 and 18 on the upper and lower sides. The laminate 19 is formed by pressurizing and firing.

【0010】上記積層体19には、図3のように両電極
11,12の電極のない領域13,14の部分を上下に
貫通するスルーホール20,21を設ける。
The laminated body 19 is provided with through holes 20 and 21 vertically penetrating the portions 13 and 14 of the electrodes 11 and 12 where there is no electrode, as shown in FIG.

【0011】このスルーホール20,21は、電極のな
い領域13,14よりも少し小径でしかも上記領域1
3,14の中心を貫通するように設けられ、これによっ
て両スルーホール20,21は電極のない領域13,1
4を貫通する部分においてはその電極と導通することが
なく、一方のスルーホール20は電極12を、他方のス
ルーホール21は電極11を貫通し、この貫通部分で各
々の電極11,12と電気的に接続されることになる。
The through holes 20 and 21 have a diameter slightly smaller than that of the regions 13 and 14 having no electrode, and the region 1 described above is used.
It is provided so as to penetrate through the centers of the electrodes 3 and 14, so that both through holes 20 and 21 are formed in the regions 13 and 1 without electrodes.
4 does not conduct with the electrode, and one through hole 20 penetrates the electrode 12 and the other through hole 21 penetrates the electrode 11, and at this penetrating portion, the electrodes 11 and 12 are electrically connected. Will be connected.

【0012】従って、両スルーホール20,21は、同
一の電極11,12を互いに接続して積層コンデンサA
を形成し、両スルーホール20,21は積層体19の外
部に引出した部分で回路基板への接続を行なう外部電極
とできる。
Therefore, the through-holes 20 and 21 are formed by connecting the same electrodes 11 and 12 to each other.
Both of the through holes 20 and 21 can be used as external electrodes for connecting to the circuit board at the portions that are drawn out of the laminated body 19.

【0013】上記のように、両スルーホール20と21
は、両電極11,12の引出し部となるが、両スルーホ
ール20,21を電極11,12の内部に形成すること
で最も短い距離で外部電極まで結線することができ、実
質的に引出し部がほとんどない状態になる。
As described above, both through holes 20 and 21 are provided.
Is a lead-out portion for both electrodes 11, 12, but by forming both through-holes 20, 21 inside the electrodes 11, 12, it is possible to connect to the external electrode at the shortest distance, and substantially the lead-out portion is formed. Is almost gone.

【0014】即ち、電極11,12の各部からスルーホ
ール20,21までの距離がl1 からl2 の範囲に抑え
ることができ、従って2つのスルーホール20と21は
電極11,12の中心にできるだけ近く形成できるよ
う、電極のない領域13,14を設けておくのが好まし
い。
That is, the distance from each part of the electrodes 11, 12 to the through holes 20, 21 can be suppressed within the range of l 1 to l 2 , so that the two through holes 20 and 21 are located at the centers of the electrodes 11, 12. It is preferable to provide the regions 13 and 14 without electrodes so that they can be formed as close as possible.

【0015】次に、図2はセラミックグリーンシート1
5a,16aに設ける電極11,12を正方形に形成
し、両電極11,12の異なった位置に電極のない領域
13,14を設け、このグリーンシート15a,16a
を図1と同様に積層することにより積層コンデンサを形
成する例を示している。
Next, FIG. 2 shows a ceramic green sheet 1.
Electrodes 11 and 12 provided on 5a and 16a are formed in a square shape, and electrode-free regions 13 and 14 are provided on different positions of both electrodes 11 and 12, respectively.
1 shows an example of forming a multilayer capacitor by stacking in the same manner as in FIG.

【0016】この例のように、電極11,12を正方形
にすると、スルーホールから電極の四隅までの距離が円
形の電極に比べて大きくなり、その分、特性は若干低下
するが、円形の電極に比べて同一面積をとる場合、積層
コンデンサの平面形状を小型化できるという利点があ
る。
When the electrodes 11 and 12 are square like this example, the distances from the through holes to the four corners of the electrodes are larger than those of the circular electrodes, and the characteristics are slightly degraded by that amount, but the circular electrodes are Compared with the above, when taking the same area, there is an advantage that the planar shape of the multilayer capacitor can be downsized.

【0017】なお、何れの例においても、図4に示すよ
うに、各電極11,12の接続と積層体19の外部への
引出しをビアホール22,23で行なうようにしてもよ
く、この場合積層体19の裏面に出た電極ランドには、
回路基板に実装しやすくするため、バンプ24,25を
形成してもよい。また、異なった位置に電極のない領域
を設けるシートは、三種類以上であってもよい。
In any of the examples, as shown in FIG. 4, the electrodes 11 and 12 may be connected to each other and the laminated body 19 may be drawn out through the via holes 22 and 23. In this case, the laminated bodies are laminated. In the electrode land on the back of the body 19,
The bumps 24 and 25 may be formed to facilitate mounting on the circuit board. Further, three or more types of sheets may be provided to provide regions having no electrodes at different positions.

【0018】この発明の積層コンデンサは上記のような
構成であり、図3及び図4に示したように、電極11,
12の接続と外部の引出しを行なうスルーホール20,
21又はビアホール22,23が、電極11,12の中
から取り出されているので引出し用の電極がほとんどな
い状態になり、従って引出し用の電極に起因するインダ
クタンス及び抵抗の発生が少なく、これによって共振周
波数が高く、かつ等価直列抵抗(ESR)が小さくな
る。
The multilayer capacitor of the present invention has the above-mentioned structure, and as shown in FIGS.
Through hole 20 for connecting 12 and drawing out
21 or the via holes 22 and 23 are taken out of the electrodes 11 and 12, so that there is almost no lead-out electrode, and accordingly, the generation of inductance and resistance due to the lead-out electrode is small, which causes resonance. The frequency is high and the equivalent series resistance (ESR) is low.

【0019】ちなみに、図7に示した従来の積層コンデ
ンサと図1及び図2で示したこの発明の積層コンデンサ
を用いてその特性を測定した結果を表1に示す。
By the way, Table 1 shows the results of measuring the characteristics of the conventional multilayer capacitor shown in FIG. 7 and the multilayer capacitor of the present invention shown in FIGS. 1 and 2.

【0020】[0020]

【表1】 [Table 1]

【0021】上記の測定結果から明らかなように、従来
の積層コンデンサに比べてこの発明の積層コンデンサ
は、共振周波数が大幅に高くなり、等価直列抵抗が小さ
くなっている。
As is clear from the above measurement results, the multilayer capacitor of the present invention has a significantly higher resonance frequency and a smaller equivalent series resistance than the conventional multilayer capacitor.

【0022】また、この発明の積層コンデンサにおいて
は、電極の形状によって特性が異なるため、特性とサイ
ズの両面から電極形状を選択すればよい。
Further, in the multilayer capacitor of the present invention, since the characteristics differ depending on the shape of the electrode, the electrode shape may be selected from both aspects of characteristics and size.

【0023】更に、共振周波数が高く等価直列抵抗が低
いという特徴を生かすため、図5に示すように、積層コ
ンデンサの表面に引出した電極の部分にコンデンサや抵
抗等の部品26を実装し、積層コンデンサをモジュール
等の基板として使用してもよい。
Further, in order to take advantage of the characteristic that the resonance frequency is high and the equivalent series resistance is low, as shown in FIG. 5, a component 26 such as a capacitor or a resistor is mounted on the electrode portion drawn out on the surface of the multilayer capacitor, and the multilayer capacitor is laminated. You may use a capacitor as a board | substrate of a module etc.

【0024】[0024]

【発明の効果】以上のように、この発明によると、積層
コンデンサにおける内部電極の接続と外部への引出しを
内部電極の中から行なったので、コンデンサを形成する
内部電極に外部電極が近くなり、引出し用の電極がほと
んどない状態になり、電気的共振周波数が高く、等価直
列抵抗が低くなるという効果がある。
As described above, according to the present invention, the connection of the internal electrodes in the multilayer capacitor and the extraction to the outside are performed from the inside of the internal electrodes, so that the external electrodes are close to the internal electrodes forming the capacitor, There is an effect that there is almost no extraction electrode, the electric resonance frequency is high, and the equivalent series resistance is low.

【図面の簡単な説明】[Brief description of drawings]

【図1】積層コンデンサを構成するセラミックグリーン
シートと電極のパターンを示す分解斜視図。
FIG. 1 is an exploded perspective view showing patterns of a ceramic green sheet and electrodes that form a multilayer capacitor.

【図2】同上の電極パターンが異なる例を示す分解斜視
図。
FIG. 2 is an exploded perspective view showing an example in which the same electrode pattern is different.

【図3】積層コンデンサの縦断面図。FIG. 3 is a vertical sectional view of a multilayer capacitor.

【図4】ビアホールを用いた積層コンデンサの縦断面
図。
FIG. 4 is a vertical sectional view of a multilayer capacitor using a via hole.

【図5】積層コンデンサをモジュール基板として用いた
縦断面図。
FIG. 5 is a vertical cross-sectional view using a multilayer capacitor as a module substrate.

【図6】従来の積層コンデンサを示す分解斜視図。FIG. 6 is an exploded perspective view showing a conventional multilayer capacitor.

【図7】従来の積層コンデンサを示す縦断面図。FIG. 7 is a vertical sectional view showing a conventional multilayer capacitor.

【図8】同上の等価回路図。FIG. 8 is an equivalent circuit diagram of the above.

【符号の説明】[Explanation of symbols]

11,12 電極 13,14 電極のない領域 15,15a,16,16a セラミックグリーンシー
ト 17,18 セラミックグリーンシート 19 積層体 20,21 スルーホール 22,23 ビアホール
11,12 Electrodes 13,14 Areas without electrodes 15,15a, 16,16a Ceramic green sheet 17,18 Ceramic green sheet 19 Laminated body 20,21 Through hole 22,23 Via hole

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 表面に設けた電極の内側に電極のない領
域を異なった位置に形成した少なくとも二種類の絶縁シ
ートを積み重ねて積層体を形成し、前記積層体に電極の
ない領域の部分を貫通するよう設けたスルーホールもし
くはビアホールの引出し電極で同一電極を互に接続して
積層体の外部に引出したことを特徴とする積層コンデン
サ。
1. A laminated body is formed by stacking at least two kinds of insulating sheets each having an electrodeless region formed at different positions inside an electrode provided on a surface thereof to form a laminated body. A multilayer capacitor, wherein the same electrodes are connected to each other by lead-out electrodes of through-holes or via-holes provided so as to penetrate and are led out to the outside of the laminated body.
JP3418792A 1992-01-24 1992-01-24 Multilayer capacitor Pending JPH05205966A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3418792A JPH05205966A (en) 1992-01-24 1992-01-24 Multilayer capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3418792A JPH05205966A (en) 1992-01-24 1992-01-24 Multilayer capacitor

Publications (1)

Publication Number Publication Date
JPH05205966A true JPH05205966A (en) 1993-08-13

Family

ID=12407196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3418792A Pending JPH05205966A (en) 1992-01-24 1992-01-24 Multilayer capacitor

Country Status (1)

Country Link
JP (1) JPH05205966A (en)

Cited By (19)

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US6327134B1 (en) 1999-10-18 2001-12-04 Murata Manufacturing Co., Ltd. Multi-layer capacitor, wiring board, and high-frequency circuit
US6344961B1 (en) 1999-11-19 2002-02-05 Murata Manufacturing Co., Ltd Multi-layer capacitator, wiring substrate, decoupling circuit, and high-frequency circuit
US6351369B1 (en) 1999-11-19 2002-02-26 Murata Manufacturing Co., Ltd Multi-layer capacitor, wiring substrate, decoupling circuit, and high-frequency circuit
US6370010B1 (en) 1999-10-18 2002-04-09 Murata Manufacturing Co., Ltd Multi-layer capacitor, wiring board, and high-frequency circuit
US6370011B1 (en) 1997-11-14 2002-04-09 Murata Manufacturing Co., Ltd Multilayer capacitor
JP2003100549A (en) * 2002-09-09 2003-04-04 Murata Mfg Co Ltd Chip capacitor and its manufacturing method
US6549395B1 (en) 1997-11-14 2003-04-15 Murata Manufacturing Co., Ltd Multilayer capacitor
US6556420B1 (en) 1999-12-27 2003-04-29 Murata Manufacturing Co., Ltd. Wiring connection structure of laminated capacitor and decoupling capacitor, and wiring board
US6756628B2 (en) 2001-05-30 2004-06-29 Matsushita Electric Industrial Co., Ltd. Capacitor sheet with built in capacitors
JP2006222442A (en) * 2002-10-30 2006-08-24 Kyocera Corp Capacitor and wiring board
WO2006108397A1 (en) * 2005-04-11 2006-10-19 Epcos Ag Electric multilayer component and method for the production of a multilayer component
JP2007103964A (en) * 2006-12-11 2007-04-19 Kyocera Corp Multilayer wiring board with built-in capacitor element and electronic device
KR100739491B1 (en) * 2005-10-21 2007-07-19 한국과학기술연구원 Igh dielectric capacitor and fabricating method thereof
JP2012191203A (en) * 2011-03-04 2012-10-04 General Electric Co <Ge> Multi-plate board embedded capacitor and methods for fabricating the same
US9001486B2 (en) 2005-03-01 2015-04-07 X2Y Attenuators, Llc Internally overlapped conditioners
US9019679B2 (en) 1997-04-08 2015-04-28 X2Y Attenuators, Llc Arrangement for energy conditioning
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
JP2017037901A (en) * 2015-08-07 2017-02-16 株式会社村田製作所 Multilayer capacitor, and wiring board

Cited By (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9373592B2 (en) 1997-04-08 2016-06-21 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
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