JPH05183884A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To prevent the loss of resolution and the deviation of an image due to erroneous movement detection when a scanning line conversion processing is executed for television-cinema video signal formed in 2-3 pull-down system, for example. CONSTITUTION:The scanning line conversion is made of an input video signal Vin in order by a scanning line conversion means consisting of field memories 8 and 9 and a switch circuit 10. A difference signal SDF between one frame to be formed by field memories 3 and 4 a subtractor 2, is supplied to a detection circuit 5 for the television-cinema video signal in the 2-3 pull-down system. When the video signal Vin is the television-cinema video signal, a signal STC is supplied to a control signal generation circuit 7 by the detection circuit 5. At this time, the video signal converted into a scanning line in order which is outputted by a switch circuit 11 is supplied to a scanning line conversion circuit 12 via the switch circuit 11, and the scanning line conversion is made by means of a still picture processing without performing movement detection at all times. When the video signal Vin is the television-cinema video signal, since the movement detection is not conducted, the loss of resolution and the deviation of the image due to the erroneous movement detection can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is more than a motion picture film.
The present invention relates to a video signal processing circuit suitable for application to processing using a plurality of scanning line signals for a telecine video signal formed by a -3 pulldown method.

[0002]

2. Description of the Related Art In the current television system (NTSC system), one frame is divided into two fields and transmitted by interlaced scanning, and the number of images is 30 frames (60 fields) per second. On the other hand, 16mm and 35
A standard motion picture film such as mm has 24 frames per second. As a method of forming a video signal (telecine video signal) from this motion picture film, the 2-3 pull-down method is conventionally known.

In the 2-3 pull-down system, the nth film is frame-fed every 3 fields (3/60 seconds), and the n + 1th film is frame-fed every 2 fields (2/60 seconds). , 2 frames of film and 5 fields of a video signal are associated with each other. Therefore, the telecine video signal formed by the 2-3 pull-down method is an alternating repetition of the video signal of 3 fields and the video signal of 2 fields formed from the same film.

For example, as shown in FIG. Fields 1 to 3 are formed, and No. 2 from the second frame. 4 and 5 fields are formed, and from the third frame, N
o. 6-8 fields are formed, and from the 4th frame, N
o. 9 and 10 fields are formed. Hereinafter, this is repeated.

A so-called high-definition system has been proposed as a high-definition television system. In the high-definition system, the number of scanning lines is 1125 lines / frame, the field frequency is 60 Hz, the interlace ratio is 2: 1, and the aspect ratio is 16: 9. On the other hand, in the NTSC system, the number of scanning lines is 525 lines / frame, the field frequency is 60 Hz, the interlace ratio is 2: 1, and the aspect ratio is 4: 3.

[0006] Here, there may be a case where a high-definition program is used in the current television broadcasting (for example, NTSC system). Therefore, conventionally, for example, system conversion from the high-definition system to the NTSC system has been proposed. An example of scanning line conversion (down conversion) in this system conversion will be described.

When the image is a still image, both of the video signals of the even-odd field of the high definition system of 562.5 lines / field as shown in FIG. 12A are used, and 1125 lines / frame as shown in FIG. A scanning type video signal is formed. Weighting processing is performed on the video signal of 1125 lines / frame to obtain 525 as shown in FIG.
A video signal of a book / frame progressive scanning method is formed.
Then, from the video signal of 525 lines / frame
The video signal of the even-odd field of the NTSC system of 262.5 lines / field as shown in FIG. in this case,
The video signal of the even-odd field of the NTSC system is formed by using both the video signals of the odd-even field of the high-definition system, and a high-resolution video signal is obtained.

On the other hand, when it is a moving image, it is shown in FIG.
By weighting the odd-even field video signals of the 562.5 lines / field high-definition video signal as shown in FIG.
An image signal of an odd-even field of the NTSC system of 2.5 lines / field is formed. In this case, each of the high-definition odd-even field video signals is used for NT.
A video signal of an even-odd field of the SC system is formed, and image shift is prevented.

[0009]

By the way, as described above, it is necessary to detect the motion of an image in order to make a difference in the down conversion process depending on whether the image is a still image or a moving image. When erroneous motion detection is performed, there is an inconvenience that moving image processing is performed on a still image video signal to deteriorate resolution, or still image processing is performed on a moving image video signal to cause image shift. This was the same even when the high-definition video signal was the telecine video signal formed by the 2-3 pull-down system.

Therefore, according to the present invention, when the scanning line conversion processing is performed on the telecine video signal formed by, for example, the 2-3 pull-down method, it is possible to prevent the deterioration of the image quality such as the resolution reduction and the image shift due to the false motion detection. is there.

[0011]

SUMMARY OF THE INVENTION According to the present invention, a signal discriminating means for discriminating whether or not an input video signal is a telecine video signal formed by a 2-3 pulldown system from a motion picture film, and the input video signal are sequentially supplied. A progressive scan conversion means for converting into a scanning system and a signal processing means for performing processing using a plurality of scanning line signals are provided, and when the signal discrimination means discriminates the telecine video signal, the input video signals are sequentially transmitted. The signal is supplied to the signal processing means after being converted into the progressive scanning method by the scanning conversion means.

[0012]

In the above construction, when the input video signal is a telecine video signal formed by the 2-3 pull-down system, the input video signal is supplied as a progressive scanning system video signal to the signal processing means. Therefore, for example, when the scanning processing is performed by the signal processing means, the same processing as that conventionally performed for a still image can be performed without detecting the movement of the image, which may cause an erroneous movement detection. It is possible to avoid deterioration of image quality such as resolution deterioration and image shift.

In this case, if the progressive scan conversion means forms the video signal of the progressive scan system from the video signal of the odd-even field formed from the same frame of the motion picture film, the scan line conversion is performed even for the moving picture. No image shift occurs due to the processing.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. This example is an example of scanning line conversion (down conversion) from the high definition system to the NTSC system.

In FIG. 1, an input terminal 1 is supplied with a high definition video signal Vin. The video signal Vin is directly supplied to the subtractor 2 and is also supplied to the subtractor 2 via the series circuit of the field memories 3 and 4 forming a delay circuit (delay time of one frame period). The one-frame difference signal SDF output from the subtracter 2 is supplied to the 2-3 pull-down type telecine video signal detection circuit 5.
A frame memory may be used instead of the field memories 3 and 4.

The video signal V supplied to the input terminal 1
in is supplied to the timing generation circuit 6. The timing generation circuit 6 is configured to have a sync separation circuit, a PLL circuit, etc., and based on the sync signal separated from the video signal Vin, the clock CK, the line sync signal LO / E corresponding to the odd / even line, and the field pulse VP. , Frame pulse FP
Is formed. The field pulse VP is supplied from the timing generation circuit 6 to the detection circuit 5 described above.

FIG. 2 shows a specific configuration of the detection circuit 5 for the telecine video signal. In the figure, the one-frame difference signal SDF from the subtractor 2 is supplied to the integrating circuit 22 and integrated after the absolute value is taken by the absolute value circuit 21. The integrated value in the integrating circuit 22 is reset at the rising edge of the field pulse VP.

The integrated output from the integrating circuit 22 is supplied to the comparator 23 and compared with a predetermined threshold value Vth. The comparison output of the comparator 23 is “0” when the integrated output is smaller than the threshold Vth, and is “1” when the integrated output is equal to or larger than the threshold Vth.

The comparison output from the comparator 23 is supplied to a series circuit of registers (D flip-flops) 24-28. The field pulse VP is supplied to the registers 24-28 as a clock. Register 24-28
Is output to the OR gate 29.

The output signal of the OR gate 29, the signal obtained by inverting the output signal of the register 28 by the inverter 30, and the output signal of the registers 24 to 27 are the AND gate 31.
And the output signal of the AND gate 31 is used as the output signal of the detection circuit 5.

The telecine video signal formed by the 2-3 pull-down system as described above is No. 1 and No. No. 3 field, no. 6 and No. The eight fields are the same (see FIG. 11). Therefore, input terminal 1
No. when the video signal Vin supplied to No. 2 is a telecine video signal formed by the 2-3 pull-down system. 1,6
Input signal of AND gate 31 is all "1" in the field
And the output signal of the AND gate 31 becomes "1" (illustrated in FIG. 3C). FIG. 3A shows the video signal Vin.

Returning to FIG. 1, the output signal of the detection circuit 5 is supplied to the control signal generation circuit 7 as the telecine cut signal STC. The control signal generating circuit 7 is supplied with the clock CK, the line synchronizing signal LO / E, the field pulse VP, and the frame pulse FP from the timing generating circuit 6.

The video signal V supplied to the input terminal 1
in is supplied to the field memories 8 and 9. The write control signals W1 and W2 and the read control signals R1 and R2 are supplied from the control signal generation circuit 7 to these memories 8 and 9.

The control signals W1, W2, R1 and R2 are formed by using a field sync signal F0 / E or the like indicating an odd / even field.

First, the generator of the field synchronizing signal F0 / E in the control signal generating circuit 7 will be described with reference to FIG.

In the figure, the frame pulse FP (see FIG.
(Shown in B) is supplied to a predetermined number of shift registers 42 via an inverter 41. A clock CK (illustrated in FIG. A) is supplied as the shift clock of the shift register 42. The output signal of the shift register 42 is the register (D
It is supplied to a series circuit of flip-flops 43 and 44.

The field pulse VP (shown in FIG. 6C) is supplied to the register 43 as a clock via the inverter 45 and directly to the register 44 as a clock.

In the above configuration, the shift register 42
Output signal is a signal in which the frame pulse FP is inverted and delayed by a predetermined time (shown in FIG. 6D), and the output signal of the register 43 becomes as shown in FIG. Then, the register 44 outputs a field synchronization signal F0 / E which becomes "0" in the odd field and "1" in the even field (shown in FIGS. 6F and 3B).

Next, the generators of the write control signals W1 and W2 in the control signal generation circuit 7 will be described with reference to FIG.

In the figure, a clock CK (shown in FIG. 8A) is supplied to AND gates 61 and 62. Further, the field synchronization signal F0 / E (shown in FIG. 9B) is directly supplied to the AND gate 61 and also to the AND gate 62 via the inverter 63. Further, the telecine cut signal STC (shown in FIG. 4D) is supplied to the AND gates 61 and 62 via the inverter 64.

In the above structure, the output signal of the inverter 63 is a signal obtained by inverting the field sync signal F0 / E (shown in FIG. 8C), and the output signal of the inverter 64 is a signal obtained by inverting the telecine cut signal STC. (Fig. E
(Illustrated in).

Therefore, from the AND gate 61, 2-
No. of the above-mentioned 10-field cycle (hereinafter referred to as "telecine cycle") of the telecine video signal formed by the 3 pulldown system. 3, No. 5, No. 7, No. The clock CK is gated in the field of 9 and is output as the write control signal W1 (shown in FIG. 4F). Further, from the AND gate 62, the No. of the telecine cycle is displayed. 2, No.
4, No. 8, No. Clock CK in 10 fields
Are gated and output as a write control signal W2 (shown in FIG. 7G).

The telecine cycle No. 1 in which the telecine cut signal STC becomes "1". 1, No. In the field of No. 6, neither of the control signals W1 and W2 is output (FIG. 8).
(Dashed lines are shown in F and G).

Next, the generator of the read control signals R1 and R2 in the control signal generation circuit 7 will be described with reference to FIG.

In the figure, a clock CK (illustrated in FIG. 10A and field synchronization signal F0 / E in FIG. 10B) is supplied to an AND gate 71. Further, the telecine cut signal STC (shown in FIG. 6C) is supplied to the register (D flip-flop) 72. The field pulse VP (shown in FIG. 4D) is supplied to the register 72 as a clock. The output signal of the register 72 is inverted and supplied to the AND gate 71.

The output signal of the AND gate 71 is supplied to the AND gates 74 and 75. Also, the line sync signal LO /
E is directly supplied to the AND gate 74 and is also supplied to the AND gate 75 via the inverter 76. The line synchronization signal LO / E is a signal which becomes "1" in the odd field and "0" in the even field, which is not described above.

In the above structure, the inverted signal of the output signal of the register 72 is a signal in which the telecine cut signal STC is inverted and delayed by one field period (shown in FIG. 10E). From the AND gate 71, the No. of the telecine cycle is displayed. 1, No. 3-6, No. The clock CK is gated and output in the fields of 8 to 10 (shown in FIG. 4F). Therefore, AND gates 74 and 75
From the No. of the telecine cycle. 1, No. 3-
6, No. The clock CK is gated by the odd and even lines of the fields 8 to 10, and the read control signal R1
And R2.

Returning to FIG. 1, since the control signal generation circuit 7 outputs the write control signals W1 and W2 as described above, the memory 8 receives the No. of the telecine cycle. 3, No.
5, No. 7, No. The video signals of the field of No. 9 are sequentially written (shown in FIG. 3D), and the memory 9 has the No. 2, No. 4, No. 8, No. The video signals of the ten fields are sequentially written (shown in FIG. F).

Since the control signal generating circuit 7 outputs the read control signals R1 and R2 as described above,
From the memory 8, the No. of the telecine cycle is displayed. No. in odd lines of fields 3 and 4 The video signal of the 3rd field is
No. No. in the odd lines of fields 5 and 6 The video signal of the field of No. 5 is No. No. in the odd lines of the fields 8 and 9. The video signal of the field of No. 7 is No.
No. in the odd lines of the fields of 10 and 1. The video signal of the field of No. 9 is read (illustrated in FIGS. 3E and 4A), and the No. of the telecine cycle is read from the memory 9. No. in even lines of fields 3 and 4. The video signal of the second field is No. No. in even lines of fields 5 and 6
The video signal of the field of No. 4 is No. No. in even lines of fields 8 and 9. The video signal of 8 fields
No. No. in the even lines of the fields of 10 and 1. 10
The video signal of the field is read out (see FIGS. 3G and 4).
(Shown in B). The numbers attached in FIG. 4 indicate line numbers.

The read signals of the memories 8 and 9 are supplied to the switch circuit 10. A switching control signal (shown in FIG. 4C) is supplied from the control signal generation circuit 7 to the switch circuit 10, and the memory 8 side is selected in the odd line in which the memory 8 is in the read state, while the memory 9 is in the read state. In the line, the memory 9 side is selected.

Therefore, from the switch circuit 10, the telecine cycle No. In fields 3 and 4, No. 3 and No. The video signals of each line of the field of No. 2 are alternately displayed. In the fields of 5 and 6, No. 5 and N
o. The video signals of each line in the 4th field alternate,
o. In the fields 8 and 9, No. 8 and No. The video signal of each line of the field of No. 7 alternates with No. 1
In the fields 0 and 1, No. 10 and No. The video signals of each line of the 9 fields are alternately read (illustrated in FIGS. 3H and 4D).

That is, the switch circuit 10 outputs video signals which are sequentially scanned. In this case, the video signal for one frame which is sequentially scanned is output in two field periods.

The progressively scanned video signal output from the switch circuit 10 is supplied to the switch circuit 11. Further, the switch circuit 11 is supplied with the video signal Vin output from the memory 4 delayed by one frame period. A switching control signal is supplied from the control signal generation circuit 7 to the switch circuit 11. The video signal Vin supplied to the input terminal 1 is a telecine video signal formed by the 2-3 pull-down method, and the control signal generation circuit 7 is supplied from the detection circuit 5.
When the telecine cut signal STC is supplied to the switch circuit 11, the switch circuit 11 selects the sequentially scanned video signal output from the switch circuit 10, and in other cases, the video signal output from the memory 4 is selected. ..

The video signal output from the switch circuit 11 is supplied to a scanning line conversion circuit 12 which performs scanning line conversion (down conversion) from the high definition system to the NTSC system. The scanning line conversion circuit 12 includes a control signal generation circuit 7
A control signal is supplied by the control signal to control its operation.

That is, when the video signal Vin supplied to the input terminal 1 is a telecine video signal formed by the 2-3 pull-down method and the detection circuit 5 supplies the telecine cut signal STC to the control signal generation circuit 7. And the video signal V
When in is a normal video signal, the scanning line conversion circuit 1
The processing operation in 2 is made different.

When the video signal Vin is a normal video signal, the motion of the image is detected by the motion detection circuit (not shown) incorporated in the scanning line conversion circuit 12 as described above,
Depending on the detection result, still image processing (see FIG. 12) or moving image processing (see FIG. 13) is performed.

On the other hand, when the video signal Vin is a telecine video signal formed by the 2-3 pull-down system, it is supplied to the scanning line conversion circuit 12 as a video signal which has already been sequentially scanned (B in FIG. 12). Equivalent to the state). Therefore, the scanning line conversion circuit 12 always performs the still image processing (see FIG. 12) without detecting the movement of the image.

The scanning line conversion circuit 12 outputs a video signal Vout of the interlaced scanning system whose scanning line is converted from the high-definition system to the NTSC system, and the video signal Vout is led to the output terminal 13.

As described above, in this example, when the video signal Vin supplied to the input terminal 1 is a telecine video signal formed by the 2-3 pulldown system, the switch circuit 1
The sequentially scanned video signal output from 0 is supplied to the scanning line conversion circuit 12, and the scanning line conversion circuit 12 always performs still image processing without detecting the movement of the image.
Therefore, the image quality deterioration such as the resolution reduction and the image shift does not occur due to the incorrect motion detection.

In this case, since the progressive scan conversion means composed of the memories 8 and 9 and the switch circuit 10 uses the odd-even field video signal of the movie film to form the progressive scan video signal. Even in the case of a moving image, the image shift does not occur due to the scanning line conversion processing.

Although the signal processing means is the scanning line conversion circuit 12 in the above embodiment, the signal processing means is a motion vector detection circuit or a discrete cosine conversion circuit (DCT conversion circuit) in the present invention. The same can be applied to other circuits that perform processing using a plurality of scanning line signals (processing within a field, within a frame, between frames, etc.). For example, the motion vector detection circuit can detect the motion vector more finely, and the DCT conversion circuit can reduce the deterioration of the vertical resolution.

Further, in the above embodiment, the detection circuit 5
Is configured by using five registers 24 to 28. However, by increasing the number of stages of the registers, it is possible to reduce the error that the "1" signal is output from the AND gate 31 in the normal video signal. You can

[0053]

According to the present invention, the input video signal is 2-
In the case of a telecine video signal formed by the 3 pull-down system, the input video signal is converted into a video signal of the progressive scanning system and supplied to the signal processing means, so that, for example, scanning line conversion processing is performed by the signal processing means. Can perform the same processing as that conventionally performed on a still image without detecting the motion of the image, and can avoid the image quality deterioration such as the resolution reduction and the image shift due to the incorrect motion detection.

In this case, in the progressive scan conversion means, the video signal of the progressive scan system is formed from the video signal of the odd-even field formed from the same frame of the motion picture film, so that even a moving image is scanned by the scan line conversion process. There is no deviation.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a block diagram showing a detection circuit for a telecine video signal.

FIG. 3 is a timing chart showing the operation of the embodiment.

FIG. 4 is a timing chart showing the operation of the embodiment.

FIG. 5 is a connection diagram showing a generator of a field synchronization signal.

FIG. 6 is a timing chart showing the operation of the field synchronization signal generator.

FIG. 7 is a connection diagram showing a generator of a write control signal.

FIG. 8 is a timing chart showing the operation of the write control signal generator.

FIG. 9 is a connection diagram showing a generator of a read control signal.

FIG. 10 is a timing chart showing the operation of the read control signal generator.

FIG. 11 is a diagram for explaining a 2-3 pulldown method.

FIG. 12 is a diagram for explaining down conversion (still image processing).

FIG. 13 is a diagram for explaining down conversion (moving image processing).

[Explanation of symbols]

 1 Input Terminal 2 Subtractor 3, 4, 8, 9 Field Memory 5 Telecine Video Signal Detection Circuit 6 Timing Generation Circuit 7 Control Signal Generation Circuit 10, 11 Switch Circuit 12 Scan Line Conversion Circuit 13 Output Terminal

Claims (2)

[Claims] 1. The input video signal is 2-3 from a movie film.
A signal discriminating means for discriminating whether or not it is a telecine video signal formed by a pull-down system, a progressive scan converting means for converting the input video signal into a progressive scanning system, and a process using a plurality of scanning line signals. Signal processing means, and when the signal determining means determines that the telecine image signal is the telecine image signal, the input image signal is converted to a progressive scanning method by the progressive scan converting means and then supplied to the signal processing means. Video signal processing circuit characterized by. 2. The video signal according to claim 1, wherein the progressive scan conversion means forms a progressive scan video signal from a video signal of an odd-even field formed from the same frame of the motion picture film. Processing circuit.