JPH05175424A - Semiconductor memory device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to achieve high packaging density of elements by forming the gate electrode of a MOS-type field-effect transistor by the self- aligning mode in a trench-shaped groove. CONSTITUTION:The memory units of a MOS-type field-effect transistor are separated and insulated with a separating and insulating film 18 in the direction of a word line (direction in parallel with a trench-shaped groove). Therefore, in this vertical memory unit, the period in the direction of the word line becomes 2L (active L + separating region L) when a design rule is L. In the direction of a bit line, a gate electrode 24 is formed in a self-aligning mode in the trench. Therefore, the period becomes twice = 2L of the period of the trench. After all, the area of the memory unit becomes 2LX2L=4L<2>, and mask aligning margin is not required. Thus, the high packaging density of the elements can be achieved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including one capacitor and one MOS type field effect transistor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art As the integration of semiconductor memory progresses,
DRAM (Daynamic Rando)
A cell structure has been proposed in which the m Access Memori) cell is three-dimensionally typified by so-called stack cells and trenches.

An example of this trench type memory cell is shown in FIGS. 5 and 6 are IEDM '85 Tech,
Dig. PP714-714.
FIG. 5 is a plan view of the trench type memory cell, and FIG. 6 is a sectional view. In both FIGS. 5 and 6, the high concentration P
A P type epitaxial layer 52 is formed on a type silicon substrate 51, and a charge storage capacitor insulating film 54 is formed inside the trench 53 formed in the high concentration P type silicon substrate 51. High-concentration N-type polycrystalline silicon electrodes 55 are formed so as to face each other.

The upper portion of the high-concentration N-type polycrystalline silicon electrode 55 is directly connected to the P-type epitaxial layer 52 and serves as a source diffusion layer 56. Above the P-type epitaxial layer 52, there is a drain diffusion layer separated by an isolation insulating film 59, which also has a function as a bit line 58a.

Above the high-concentration P-type silicon substrate 51,
The above-mentioned polycrystalline silicon electrode 55 is formed so as to cover the inside of the trench, and functions as a gate electrode of the MOSFET formed inside the trench 53 and further as a word line 60 for selecting a cell. An intermediate insulating film, a wiring electrode, etc. are formed above. The trench type memory cell is configured as described above. Incidentally, 57 is a channel region.

[0006]

However, the above-mentioned conventional trench type memory cell has a problem that it is difficult to achieve a high degree of integration, that is, as shown in the plan view of FIG. Type memory cells,
Assuming that the design rule (minimum processing size) in which the isolation insulating film 59 needs to be formed in order to isolate the bit line 58a between cells is L, the isolation insulating film 5 is formed in the X direction (see FIG. 5).
9 is necessary because the alignment margin D1 between the trench 53 and
(2L + 2D1).

Further, since the alignment margin D2 between the trench 53 and the word line 60 is required for the period in the Y direction, (2L + 2)
D2). Both of the alignment margins D1 and D2 are dimensions necessary for the alignment margin in processing, which hinders the integration of the device by this amount, and the portions to be the gate electrodes and contact holes are self-aligned. Since it is not formed on the substrate, it hinders simplification of the manufacturing process.

The invention described in claim 1 is to provide a semiconductor device which solves the problem that the integration of elements is hindered due to the need for alignment margin among the problems of the prior art.

The invention according to claim 2 provides a semiconductor memory device which solves the problem that the prior art has, that a mask alignment margin is required.

Further, in the invention described in claim 3, among the problems that the above-mentioned conventional technique has, a problem that the device integration is hindered because a margin for alignment is required and the manufacturing process is simplified. It is intended to provide a method for manufacturing a semiconductor device, which solves the problem of hindrance.

[0011]

According to a first aspect of the present invention, in order to solve the above-mentioned problems, in a semiconductor device, a capacitor and a trench which are respectively separated on a side surface of a semiconductor region formed in a trench-like groove portion. A memory cell including a MOS field effect transistor in which a gate electrode is formed in a self-aligned manner in the groove portion is provided.

According to another aspect of the semiconductor device of the present invention, the semiconductor region and the insulating film on the side surface of the convex portion extending between the trench-shaped trenches extending inside the trench-shaped trenches and serving as an element of the MOS field effect transistor are formed. A capacitor is formed by a conductive electrode formed inside the trench-shaped groove.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor memory device, the first insulating film having diffusion resistance is formed on the inner side surface of the first trench-shaped groove portion, and then the first insulating film is formed.
Forming a second trench-shaped groove portion in a self-aligned manner in the trench-shaped groove portion and selectively forming an element isolation region on the surface thereof; and forming a capacitor region inside the second trench-shaped groove portion. A step of contacting one of the electrodes of the capacitor region with a semiconductor region formed on the surface of the semiconductor substrate in contact with the lower part of the first insulating film, and the side surface of the first trench-shaped groove after removing the first insulating film and the insulating film And a step of forming a gate electrode by embedding it so as to be in contact with each other through.

[0014]

According to the first aspect of the invention, the capacitor is formed inside the trench-shaped groove, the gate insulating film is formed on the side surface of the trench-shaped groove, and the capacitor and the MOS field effect transistor form a vertical memory cell. In addition, the side portion of the trench-shaped groove portion becomes the channel region, and it is not necessary to consider the mask alignment margin in the channel region shape.

According to the second aspect of the present invention, since the semiconductor region forming the capacitor of the trench-shaped groove portion is also used as the semiconductor region on the side surface of the convex portion which is an element of the MOS field effect transistor, it is used as a transfer transistor. Operate.

In a third aspect of the present invention, the second trench-shaped groove portion is formed in the first trench-shaped groove portion in a self-aligned manner, and the element isolation region is selectively formed on the surface of the second trench-shaped groove portion. By forming a capacitor in the trench-shaped groove and connecting one electrode of the capacitor to the semiconductor region formed in the first trench-shaped groove, one electrode of the capacitor and the semiconductor region of the MOS field effect transistor are shared. A vertical memory cell is formed by a capacitor and a MOS field effect transistor to enable device integration, and a gate electrode and a contact hole portion are formed in a self-aligned manner to eliminate the need for pattern formation.

[0017]

Embodiments of the semiconductor device of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view of the embodiment, and FIG. 2 is a sectional view thereof. 1 and 2, a trench-shaped groove is formed on the surface of the P-type silicon substrate 11, and a capacitor diffusion layer 19 is formed on the inner surface below the trench-shaped groove. The plate electrode 22 is formed via the capacitor diffusion layer 19 and the capacitor insulating film 21, and thus the plate electrode 22, the capacitor diffusion layer 19, and the capacitor insulating film 21 are formed.
Together with this, a charge storage capacitor is formed as a charge storage portion.

A gate electrode 24 is formed above the trench-like groove with a first silicon oxide film 13 as a gate insulating film interposed therebetween.
Is formed, the upper end of the capacitor diffusion layer 19 and the drain diffusion layer 20 form a MOSFET, and the MOSFET operates as a transfer transistor.

Further, the gate electrode 2 as a selected word line
4 and the wiring electrode 26 serving as a bit line formed on the drain diffusion layer 20 form a one-capacitor, one-transistor type memory unit.

In this case, the MOSFET T _r1 has the active regions P ₁ and P ₂ as channel regions, and
T _r2 uses the active regions P ₂ and P ₃ as channel regions. Thus, the MOSFETs T _r1 and T _r2 are vertical transistors that share the drain diffusion layer 20 and the gate electrode 24.

Each memory unit is isolated and insulated by an isolation insulating film 18 in the word line direction (direction parallel to the trench-like groove). Therefore, in such a vertical memory unit, when the design rule is L, the period in the word line direction is 2L (of active L + isolation region L).
Becomes Since the gate electrode 24 is formed in the trench in the bit line direction in a self-aligned manner, the period of the trench is twice the period = 2L. After all, the area of the memory unit is 2L × 2
L = 4L ² . Mask alignment margin D compared to the past
1, 1 and D2 are not necessary, so that the device can be highly integrated.

Next, an embodiment of a method of manufacturing the semiconductor memory device having the above structure will be described. 3 (a) to 3 (c)
FIG. 4A is a process sectional view of the first stage, and FIG.
(C) is a process sectional view of the second stage. These Figure 3
In FIGS. 3A to 3C and FIGS. 4A to 4C, the same parts as those in FIGS. 1 and 2 are denoted by the same reference numerals.

First, as shown in FIG. 3A, the P-type silicon substrate 11 extends in the bit line direction (direction of the wiring electrode 26 shown in FIG. 2) on the surface of the P-type silicon substrate 11, and has a width of 1 μm and a depth of 0.6 μ, for example.
m first trench-shaped grooves 12 are formed.

Next, 200 Å-thick first silicon oxide films 13 and 1 are formed on the entire surface of the substrate including the first trench-shaped grooves 12.
After the first silicon nitride film 14 having a thickness of 000Å is sequentially formed, the first silicon nitride film 14 is etched by directional etching and left only on the side surface of the first trench-shaped groove 12.

Next, as shown in FIG. 3B, the side portions of the first trench-like grooves 12 are etched by using the first silicon oxide film 13 and the first silicon nitride film 14 as masks. The second trench-shaped groove 15 is further formed to have a thickness of about 3 μm. Silicon substrate 1 including this second trench-shaped groove 15
A second silicon oxide film 16 and a second silicon nitride film 17 are successively formed on the surface of No. 1 in the order of 500Å and 1000Å, respectively.

Thereafter, by photolithography, as shown in FIG. 1C, the second silicon nitride film 17, the second silicon oxide film 16, the first silicon nitride film 14, and the first silicon nitride film 14 other than the element isolation region are formed. The first silicon oxide film 13 is sequentially and selectively etched. Then, thermal oxidation is performed for 60 minutes in a wet oxygen atmosphere at 950 ° C. to form a 4000 Å-thick isolation insulating film (field oxide film) 18.

In this case, if necessary, the isolation insulating film 18
Before forming Pd, phosphorus (P) may be obliquely ion-implanted at 40 keV and about 3 × 10 ¹³ cm ^-2 to form a channel stop layer. After forming the isolation insulating film 18, the second silicon nitride film 1 is formed.
7. The second silicon oxide film 16 is sequentially removed by etching.

Next, the second process step shown in FIGS. 4A to 4C is entered. First, as shown in FIG. 4A, arsenic (As) is deposited on the entire surface of the silicon substrate 11. Diagonal ion implantation is performed with an acceleration energy of 60 keV and a dose of 1 × 10 ¹⁶ cm ^-2 . At this time, since the first silicon nitride film 14 acts as a mask, only the upper surface of the convex portion sandwiched between the lower inner wall of the second trench-shaped groove 15 and the upper portion of the first trench-shaped groove 12 is n-type. An arsenic diffusion layer is formed. The n-type arsenic diffusion layer below the second trench-shaped groove 15 becomes the capacitor diffusion layer 19, and the diffusion layer on the upper surface of the first trench-shaped groove 12 becomes the drain diffusion layer 20.

Next, a silicon oxide film having a film thickness of 80 Å is formed to form a capacitor insulating film 21. Further, a doped polysilicon film is formed on the entire surface of the silicon substrate 11 by 0.7 to 1.2 μm.
Then, the second trench-shaped groove 15 is etched to an inner depth of 0.8 μm by the etch back method to form the plate electrode 22.

Thereafter, as shown in FIG. 4B, a first interlayer insulating film 23 of 0.2 μm is selectively formed in the second trench-shaped groove. Then, after removing the first silicon nitride film 14 by etching, a doped polysilicon film having a thickness of 0.5 μm is selectively formed in the first trench 12 to form the gate electrode 24. At this time, since the gate electrode 24 is embedded in the first trench-shaped groove 12 in a self-aligned manner,
There is no need for photolithography. In addition, the gate electrode 2
The side surface of the active region corresponding to 4 is the channel length.

Further, as shown in FIG. 4C, a second interlayer insulating film 25 having a thickness of 0.2 μm is selectively formed in the first trench-shaped groove, and is sandwiched between the first trench-shaped grooves 12. After selectively removing the first silicon oxide film 13 on the upper surface of the engraved convex portion, an aluminum electrode having a thickness of 0.5 μm to 0.8 μm is formed to form a wiring electrode 26. In this case, if necessary, the intermediate insulating film and the wiring electrode may be laminated to form a multilayer wiring.

The present invention is not limited to the embodiments shown in the drawings, and various modifications can be made without departing from the scope of the invention. For example, as the capacitor insulating film 21, not only a silicon oxide film single layer but also a two-layer or three-layer film containing a silicon nitride film, or a high dielectric film typified by tantalum oxide can be used.

Further, in the above embodiment, the first silicon oxide film 13 after the formation of the first trench-shaped groove 12 is used as it is as the gate oxide film. However, for example, before the formation of the gate electrode after the formation of the capacitor portion. The first silicon oxide film may be removed once, and the gate oxide film may be oxidized again to be formed.

Further, although As was used as the dopant of the capacitor diffusion layer, phosphorus (P) can also be used. In addition to the oblique ion implantation method, a vapor phase diffusion method, a solid phase diffusion method, or the like can be used as the diffusion method.
These methods are particularly effective for deep trench-like grooves. Furthermore, when a silicon oxide film is used as the capacitor insulating film 21, the diffusion layer can be formed even after the capacitor insulating film is formed.

Further, the gate electrode and the like are buried in the first trench-shaped groove 12 by the etch-back method. However, if the first trench-shaped groove 12 can be buried in the first trench-shaped groove in a self-aligning manner, the etch-back method is used. I'm not particular about it.

[0036]

As described in detail above, according to the invention described in claim 1, a semiconductor region is formed in a trench-like groove, and a capacitor and a MOS type field effect which are respectively separated on the side surfaces of the semiconductor region. Since the memory cell including the transistor is provided and the gate electrode of the MOS field effect transistor is formed in the trench-shaped groove portion in a self-aligned manner, it is not necessary to consider the mask alignment margin in forming the channel region. Along with this, high integration of the device is promoted, and the channel length is almost determined at the time of forming the first trench groove, so that there is an advantage that the channel length can be controlled more easily than in the conventional example.

According to the second aspect of the invention, a semiconductor region is formed on the side surface of the convex portion that extends from the inside of the trench-shaped groove and serves as an element of the MOS field effect transistor. Since the capacitor is configured by the conductive electrode formed in the trench-shaped groove via the, the MOS field effect transistor and the vertical memory cell can be configured, and the mask alignment margin is not required. High integration of elements becomes possible.

Further, according to the invention of claim 3, a second trench-shaped groove is formed under the first trench-shaped groove, and a capacitor is formed in the second trench-shaped groove.
A vertical MOS field effect transistor sharing the drain diffusion layer and the gate electrode is formed in the first trench-shaped groove portion, and the gate electrode and the contact hole are formed in a self-aligned manner. It is possible to simplify and shorten the process such as unnecessary.

[Brief description of drawings]

FIG. 1 is a perspective view of an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a cross-sectional view of the same semiconductor memory device.

FIG. 3 is a process sectional view of a first stage of an embodiment of a method of manufacturing a semiconductor memory device of the present invention.

FIG. 4 is a process sectional view of a second stage of the method for manufacturing the semiconductor memory device.

FIG. 5 is a plan view of a conventional trench memory cell.

FIG. 6 is a cross-sectional view of a conventional trench memory cell.

[Explanation of symbols]

 11 silicon substrate 12 first trench groove 13 first silicon oxide film 14 first silicon nitride film 15 second trench groove 16 second silicon oxide film 17 second silicon nitride film 18 isolation insulating film 19 capacitor diffusion Layer 20 Drain diffusion layer 21 Capacitor insulating film 22 Plate electrode 23 First interlayer insulating film 24 Gate electrode 25 Second interlayer insulating film 26 Wiring electrode

Claims (3)

[Claims] 1. A semiconductor substrate surface having a first conductivity type and having a plurality of convex portions sandwiched by a plurality of trench-shaped grooves and electrically isolated from each other, wherein An insulating film formed on at least a part and a semiconductor region having a second conductivity type formed on at least a part of the side surface, and an insulating film formed on the side surface of the convex portion sandwiched by the semiconductor region (or these semiconductor regions); A MOS type field effect transistor configured by embedding a gate electrode embedded in the trench-shaped groove so as to be in contact with the opposite side surfaces inside the trench-shaped groove portion via the insulating film; A semiconductor memory device, comprising: a charge storage portion formed in a trench-shaped groove portion below a conductivity type semiconductor region, and one of the conductive electrodes being connected to the second conductivity type semiconductor region. 2. A semiconductor region of the second conductivity type, wherein the charge storage portion extends inside the trench-shaped groove portion and is formed on a side surface of a convex portion which is an element of the MOS field effect transistor. The semiconductor memory device according to claim 1, comprising a second conductive type semiconductor region and a conductive electrode formed inside the trench-shaped groove portion with an insulating film interposed therebetween. 3. A trench-like groove is formed on the surface of the first conductivity type semiconductor substrate, and an insulating film having a diffusion resistance is formed on a side surface inside the trench-like groove to self-align with the trench-like groove. Forming a groove on the surface of the trench, and selectively forming an element isolation region on the surface of the trench; and forming a charge storage region inside the trench-like groove below the insulating film, and forming an electrode on one of the charge storage regions. Connecting to a second conductor type semiconductor region formed on the surface of the semiconductor substrate in contact with the lower portion of the insulating film, and interposing the insulating film on the facing side surface inside the trench-shaped groove where the insulating film is removed. The step of forming a gate electrode by embedding it in the trench-shaped groove so that it is in contact with each other, and the second conductivity type semiconductor region formed on the upper surface of the convex portion sandwiched between the plurality of trench-shaped grooves. Connected And a step of forming wiring electrodes as described above, and a method of manufacturing a semiconductor memory device.