JPH0513709A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device which has such circuit constitution that it reduces the wiring resistance of a bit line discharge path to shorten the sense time of a semiconductor storage device (DRUM) and does not incur the increase of the chip area. CONSTITUTION:A region where the wiring of the same wiring layer as a column switch control line (CSL) becomes possible by narrowing the wiring interval of a column switch control line (CSL) more than the interval of a column switch 11 is provided on a memory cell array region 2, and an earth wire 14 is wired to cover the region and a word line snap region 10, and these and the common source line for a sense amplifier circuit row region 4 are connected through a sub sense amplifier driving circuit, whereby the wiring resistance of a bit line discharge path can be made small without incurring the increase of a chip area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a highly integrated semiconductor memory device such as a DRAM.

[0002]

2. Description of the Related Art Among semiconductor memory devices in which MOS transistors are integrated, DRAM is most suitable for high integration because it occupies a small memory cell area. Recently, the minimum processing size is 0.
A 16M bit DRAM with a size of 6 μm or less has been announced domestically and internationally, and its mass production is close. In such a highly integrated DRAM, pursuing high speed only by improving the switching speed of the MOS transistor due to miniaturization has reached its limit, and further improvement in high speed is required. DR
One of the major obstacles to speeding up AM is the sense time of the sense amplifier. The sense time is greatly influenced by the data pattern written in the memory array, and the access time is defined by the data pattern having the longest sense time. This situation is described in Japanese Patent Laid-Open No. 3-16082. In the configuration described in this publication, since the discharge current paths from the bit line are provided in multiple directions, the wiring resistance of the discharge path can be equivalently reduced, and the clamp potential of the bit line discharge path can be lowered.
The bit line discharge time constant is reduced, and the sensing time can be shortened.

The following is a description of the conventional invention with reference to the drawings.
And will be described in detail. FIG. 4 is a circuit diagram of the DRAM of the present invention.
The structure of the core circuit part centering on the amplifier is shown.
Bit line pair BL, / BL (BL₀, / BL₀, BL₁, /
BL₁, ...) and word line WL (WL₀, WL₁, ...)
Memory cells M (M₁₁, M
₁₂, ...) 1 is arranged. Each bit line pair BL, / B
L is a MOS transistor (Q₁, Q₂), (Q₃, Q_Four),
A dynamic sense amplifier circuit SA (SA
₁, SA₂, ...) 3 is connected to the MOS transistor
(Q₁₁, Q₁₂), (Q₁₃, Q₁₄), ... column
Connected to input / output lines I / O and / I / O via switch 11.
Has been. The column switch 11 is a column decoder 12
Column select line CSL (CSL₀, CS
L₁, ...) signals. Sense amplifier circuit
The common source wiring / SAN of the MOS transistor of 3 is
A MOS transistor for driving the sense amplifier circuit SA
Dista Q₉Main sense amplifier drive circuit whose main component is
8 and a MOS transistor (Q_{twenty one}, Q_{twenty two}, ...)
Connected to the sub-sense amplifier drive circuit 9 as a component
There is. These sense amplifier drive circuits are
Provided in the main sense amplifier drive circuit 8 arranged at the end.
Row block selection signal RBS and sense amplifier activation
Controlled by a logic circuit that receives the sexualization signal SEN
It M for drive circuit activation in the main sense amplifier drive circuit 8
OS transistor Q₉The source line of is grounded. Well
In addition, the sub-sense amplifier drive circuit 9 has two sense amplifier circuits.
It is placed in the space sandwiched between the road areas and drives in this drive circuit.
MOS transistor Q for dynamic circuit activation_{twenty one}, Q_{twenty two}Source of
The lines pass through the word line snap area 10 parallel to the bit lines.
Grounded.

As the resistance value of / SAN, the drive transistor Q ₉ of the main sense amplifier drive circuit 8 and the drive transistors Q ₂₁ , Q _{22 of the} sub sense amplifier drive circuit 9 are used.
ON resistance of / SAN wiring resistance R ₁ , R ₂ ,
R ₂₁ and R ₂₂ are conceivable. The ON resistance of the former transistor is mainly determined by the gate width of each transistor. Compared to the gate width of the driver transistor Q ₉ of the main sense amplifier driving circuit 8, the gate width of the driver transistor Q _21, Q ₂₂ of the sub-sense amplifier driving circuit 9 can not be increased on the layout area, Q _21, Q ₂₂ each The on-resistance becomes larger than the on-resistance of Q ₉ . However, as the DRAM becomes highly integrated, the word line becomes longer and the snap region 10 per word line also increases, so that a large number of sub-sense amplifier drive circuits 9 can be provided, and the sub-sense amplifier provided therein can be provided. A driving transistor Q ₂₁ arranged in parallel with the driving circuit 9,
Q _22, the total on-resistance of ... it becomes possible to reduce. Regarding the wiring resistance of the sub sense amplifier driving circuit 9, the wiring width of the sub sense amplifier driving circuit 9 is smaller and the wiring length thereof is longer than that of the main sense amplifier driving circuit 8. Similarly, the individual values of R ₂₁ , R ₂₂ , ... Are larger than those of R ₁ and R ₂ , but it is possible to reduce the total wiring resistance by arranging a large number of wirings in parallel. The discharge time constant of can be reduced.

[0005]

However, in order to further shorten the sense time due to the demand for higher speed, the bit line discharge path is provided only in the snap region 10 of the word line as in the prior art. Therefore, there is a possibility that the resistance value cannot be made sufficiently small judging from the area.

The present invention has been made in view of the above problems,
An object of the present invention is to provide a semiconductor memory device in which the discharge time constant of the bit line discharge path is sufficiently reduced to further shorten the sensing time.

[0007]

According to the present invention, a bit line pair coupled to a memory cell, a sense amplifier circuit connected to the bit line pair, and the sense amplifier circuit and a data input / output line are connected. And a first control line for controlling the first switch is wired at an interval narrower than the arrangement interval of the first switches, and the common source line of the sense amplifier circuit is A first power supply line connected via a second switch or a first ground line connected via a third switch, and the first power line or ground line controlling the first switch. In the semiconductor memory device, wiring is provided so as to cover a boundary region between two memory cell array regions adjacent in the column address direction in the same wiring layer as the control line.

According to a second aspect of the present invention, a sense amplifier circuit array including a plurality of CMOS type sense amplifier circuits, the memory cell array arranged corresponding thereto, a common source line of the N type sense amplifier circuit, and a fourth aspect. Second ground line connected by the switch, a common source line of the P-type sense amplifier circuit and a second power supply line connected by the fifth switch, and the fourth and fifth switches. The CMOS
Type sense amplifier circuit rows are arranged at different end portions in the column address direction, and the CMOS type sense amplifier circuit row and the memory cell array arranged corresponding thereto are divided in the column address direction, and the division is performed. The wiring for supplying the same potential as the far side of the second ground line and the power supply line when seen from the boundary region of the CMOS type sense amplifier circuit row region is divided into two adjacent lines in the column address direction. In the semiconductor memory device, wiring is provided so as to cover a boundary region of the memory cell array region.

[0009]

According to the present invention, by making the wiring interval of the first control lines arranged in the memory cell region narrower than the arrangement interval of the column switches, a space where the bit line discharge path can be installed is provided also in the memory cell region. Since the discharge path of the bit line charges is provided not only in the word line snap region but also in the word line snap region and the memory cell region, the wiring resistance can be further reduced and the discharge time constant can be reduced. Therefore, it is possible to shorten the sensing time of the sense amplifier circuit.

[0010]

(Embodiment 1) FIG. 1 is a plan view of a DRAM having the structure of a first embodiment of the present invention, and FIG. 1 (a) is a memory cell array region 2 composed of a plurality of memory cells and a sense amplifier circuit. 2 shows a memory area in which the sense amplifier circuit row area 4 and the sense amplifier circuit row area 4 are arranged in a matrix. DRAM
Input / output of data is controlled by the row decoder 7 to select the word 6 line, the column decoder 12 to select the column switch control line CSL, and the column switch control line CSL selected from the column switches of the MOS transistors. This is done by turning on ones and connecting the bit lines to the input / output lines. The column switch control lines CSL are normally wired at the arrangement intervals of the column switches, but since it is only necessary to input the selection signal to the gate of the MOS transistor which is the column switch, the column switch control line CSL on the memory cell array region 2 is required. The CSL is wired so as to be narrower than the arrangement interval of the column switches.

In recent DRAMs, in order to prevent the delay due to the narrow line width of the word lines, metal wirings are arranged in parallel with the word lines and contact with the word lines is made at appropriate intervals. A region for making this contact is called a word line snap region 10. The memory area is defined by the word line snap area 10 and the memory cell array area 2
And the sense amplifier circuit array is also divided and arranged as the sense amplifier circuit array region 4 accordingly. Conventionally, the column switch control lines CSL are laid out at intervals of the column switches on the memory cell array region 2,
Wiring using the same wiring layer as the column switch control line CSL (for example, second layer aluminum) was possible only in the word line snap region 10. However, according to the configuration of the present invention, the column switch control line CS is provided not only on the word line snap area 10 but also on a part of the memory cell array area 2.
Wiring in the same wiring layer as L is possible.

FIG. 1 (b) is an enlarged view of the hatched portion in FIG. 1 (a). The column switch control line C is arranged at an interval l ₁ narrower than the column switch arrangement interval l _{2 in the} sense amplifier circuit row region 4.
SL is wired, and not only the word line snap region 10 but also the memory cell array region 2 is provided with a wirable region of the same wiring layer as the column switch control line CSL (for example, second layer aluminum). Although FIG. 1A shows that five column switch control lines CSL are wired to the memory cell array region 2, several tens of column switch control lines are actually wired to the memory cell region 2. ing.

FIG. 2 is a circuit configuration diagram centering on the sense amplifier according to the configuration of the first embodiment of the present invention.

An NMOS type sense amplifier circuit 3 is connected to a drive circuit for driving the sense amplifier. The sense amplifier drive circuit includes a main sense amplifier drive circuit 8 provided at an end of a memory area and a sense circuit. The sub-sense amplifier drive circuit 9 is provided at the end of the amplifier circuit row region 4. The main sense amplifier drive circuit 8 includes a row block selection signal RBS and a sense amplifier activation signal SE.
It is constituted by a logic circuit for taking a logical product with N and a MOS transistor switch Q ₉ which is turned on as a result of the logical operation. The sub-sense amplifier drive circuit 9 is composed of MOS transistor switches Q ₂₁ , Q ₂₂ , ... Which are turned on in synchronization with the switch Q ₉ .

In the read operation, first, the word line 6 is selected, the charge of the memory cell 1 connected to the selected word line is read to the bit line, and then the main and sub sense amplifier drive circuits 8 and 9 are read. MOS transistor switch Q
_The sense amplifier circuit 3 is activated by turning on ₉ , Q ₂₁ , Q _22, ... And the potential difference between the bit lines BL and / BL is amplified. Bit line BL, / BL is column switch 1
Only the column switches connected to the input / output lines I / O and / I / O via 1 and connected to the column switch control line CSL selected by the column decoder 12 are turned on, and the potential of the bit line is changed. Is output to the input / output line and input to the I / O buffer 13.

To shorten the sensing time, the wiring resistance of the bit line discharge path / SAN may be reduced. The source line of the sub sense amplifier drive circuit 9 is the column switch control line CSL.
_Vss wired in the same wiring layer as (for example, second layer aluminum)
The column switch control line C is connected to the ground line 14.
When SL is wired toward the center of the memory cell array region 2 with a narrower spacing than the column switch arrangement interval, the column switch control line CS is provided at the end of the memory cell array region 2.
There is a region where the same wiring layer as L can be wired, and V _SS ground line 1
4 are wired so as to cover the word line snap region 10 and the ends of the memory cell array region 2 above and below it.

By wiring the V _SS ground line 14 in this way,
Bit line discharge path / SA without increasing chip area
It is possible to keep the wiring resistance of N lower than before. Since the MOS transistors Q ₂₁ , Q ₂₂ , ... Which are the constituent elements of the sub-sense amplifier drive circuit 9 are installed between the divided sense amplifier circuit row regions 4, the chip area is not increased.

(Embodiment 2) FIG. 3 is a circuit configuration diagram centering on a CMOS type sense amplifier according to the configuration of the second embodiment of the present invention.

The CMOS type sense amplifier circuit is composed of an N type sense amplifier circuit 3n and a P type sense amplifier circuit 3p, and their respective common source lines / SAN are connected to main sense amplifier drive circuits 8n and 8p, respectively. In this configuration, the bit line farther from the main sense amplifier drive circuit has a larger wiring resistance in the discharge path, which causes a problem of voltage clamping.

To solve this, the common source wiring / SAN of each of the N-type and P-type sense amplifier circuits 3n and 3p
The sub sense amplifier driving circuits 9n and 9p are connected to the word line snap region 10 and the V _SS ground line 14 and the V _CC power line 15 are connected to the word line snap region 10.
However, the sub sense amplifier driving circuits 9n and 9p, the V _SS ground line 14, and the V _CC power supply line 1 are provided between the two sense amplifier circuit row regions 4 and the memory cell array region 2.
In the case of wiring 5, the possibility of increasing the chip area must be considered. Therefore, FIG. 3 shows a configuration in which the wiring resistance of the discharge path of the bit line far from the main sense amplifier drive circuit is efficiently reduced. Main sense amplifier drive circuit 8n, 8p
Are arranged at both ends of the memory area and are far from the main sense amplifier drive circuit 8n, and a sub sense amplifier drive circuit 9n is installed between the two sense amplifier circuit row areas 4 and far from the main sense amplifier drive circuit 8p. A sub sense amplifier drive circuit 9p is provided between the two sense amplifier circuit row regions 4. The sub sense amplifier drive circuit 9n is connected to the V _SS ground line 14, and the sub sense amplifier drive circuit 9p is connected to the V _CC power supply line 15. Other configurations are similar to those in the case of FIG.

Although the first embodiment has been described by using the NMOS type sense amplifier circuit, it is also possible to use the PMOS type sense amplifier. Basically, the same circuit configuration may be used, but it is not the V _SS ground line but the V _CC power supply line that is connected to the sub sense amplifier drive circuit.

Furthermore, when wiring the column control line CSL narrower than the space between the column switches, it is not necessary to narrow it toward the center of the memory cell array region 2, and it may be narrowed toward any position of the memory cell array.

[0023]

According to the present invention, the chip area is increased by arranging the ground line and the power line of the bit line discharge path so as to cover not only the word line snap region but also the end portion of the memory cell region. The wiring resistance of the bit line discharge path can be reduced without any need, the sensing time can be shortened as compared with the conventional case, and a high-speed DRAM can be obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram centering on a sense amplifier of the semiconductor memory device of the embodiment.

FIG. 3 is a semiconductor memory device C according to a second embodiment of the present invention.
Circuit diagram centered on MOS type sense amplifier

FIG. 4 is a circuit configuration diagram centering on a sense amplifier circuit of a conventional semiconductor memory device.

[Explanation of symbols]

1 memory cell 2 Memory cell array area 3 sense amplifier 4 Sense amplifier circuit row area 6 word lines 7 Row decoder 8 Main sense amplifier drive circuit 9 Sub-sense amplifier drive circuit 10 word line snap area 11 Column switch 12 column decoder 14 Ground wire 15 power line

Claims (2)

[Claims] 1. A bit line pair coupled to a memory cell, a sense amplifier circuit connected to the bit line pair, and a first switch for connecting the sense amplifier circuit and a data input / output line. A first control line for controlling the first switch is provided at an interval narrower than an arrangement interval of the first switch, and a common source line of the sense amplifier circuit is provided via a second switch. The first power line or the first switch is connected to a first ground line via a third switch,
The power supply line or the ground line of the first switch is wired in the same wiring layer as the first control line for controlling the first switch so as to cover the boundary region between two memory cell array regions adjacent in the column address direction. Semiconductor memory device. 2. A sense amplifier circuit row composed of a plurality of CMOS type sense amplifier circuits, a memory cell array arranged corresponding thereto, a common source line of the N type sense amplifier circuit and a fourth switch. A second ground line, a common source line of the P-type sense amplifier circuit and a second power supply line connected by a fifth switch, and the fourth and fifth switches are of the CMOS type. The sense amplifier circuit rows are arranged at different end portions in the column address direction, and the CMOS type sense amplifier circuit row and the memory cell array arranged corresponding thereto are divided in the column address direction, and the division is performed. Wiring for supplying the same potential as the far side of the second ground line and the power supply line when viewed from the boundary region of the CMOS type sense amplifier circuit row region,
A semiconductor memory device, characterized in that wiring is provided so as to cover a boundary region between two divided memory cell array regions adjacent to each other in a column address direction.