JPH05129344A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To reduce a source resistance, to reduce the component in the horizontal direction of a channel directly under a gate electrode and to enhance the breakdown strength of a drain gate by a method wherein the gate electrode is arranged so as to be close to a source electrode in a field-effect transistor wherein the gate electrode has been formed inside a recess. CONSTITUTION:A recessed part 8 is formed on the face of a substrate 1 near a source electrode 16 formed on the surface of the substrate 1; a gate electrode 19 is formed on the sidewall face on the side of the source electrode 16 in the recessed part 8; a drain electrode 17 is formed on the bottom face of the recessed part 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor and a method of manufacturing the same, and more particularly to a field effect transistor having a reduced parasitic resistance and an improved breakdown voltage.

[0002]

2. Description of the Related Art FIG. 6 shows a conventional field effect transistor (F
ET) is a cross-sectional view showing a structure, in which 1 is a semi-insulating semiconductor substrate, and on this semi-insulating semiconductor substrate 1, a non-doped GaAs buffer layer 2 and a non-doped I substrate are provided.
An nGaAs channel layer 3, an n ⁺ AlGaAs electron supply layer 4, and an n ⁺ GaAs cap layer 5 are sequentially stacked, and the n ⁺ AlGaAs electron supply layer 4 and non-doped InGaA are formed.
The two-dimensional electron gas layer 10 having a high mobility formed in the channel layer 3 has a heterojunction with the s-channel layer 3 to perform a high-speed operation, so-called HEMT (H
igh electron mobility transistor) structure. Reference numeral 9 is a gate electrode arranged in a recess 8 formed in the n ⁺ GaAs cap layer 5, and the concentration of the two-dimensional electron gas layer 10 is changed by the voltage applied to the gate electrode 9. FET operation is performed. Reference numerals 6 and 7 denote a source electrode and a drain electrode formed on the surface of the cap layer 5 near the recess 8. The cap layer 5 serves to make ohmic contact with each electrode.

Next, the operating principle will be described. In the field effect transistor configured as described above, n ⁺ A
The electrons of the 1GaAs electron supply layer 4 move to the side of the channel layer 3 where energy is low across the heterojunction, form a region with a high electron concentration, that is, a two-dimensional electron gas layer 10, and accumulate in this two-dimensional electron gas layer 10. The generated electrons are controlled by the voltage applied to the gate electrode 9 to perform the FET operation. At this time, the electron supply layer 4 in which the depletion layer spreads over the entire role serves as an insulating film of the MOS.

By the way, in a field effect transistor having a recess, the structure other than the channel region is made thicker than the thickness of the surface depletion layer to reduce the source resistance. The source parasitic resistance R _S in this structure is almost determined by the portion surrounded by the source 6 side edge of the recess 8, the extension line of the recess 8 bottom surface and the gate 9 side edge extension line of the source electrode 6, The edge of the recess 8 on the side of the source electrode 6 cannot be very close to the source electrode 6 due to structural restrictions such as mask alignment at the time and a margin of the recess 8 for forming the gate electrode 9. Therefore,
There is a limit to the reduction of the source parasitic resistance R _S.

Further, even if the horizontal component of the electric field of the channel immediately below the gate electrode 9 is relaxed by creating a vertical component as a recess structure, it cannot be sufficiently relaxed because the channel is in the horizontal direction. 9 and drain electrode 7
Easy to break down between. That is, it is difficult to improve the gate-drain breakdown voltage V _gd0 .

[0006]

Since the conventional field effect transistor is constructed as described above, the gate cannot be extremely close to the source, so that the source resistance R _S cannot be reduced and the channel cannot be reduced. The horizontal component of the electric field directly below is large and the electric field concentrates on the edge of the recess on the drain side, and the gate-drain breakdown voltage V _gd0 is _set to the drain resistance R _d.
However, there is a problem that it is difficult to significantly improve the DC (direct current) and RF (high frequency) characteristics of the device for these reasons.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to reduce the source resistance R _S of the FET and to reduce the gate-drain breakdown voltage V _gd0 without deteriorating the drain resistance R _d . It is an object of the present invention to provide a field effect transistor that can be improved and a manufacturing method thereof.

[0008]

According to the field effect transistor and the method of manufacturing the same of the present invention, one main electrode is formed on the surface of a semiconductor substrate and a resist having an opening near the electrode is used to form a recess in the semiconductor substrate. After forming the metal film, the gate electrode is provided on the side wall surface of the recess on the side where the one main electrode is formed by obliquely performing metal deposition, and the other main electrode is formed by using a resist having an opening on the bottom surface of the recess. It is designed to be formed.

A second concave portion is provided on the bottom surface of the concave portion of the semiconductor substrate, and the other main electrode is arranged in the second concave portion.

As the semiconductor substrate, there is a cap layer for ohmic contact of each electrode, the cap layer is formed from the bottom of the recess to the vicinity of the gate electrode, and the other main electrode is on the cap layer. It is designed to be placed in.

Further, a semiconductor layer forming a heterojunction is provided on the lower surface of the cap layer, and the semiconductor layer is provided only between the gate electrode and one main electrode arranged on the surface of the semiconductor substrate around the recess. It is provided.

[0012]

In the present invention, since the gate electrode is provided on the side wall surface of the recess and the source electrode, which is the main electrode, is disposed on the substrate surface in the vicinity of the gate electrode, the structure in which the gate electrode is close to the source electrode causes the source parasitic resistance. R _S can be significantly reduced. Further, since the drain electrode is arranged on the bottom surface of the recess, the horizontal component of the electric field at the drain side edge of the gate electrode is relaxed, and the gate-drain breakdown voltage V _gd0 can be improved.

Since the second concave portion is provided in the concave portion and the drain electrode is arranged in the second concave portion, the gate-drain breakdown voltage V _gd0 can be further improved.

Further, a cap layer for ohmic contact is formed in the recess up to the vicinity of the gate electrode formed on the sidewall surface of the recess, and the drain electrode which is the other main electrode is formed on the bottom surface of the recess of the cap layer. Since this is arranged, the drain resistance can be reduced in addition to the source resistance reduction and the drain breakdown voltage improvement.

Further, the drain electrode is provided on the semiconductor substrate around the recess, and the cap layer is formed in the recess to the vicinity of the gate electrode formed on the sidewall surface of the recess, and the source electrode is provided on the cap layer. , The distance between the source electrode and the gate electrode is reduced to reduce the source resistance, the distance between the drain electrode and the gate electrode is reduced to reduce the drain resistance, and the horizontal direction toward the gate electrode directly below the gate electrode is reduced. The electric field component is reduced and the gate / drain breakdown voltage is improved.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A field effect transistor according to an embodiment of the present invention will be described below with reference to the drawings. In FIG.
The same reference numeral indicates the same or corresponding portion, 19 is a gate electrode formed on the side surface of the recess 8 of the cap layer 5, 16 is on the cap layer 5 near the recess 8 in which the gate electrode 19 is formed, on the flat surface of the substrate. The formed source electrode 17 is a drain electrode formed on the cap layer 5 on the bottom surface of the recess 8.

Next, the function and effect of this embodiment will be described. With the above configuration, the distance from the edge of the recess 8 on the source electrode side to the source electrode 16 is the same as the conventional one, but since the gate electrode 19 is formed close to the source electrode 16, the source parasitic resistance R _S is significantly reduced. To do. Further, since the gate electrode 19 is formed on the side surface of the concave portion 8, the horizontal (drawing left and right method) component of the electric field in the channel directly below the gate electrode 19 becomes small, and the vertical component to the bottom surface of the concave portion 8 (vertical direction in the drawing). Gates
The drain withstand voltage V _gd0 is improved.

Next, a second embodiment of the present invention will be described with reference to the drawings. In this embodiment, the concave portion 8 is further provided on the bottom surface of the concave portion 8.
a is formed, and the drain electrode 17 is arranged on the bottom surface thereof. With such a structure, the source parasitic resistance R _S is similar to that of the first embodiment.
In addition, the vertical (vertical direction in the drawing) component of the electric field is increased and the horizontal component is alleviated by the recess 8a, so that the gate-drain breakdown voltage V _gd0 can be further improved.

Needless to say, the number of steps of the recess may be two or more.

Next, a third embodiment of the present invention will be described with reference to the drawings. In this embodiment, as shown in FIG. 3, the source electrode 16 is provided on the upper surface of the recess 8, the drain electrode 17 is provided on the bottom of the recess 8, and from the side surface of the recess 8 on the drain electrode 17 side to immediately below the gate electrode 19. ^{+ The} GaAs layer 5 is formed.

With this structure, the first
The source parasitic resistance R _S is reduced and the horizontal component of the electric field of the channel immediately below the gate electrode 19 is relaxed by the vertical component in the same manner as in the above embodiment, so that the gate-drain breakdown voltage V _gd0 is improved. , N ⁺ GaAs layer 5 is formed so as to extend to the side wall portion of the drain electrode 17, the gate electrode 19 and the drain electrode 17 are in close proximity to each other, and the drain parasitic resistance R _d can be reduced.

Next, a fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, the drain electrode 17 is provided on the upper surface of the recess 8, the source electrode 16 is provided on the bottom of the recess 8, and the n ⁺ GaAs layer 5 is formed from the side surface of the recess 8 on the source electrode 16 side to immediately below the gate electrode 19. , And the gate electrode 1
9 and the drain electrode 17 are provided with a heterojunction only. With this structure, the gate electrode 1
The vertical component of the channel immediately below 9 is increased, the horizontal component is relaxed to improve the gate breakdown voltage, and the drain resistance is reduced because the drain electrode 17 and the gate electrode 19 are close to each other. Gate electrode 1
9 is formed close to the source electrode 16, the source parasitic resistance R _S can be reduced.

Further, in this embodiment, the heterojunction is formed only between the gate electrode 19 and the drain electrode 17 because if it is formed so as to extend below the source electrode 16 in this structure, DC (direct current) characteristics will not be obtained. It has no effect,
This is because the deterioration of the RF (frequency) characteristics is observed, which is considered to be due to the increase of the source resistance due to the formation of the hetero layer.

Next, a specific method for manufacturing the gate electrode 19 in the first to fourth embodiments will be described with reference to FIG. In FIG. 5, 20 is a semiconductor substrate provided with an active layer, 17a is a drain electrode metal, 19a is a gate electrode metal, 21, 22 and 24 are photoresists.

First, as shown in FIG. 5A, after the source electrode 16 is formed on the semiconductor substrate 20 having an active layer and the like,
A photoresist 21 patterned by photolithography is provided to form a gate electrode.

Next, as shown in FIG. 5B, a recess 8 is formed in the semiconductor substrate 20 by using the photoresist 21 as a mask, and a gate metal 19a is obliquely deposited to form a sidewall of the recess 8 on the source side. A gate electrode 19 is formed on.

Next, as shown in FIG. 5C, unnecessary gate metal 19a and photoresist 21 are removed by a lift-off method.

Next, as shown in FIG. 5D, a photoresist 22 patterned by photolithography is provided to form a drain electrode.

Next, as shown in FIG. 5E, the drain metal 17a is vapor-deposited by using the photoresist 22 as a mask to form the drain electrode 17.

Then, the unnecessary drain electrode metal 17a and the photoresist 22 are removed by the lift-off method.
The FET as shown in FIG. 5 (f) is completed.

In the above first to fourth embodiments,
Having described a HEMT structure with a heterojunction,
It may be a so-called MESFET that does not have a heterojunction.

Further, in the fourth embodiment, the non-doped InGaAs channel layer 3 and n ⁺ forming the heterojunction are formed.
Although the AlGaAs electron supply layer 4 is formed only between the gate electrode 19 and the drain electrode 17 so as to prevent the deterioration of the RF characteristics, it is not always necessary to have such a configuration, and the gate electrode 19 to the source electrode 16 are not necessarily formed. It may be formed.

[0033]

As described above, according to the present invention, the gate electrode is formed on the sidewall surface of the recess, the source electrode is provided on the surface of the semiconductor substrate near the recess, and the drain electrode is provided on the bottom surface of the recess. The source electrode and the gate electrode are close to each other, so that the source resistance can be reduced, and the horizontal component of the electric field directly under the gate electrode is relaxed, so that the gate / drain breakdown voltage is improved.

By providing a second recess in the recess and disposing the drain electrode in the second recess, the horizontal component of the electric field is further relaxed, and the gate-drain breakdown voltage is further improved. There is an effect that can be.

Further, a cap layer for making ohmic contact with each electrode is provided on the surface of the semiconductor substrate, and the cap layer is formed in the concave portion up to the vicinity of the gate electrode provided on the side wall surface of the concave portion. Since the drain electrode is placed on the cap layer, the distance between the source and gate electrodes can be shortened to reduce the source resistance, the horizontal component of the channel directly below the gate electrode can be reduced, and the gate and drain low voltage can be improved. In addition to the above, there is an effect that the distance between the gate and the drain electrode is shortened and the drain resistance can be reduced.

Further, a cap layer for making ohmic contact with each electrode is provided on the surface of the semiconductor substrate, and the cap layer is formed in the concave portion up to the vicinity of the gate electrode provided on the side wall surface of the concave portion. Since the source electrode is arranged on the cap layer,
The distance between the gate electrodes can be shortened to reduce the drain resistance, the horizontal component of the channel directly below the gate electrode can be reduced to improve the gate / drain low voltage, and the distance between the source / drain electrodes can be shortened to reduce the source resistance. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a sectional view showing the structure of a field effect transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view showing the structure of a field effect transistor according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing the structure of a field effect transistor according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing the structure of a field effect transistor according to a fourth embodiment of the present invention.

FIG. 5 is a manufacturing process drawing for explaining the manufacturing method of the gate electrode of the field effect transistor according to the first to fourth inventions of the present invention.

FIG. 6 is a sectional view showing the structure of a conventional field effect transistor (FET).

[Explanation of symbols]

1 semi-insulating semiconductor substrate 2 non-doped GaAs buffer layer 3 non-doped InGaAs channel layer 4 n ⁺ AlGaAs electron supply layer 5 n ⁺ GaAs cap layer 8 recess 8a second recess 10 two-dimensional electron gas layer 16 source electrode 17 drain electrode 17a drain Electrode metal 19 Gate electrode 19a Gate electrode metal 20 Semiconductor substrate provided with active layer 21 Photoresist 22 Photoresist

Claims (5)

[Claims] 1. A semiconductor substrate having a recess on its surface,
In a field effect transistor comprising a main electrode provided on the surface of a semiconductor substrate and serving as a source or drain electrode, and a gate electrode provided in a recess on the surface of the semiconductor substrate, the gate electrode is provided on a sidewall surface of the recess. A field effect transistor, wherein one of the main electrodes is disposed on the bottom surface of the recess. 2. The field effect transistor according to claim 1, wherein the recess has a second recess at a bottom thereof, and one main electrode disposed on the bottom surface of the recess is disposed within the second recess. A field effect transistor characterized by being provided. 3. The field effect transistor according to claim 1, wherein a cap layer for making ohmic contact with each of the electrodes is formed on the surface of the semiconductor substrate, and the cap layer extends from the bottom surface of the recess to the sidewall surface of the recess. A field effect transistor characterized in that it is formed up to the vicinity of the gate electrode, and one main electrode arranged on the bottom surface of the recess is arranged on the cap layer. 4. The field effect transistor according to claim 3, further comprising a semiconductor layer forming a heterojunction surface on the lower surface of the cap layer, the semiconductor layer being on the surface of the semiconductor substrate around the gate electrode and the recess. A field effect transistor characterized in that it is provided only between one of the arranged main electrodes. 5. A field effect transistor comprising a semiconductor substrate on which an active layer is formed, a recessed portion, a gate electrode formed in the recessed portion, and a main electrode serving as a source or drain electrode formed on the surface of the semiconductor substrate. In the method for manufacturing the method described above, a step of forming one main electrode on the surface of the semiconductor substrate, a step of forming a recess on the surface of the semiconductor substrate using a resist having an opening in the vicinity of the formed main electrode; The step of performing vapor deposition to form a gate electrode on the side wall surface of the concave portion on which the one main electrode is formed, and the metal vapor deposition using a resist having an opening at a predetermined portion of the concave portion bottom surface, and the other on the concave portion bottom surface. A method of manufacturing a field effect transistor, comprising the step of forming a main electrode.