JPH05102190A - Compound-semiconductor heterojunction-gate field-effect transistor - Google Patents

Abstract

PURPOSE:To obtain an FET wherein a sheet carrier concentration is high and the traveling speed of carriers is high by a method wherein a layer composed of a first undoped semiconductor is provided between a channel layer and one barrier layer. CONSTITUTION:A laminated structure where a channel layer 5 composed of a first doped semiconductor has been sandwiched between two layers 4, 6 composed of a first undoped semiconductor is provided; in addition, a barrier 7 composed of a second semiconductor whose composition is different from that of the first semiconductor is provided at the upper layer of the laminated structure. Barrier layers 3, 7 composed of the second semiconductor whose composition is different from that of the first doped semiconductor are provided at the upper layer and the lower layer of the channel layer 5 composed of the first doped semiconductor; in addition, a layer composed of the first undoped semiconductor layer is provided between one of the barrier layers and the channel layer 5. Thereby, it is possible to obtain a compound-semiconductor heterojunction-gate FET which is provided with a high sheet carrier concentration and in which the traveling speed of carriers is high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor heterojunction gate field effect transistor.

[0002]

2. Description of the Related Art Most of integrated circuits using compound semiconductors such as GaAs are composed of Schottky junction (MES) field effect transistors (FETs) which are easy to process. Transconductance gm per unit channel width of FET including MESFET can be expressed as follows in the velocity saturation region. gm = V _s ε _s / h V _s : saturation rate ε _s : dielectric constant h: depletion layer width That is, in order to improve gm and further improve the performance of the integrated circuit, the depletion layer immediately below the gate electrode is used. It is necessary to make the width h smaller. In the case of an FET having a doped channel layer such as MESFET, it is possible to reduce the depletion layer width h by improving the carrier concentration of the channel layer, but at the same time, the tunnel current component at the gate junction increases and the gate breakdown voltage decreases. The problem of doing. Further, in the highly doped semiconductor layer, there is a problem that the traveling speed of carriers is reduced due to scattering of ionized impurities. In order to solve the former problem, a structure has been proposed in which a barrier layer such as an i-A1GaAs layer is inserted between the metal gate electrode and the doping channel layer. FET having this structure is
Referred to as MT or DC-HIGFET. In this case, a high gate breakdown voltage can be obtained. On the other hand, the latter problem is not solved at all.

On the other hand, in the FET using the non-doped channel layer, high mobility can be expected because it does not undergo ionized impurity scattering. An example of this is HEMT. However, in the case of HEMT, there is a drawback that the sheet carrier concentration Ns of the two-dimensional electron gas layer is saturated when the impurity doping amount of the carrier supply layer is increased to some extent, and high driving performance cannot always be obtained. In this respect, an FET with a doped channel layer
Can achieve higher sheet carrier density,
Although it is considered to be advantageous, it is inferior to the structure using the undoped channel layer in terms of mobility or carrier traveling speed as described above.

[0004]

As described above, all of the FETs proposed hitherto have a serious problem and cannot achieve a desired high performance. The present invention has been made in view of the above points, and provides an FET having a high sheet carrier concentration and a high carrier traveling speed.

[0005]

A compound semiconductor heterojunction gate FET according to the present invention is a barrier layer composed of at least an upper layer of a channel layer composed of a doped first semiconductor and a second semiconductor having a composition different from that of the first semiconductor. And a layer of undoped first semiconductor between the channel layer and the at least one barrier layer.

[0006]

Operation: Compound semiconductor heterojunction gate FET of the present invention
Is a semiconductor having a composition different from that of the channel layer, such as A1 _0.3 G, on the surface side of the channel layer made of n-GaAs.
By having a barrier layer made of a _0.7 As, a high gate forward / reverse breakdown voltage is exhibited despite having a heavily doped channel layer. In addition, the high-concentration channel layer is composed of two undoped semiconductor layers having the same composition as the channel layer, or a barrier layer made of an undoped semiconductor layer having the same composition as the channel layer and a semiconductor having a different composition from the channel layer. It is sandwiched between. When the high-concentration channel layer thickness is small, a V-type potential is generated centering on the channel,
Subbands are formed. That is, for example, in the case of an n-type channel layer, the energy that electrons can take is discrete. In the state where a small electric field is applied, many electrons remain in the ground state and travel due to scattering by ionized impurities and the like. , The electron velocity does not increase so much. However, when a high electric field is applied, the electrons transit to a higher-order subband or jump out of the V-type potential and transit to the semiconductor layers on both sides. In any case, since the probability of existence of electrons in the undoped semiconductor layer adjacent to the channel layer is high, a higher electron velocity can be obtained as compared with the case where the undoped semiconductor layer is not provided. Such an effect becomes remarkable when the width of the V-type potential is narrow and steep, that is, when the channel layer is thin and the electron concentration is high. It is desirable that the thickness of the channel layer is 10 nm or less and the electron concentration is 4 × 10 ¹⁸ cm ⁻³ or more, but even if the thickness is 20 nm or less and the electron concentration is 3 × 10 ¹⁸ cm ⁻³ or more, the effect is obtained. Be done. FET
When the gate length is shortened, electrons traveling in a region closer to the interface of the gate electrode can suppress the so-called short channel effect. Therefore, an undoped semiconductor layer of the same composition as the channel layer
It is more desirable to insert the channel layer on the side closer to the interface with the gate electrode. Also, for example, in the case of a structure having a barrier layer made of a semiconductor such as A1 _0.3 Ga _0.7 As having a different composition from the channel layer above and below a channel layer made of a doped semiconductor such as GaAs, an electron V type It runs out of the potential and travels in the barrier layers on both sides, and the electron velocity decreases due to the low electron mobility in A1 _0.3 Ga _0.7 As or the like. By inserting an undoped semiconductor layer of the same composition as the channel between the channel layer and the barrier layer, this problem is avoided. Also in this case, the undoped semiconductor layer having the same composition as the channel layer is more preferably inserted on the side closer to the gate electrode for the above-mentioned reason, but may be inserted on the side far from the gate electrode. Be done.

[0007]

EXAMPLE A compound semiconductor heterojunction gate FET according to an example of the present invention will be described with reference to FIG.

A thickness of about 500 is formed on the semi-insulating GaAs substrate 1.
nm undoped i-GaAs layer 2, i 50 nm thick
-A1 _0.3 Ga _0.7 As barrier layer 3, 10 nm thick i-

GaAs spacer layer 4, thickness 10 nm, n-GaAs channel layer 5 having an electron concentration of 4 × 10 ¹⁸ cm ^-3 , i-GaAs spacer layer 6 having a thickness 10 nm, thickness 30 nm
I-A1 _0.3 Ga _0.7 As barrier layer 7 having a thickness of 5 nm
The -GaAs surface layer 8 is sequentially formed by epitaxial growth. Reference numeral 9 is a WNx gate electrode. 10, 11
Is Si ⁺ Are source / drain regions formed by ion implantation and heat treatment, and 12 and 13 are source / drain electrodes made of AuGe alloy.

In the FET of this embodiment, the thin n-GaAs channel layer 5 having a high electron concentration is used as the i-GaAs layers 4 and 6.
Since it has a structure sandwiched between, it forms a narrow and steep V-shaped potential. Therefore, when the electric field strength increases, i-
The number of electrons traveling in the GaAs layers 4 and 6 increases, and a high electron velocity is obtained. Incidentally, since the n-GaAs layer 5 having a high concentration is included, the sheet electron concentration is also high. When the gate length was 0.3 μm, gm _max showed a high value of ˜700 mS / mm.

The embodiments of the present invention are not limited to the above. For example the barrier layer is i or _{p-A1 x Ga 1-x} As layer (0.
2 ≦ X ≦ 0.4). In addition, the material of the channel layer and the spacer layer may be changed to, for example, an In _x Ga _1-x As layer, in which case i or p-In is used as the barrier layer.
_{An x} A1 _1-x As layer or an A1 _x Ga _1-x As layer can be used. For the substrate or other semiconductor layers,
It is only necessary to select a material corresponding to these. Further, the desired effect can be obtained even if the spacer layer is provided only above or below the channel layer. The gate electrode material is not limited to the WNx, Ti, W, TiW, etc. W _x Si _Y, A1,
Any material may be used as long as it forms a Schottky junction with the compound semiconductor. Similarly, the material for the source / drain electrodes is AuGe.
The material is not limited to the alloy, and any material that can form a good ohmic junction with the source / drain regions may be used. The source / drain regions may be formed using ion implantation other than Si, or may be formed using an epitaxial growth method. In addition, the parameters such as the carrier concentration and the film thickness in the embodiments are merely examples, and it is sufficient that the same effects can be obtained.

[0012]

As described above, according to the present invention, a compound semiconductor heterojunction gate FET having a high sheet carrier concentration and a high carrier traveling speed can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view showing a compound semiconductor heterojunction gate FET according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Semi-insulating GaAs substrate 2 ... i-GaAs layer 3, 7 ... i-A1 _0.3 Ga _0.7 As barrier layer 4, 6 ... i
-GaAs spacer layer 5 ... n-GaAs channel layer 8 ... i-GaAs surface layer 9 ... WNx gate electrodes 10, 11 ... Source / drain regions 12, 13 ... Source / drain electrodes

Claims (4)

[Claims] 1. A laminated structure in which a channel layer made of a doped first semiconductor is sandwiched between two layers made of an undoped first semiconductor, and the first semiconductor is provided on an upper layer of the laminated structure. And a compound semiconductor heterojunction gate field effect transistor having a barrier layer made of a second semiconductor having a different composition. 2. A compound semiconductor heterojunction gate field effect transistor having a barrier layer made of a second semiconductor having a composition different from that of the first semiconductor above and below a channel layer made of a doped first semiconductor,
A compound semiconductor heterojunction gate field effect transistor, wherein an undoped layer of the first semiconductor is inserted between at least one of the barrier layers and the channel layer. 3. The first semiconductor is n-type GaAs, and the second semiconductor is A1 _x Ga _{1 -x} As (0.2 ≦
X ≦ 0.4), wherein
A compound semiconductor heterojunction gate field effect transistor as described. 4. A channel layer made of the first doped semiconductor having a thickness of 10 nm or less and an electron concentration of 4 × 10 ¹⁸ cm ⁻³ or more. Alternatively, the compound semiconductor heterojunction gate field effect transistor described in 3 above.