JPH05101699A - Memory device - Google Patents

Abstract

PURPOSE:To shorten the read time for memory test. CONSTITUTION:A memory having plural digit lines consists of a noncoincidence detecting circuit (gate 73) which takes output data of plural digit lines as the input, a flip flop 74 where detection of noncoincidence is stored, and a circuit which reads out the result to a data bus 40. With respect to memory test, there is a conventional device which simultaneously writes data in plural memories to shorten the test time at the time of write to memories but reads out contents of memories corresponding to addresses one by one at the time of read of written data. This invented device simultaneously reads out data from plural memories at the time of read of written data to shorten the test time, and the test time reduction effect is increased according as the capacity of memories to be tested is larger.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly to a memory circuit having a test function.

[0002]

2. Description of the Related Art Conventionally, as one of means for reducing the test time of a memory, there is a circuit for collectively writing the same data to a plurality of memory cells at the time of test, and an example thereof is shown in FIG.

In FIG. 2, a first array 10 is a memory cell block having an array structure in which memory cells are repeatedly connected to each other (hereinafter referred to as array 10).

The four memory cell blocks of the first array 10 to the third array 13 form a memory cell group for 1 bit. Transistors 1 to 4 for selection are connected to the outputs of the digit lines connected to the memory cell blocks of each of the arrays 10 to 13 and the transistors 1 to 4 are connected.
Decode signals Y0 to Y3 are input to the gates of. The transistors 1 to 4 are connected to the output of the write buffer 6 controlled by the write signal WR to the memory cell,
The input of the write buffer 6 is connected to the data bus (D0) 30.

Besides, the transistors 1 to 4 are connected to the input of the read buffer 5 controlled by the data read signal RD of the memory, and the output of the read buffer 5 is connected to the data bus (D0) 30. The circuit configuration as described above is constructed for each bit of the first bit 20 to the eighth bit 27.

Next, the operation of the first bit 10 will be described with reference to FIG. The other bits 1 to 7 have the same operation. At the time of writing, the write buffer 6 becomes active and the read buffer 5 becomes inactive. In this state, the normal write operation selects only one of the decode signals Y0 to Y3 for selecting the digit line, but when performing a batch write to test the memory, these decode signals Y0 to Y3 are selected. Since all the signals are selected, the data can be written in four memory cells at the same time, and the number of write tests can be reduced.

Next, when reading data from the memory, the read buffer 5 becomes active and the write buffer 6 becomes inactive. In this state, one of the decode signals Y0 to Y3 is selected and the data is output to the data bus (D0) 30 via the read buffer 5.

[0008]

As described above, when performing a read test of the same data that has been collectively written,
Since data is read out collectively as in batch writing, if all the decode lines of the decode signals Y0 to Y3 are selected, the output of the digit lines up to each of the arrays 10 to 13 will be overlapped, resulting in accurate reading. The output data cannot be judged. Therefore, during the data read test,
In order to select the decode signals one by one and read the data,
It has the drawback of increasing the test time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory device which can solve the above-mentioned drawbacks, can accurately determine output data, and can be tested in a short time.

[0010]

According to the structure of the present invention, a plurality of digit lines, a transistor for selecting each of the digit lines, a decode signal input terminal for selecting each of the transistors, and the decode signal are connected to a gate. In a memory device having a circuit for inputting or outputting data selected by the selected transistor to and from a data bus, a mismatch detection circuit having the output data of the digit line as an input, and the mismatch detection circuit It has a flip-flop set by an output, a reset signal input terminal of the flip-flop, a read circuit for reading the flip-flop to the data bus, and a read signal output terminal.

[0011]

1 is a block diagram showing a memory device according to an embodiment of the present invention.

In FIG. 1, one embodiment of the present invention is
The array 10 to the fourth array 13 has four memory cell blocks to form a memory cell group for 1 bit, and the output of each digit line connected to the memory cell blocks of the arrays 10 to 13 is The transistors 7 to 10 for selection are connected, and the decode signals Y0 to Y3 are input to the gates of the transistors 7 to 10.

The transistors 7 to 10 are write buffers 7 controlled by a write signal WR to the memory cell.
2 and the input of the write buffer 72 is connected to the data bus (D0) 40. Besides, the transistors 7 to 10 are connected to the input of the read buffer 71 controlled by the data read signal RD of the memory,
The output of the read buffer 71 is the data bus (D0).
40 is connected.

The output of each digit line of the arrays 10 to 13 of the memory cell block is XNO for detecting a mismatch.
It is connected to the R gate 73, and the output of the XNOR gate 73 is connected to the set signal of the flip-flop 74 which holds the mismatch result. Further, the flip-flop 74 has a reset signal FRES for initialization, the output of the flip-flop 74 is connected to the read buffer 75 controlled by the mismatch result read signal MRD, and the output of the match result read buffer 75 is data. It is connected to the bus (D0) 40.

The circuit configuration as described above has bits 30 to 30.
Bits 37 to 37 are configured for each bit.

Next, the operation of the first bit 10 will be described with reference to FIG. 1 (the other bits 31 to 37 have the same operation).

At the time of normal writing, one of the necessary decode signals Y0 to Y3 is selected as described in the conventional example,
Data is written via the write buffer 72. In addition, the decode signal Y necessary for normal reading
One of 0 to Y3 is selected and the data is read out via the read buffer 71.

Next, at the time of testing the memory by batch writing at the time of testing the memory, all the decode signals Y0 to Y3 are selected as described in the conventional example, and the write buffer 72 transfers the data on the data bus to the memory cells. The blocks 10 to 13 are simultaneously written.

When the same batch-written data is read out by batch reading, the flip-flop 74 holding the mismatch result is reset by the reset signal FRES and the output is initialized to "0". Then, the read buffer 71 of the memory cell becomes active, and the write buffer 72 and the flip-flop read buffer 75 become inactive. That is, the data output from the data bus is the output of the digit line selected from only one of the decode signals Y0 to Y3 as in the normal read. For example, the description will be made assuming that the decoder signal Y0 is selected (the operation is the same even if the decoder signals Y1 to Y3 are selected).

When the data of all the memory cells are normal, the data of the array 10 read from the data bus 40 outputs the value equal to the expected value. At this time, array 1
0 to the output of the digit line connected to array 13 is XNOR
The data is input to the gate 73 and a mismatch operation is performed (the same data is written in the arrays 10 to 13 by batch writing).

Here, since the data in the memory cell is normal, the inputs to the XNOR gate 73 are all the same and the data output is "1". The output "1" of the XNOR gate 73 is input to the flip-flop 74, but the flip-flop 74 keeps the reset state and continues to output the initial value "0". When the data output of all the memory cells of the array 10 is completed, the output of the flip-flop 74 is output to the data bus 40 via the output buffer by the read signal MRD, and the value of the data bus is all "1".
Therefore, the contents read from the array 10 and the arrays 11 to 11
It can be seen that the data contents up to the array 13 are the same.

If the memory cell has an abnormality and the abnormal memory cell is among the arrays 11 to 13, the array 10 read from the data bus is read.
Data is equal to the expected value, but the output of the digit line connected to the array 10 to the array 13 input to the XNOR gate 73 is abnormal because the data of the memory cell is abnormal.
Since the gate 73 detects a mismatch, the output at that time is "0". When the output “0” of the XNOR gate 73 is input as the set signal of the flip-flop 74, the flip-flop 74 enters the set state and outputs “1”.

After this state, even if the output of the XNOR gate 73 outputs "1", the flip-flop 74 continues to output "1" in the set state. When the data output of all the memory cells of the array 10 is completed, the flip-flop 7
The output of No. 4 is output to the data bus via the output buffer by the read signal MRD, the output of the normal bit becomes "1", and only the output of the abnormal bit becomes "0".
Becomes Therefore, it is possible to know which bit of the data in the arrays 11 to 13 which has not been read out is abnormal.

If there is an abnormal memory cell in the array 10, the data in that memory cell is output from the data bus and is different from the expected value, so it can be seen that there is an abnormality.

From the above, array 11 to array 13
Since it is possible to perform a test without directly reading the data up to, it is not necessary to read the data from the arrays 11 to 13 by only the number of times of reading the data of the array 10, and the number of times of the test is reduced as compared with the conventional method, resulting in a longer test time. Can be shortened.

In this embodiment, the memory is divided into four blocks, but it may be divided into two or more blocks. Further, other circuit configurations such as a decoder type, a read buffer, a write buffer, a mismatch detection circuit, and a flip-flop have the same effect.

As described above, the memory read circuit of this embodiment is set in the semiconductor memory having a plurality of digit lines by the mismatch detection circuit having the plurality of digit lines as inputs and the output of the mismatch detection circuit. A flip-flop, a reset signal input terminal of the flip-flop, a circuit for reading the output of the flip-flop to the data bus, and a read signal output terminal.

As a result, in this embodiment, one of the data outputs of the plurality of digit lines is read by the conventional method,
By comparing and detecting the outputs of the remaining digit lines by the mismatch detection circuit, the number of memory read tests is reduced.

[0029]

As described above, according to the memory device of the present invention, the number of tests can be reduced because the read operation can be performed collectively during the read test of the memory cells, and the test time can be shortened as compared with the conventional read operation. effective.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory device having a batch write function according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a conventional memory device.

[Explanation of symbols]

 1 to 4, 7 to 10 transistors 5, 6, 71, 72, 75 buffer 73 XNOR gate 74 flip flop Y0 to Y3 decode signal 30, 40 data bus WR memory write signal RD memory read signal MRD flip flop read signal FRES flip flop reset signal

Claims (1)

[Claims] 1. A plurality of digit lines, a transistor for selecting each of the digit lines, a decode signal input terminal for selecting each of the transistors, and a data selected by the transistor whose gate is connected to the decode signal. A memory device having a circuit for inputting or outputting to / from a data bus, a mismatch detection circuit having the output data of the digit line as an input, and a flip-flop set by the output of the mismatch detection circuit,
A memory device having a reset signal input terminal of the flip-flop, a read circuit for reading the flip-flop to the data bus, and a read signal output terminal.